WebSVN – HelenOS – Diff – /trunk/kernel/arch/ia64/src/asm.S


#
# Copyright (c) 2005 Jakub Jermar
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# - Redistributions of source code must retain the above copyright
#   notice, this list of conditions and the following disclaimer.
# - Redistributions in binary form must reproduce the above copyright
#   notice, this list of conditions and the following disclaimer in the
#   documentation and/or other materials provided with the distribution.
# - The name of the author may not be used to endorse or promote products
#   derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
 
#include <arch/register.h>
 
.text
 
/** Copy memory from/to userspace.
 *
 * This memcpy() has been taken from the assembler output of
 * the generic _memcpy() and modified to have the failover part.
 *
 * @param in0 Destination address.
 * @param in1 Source address.
 * @param in2 Number of byte to copy.
 */
.global memcpy
.global memcpy_from_uspace
.global memcpy_to_uspace
.global memcpy_from_uspace_failover_address
.global memcpy_to_uspace_failover_address
memcpy:
memcpy_from_uspace:
memcpy_to_uspace:
	alloc loc0 = ar.pfs, 3, 1, 0, 0
 
	adds r14 = 7, in1
	mov r2 = ar.lc
	mov r8 = in1 ;;
	and r14 = -8, r14 ;;
	cmp.ne p6, p7 = r14, in1
(p7)	br.cond.dpnt 3f	;;
0:
	cmp.ne p6, p7 = 0, in2
(p7)	br.cond.dpnt 2f	;;
(p6)	adds r14 = -1, in2
(p6)	mov r16 = r0
(p6)	mov r17 = r0 ;;
(p6)	mov ar.lc = r14
1:
	add r14 = r16, r8
	add r15 = r16, in0
	adds r17 = 1, r17 ;;
	ld1 r14 = [r14]
	mov r16 = r17 ;;
	st1 [r15] = r14
	br.cloop.sptk.few 1b ;;
2:
	mov ar.lc = r2
 
	mov ar.pfs = loc0
	br.ret.sptk.many rp
3:
	adds r14 = 7, in0 ;;
	and r14 = -8, r14 ;;
	cmp.eq p6, p7 = r14, in0
(p7)	br.cond.dptk 0b
	shr.u r18 = in2, 3 ;;
	cmp.ne p6, p7 = 0, r18
(p7)	br.cond.dpnt 5f	;;
(p6)	adds r14 = -1, r18
(p6)	mov r16 = r0
(p6)	mov r17 = r0 ;;
(p6)	mov ar.lc = r14
4:
	shladd r14 = r16, 3, r0
	adds r16 = 1, r17 ;;
	add r15 = r8, r14
	add r14 = in0, r14
	mov r17 = r16 ;;
	ld8 r15 = [r15] ;;
	st8 [r14] = r15
	br.cloop.sptk.few 4b
5:
	and r15 = 7, in2
	shladd r14 = r18, 3, r0
	mov r16 = r0
	mov r18 = r0 ;;
	cmp.eq p6, p7 = 0, r15
	add in0 = r14, in0
	adds r15 = -1, r15
	add r17 = r14, r8
(p6)	br.cond.dpnt 2b	;;
	mov ar.lc = r15
6:
	add r14 = r16, r17
	add r15 = r16, in0
	adds r16 = 1, r18 ;;
	ld1 r14 = [r14]
	mov r18 = r16 ;;
	st1 [r15] = r14
	br.cloop.sptk.few 6b ;;
	mov ar.lc = r2
 
	mov ar.pfs = loc0
	br.ret.sptk.many rp
	
memcpy_from_uspace_failover_address:
memcpy_to_uspace_failover_address:
	mov r8 = r0			/* return 0 on failure */
	mov ar.pfs = loc0
	br.ret.sptk.many rp
 
.global memsetb
memsetb:
	br _memsetb
 
.global cpu_halt
cpu_halt:
	br cpu_halt
 
.global panic_printf
panic_printf:
	{
		br.call.sptk.many b0=printf
	}
	br halt
 
/** Switch to userspace - low level code.
 *
 * @param in0 Userspace entry point address.
 * @param in1 Userspace stack pointer address.
 * @param in2 Userspace register stack pointer address.
 * @param in3 Userspace address of thread uspace_arg_t structure.
 * @param in4 Value to be stored in IPSR.
 * @param in5 Value to be stored in RSC.
 */
.global switch_to_userspace
switch_to_userspace:
	alloc loc0 = ar.pfs, 6, 3, 0, 0
	rsm (PSR_IC_MASK | PSR_I_MASK)		/* disable interruption collection and interrupts */
	srlz.d ;;
	srlz.i ;;
	
	mov cr.ipsr = in4
	mov cr.iip = in0
	mov r12 = in1
 
	xor r1 = r1, r1
	
	mov loc1 = cr.ifs
	movl loc2 = PFM_MASK ;;
	and loc1 = loc2, loc1 ;;
	mov cr.ifs = loc1 ;;			/* prevent decrementing BSP by rfi */
 
	invala
	
	mov loc1 = ar.rsc ;;
	and loc1 = ~3, loc1 ;;			
	mov ar.rsc = loc1 ;;			/* put RSE into enforced lazy mode */
 
	flushrs ;;
	
	mov ar.bspstore = in2 ;;
	mov ar.rsc = in5 ;;
	
	mov r8 = in3
	
	rfi ;;
 

Rev 1787	Rev 2071
1	#	1	#
2	# Copyright (C) 2005 Jakub Jermar	2	# Copyright (c) 2005 Jakub Jermar
3	# All rights reserved.	3	# All rights reserved.
4	#	4	#
5	# Redistribution and use in source and binary forms, with or without	5	# Redistribution and use in source and binary forms, with or without
6	# modification, are permitted provided that the following conditions	6	# modification, are permitted provided that the following conditions
7	# are met:	7	# are met:
8	#	8	#
9	# - Redistributions of source code must retain the above copyright	9	# - Redistributions of source code must retain the above copyright
10	# notice, this list of conditions and the following disclaimer.	10	# notice, this list of conditions and the following disclaimer.
11	# - Redistributions in binary form must reproduce the above copyright	11	# - Redistributions in binary form must reproduce the above copyright
12	# notice, this list of conditions and the following disclaimer in the	12	# notice, this list of conditions and the following disclaimer in the
13	# documentation and/or other materials provided with the distribution.	13	# documentation and/or other materials provided with the distribution.
14	# - The name of the author may not be used to endorse or promote products	14	# - The name of the author may not be used to endorse or promote products
15	# derived from this software without specific prior written permission.	15	# derived from this software without specific prior written permission.
16	#	16	#
17	# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	#	27	#
28		28
29	#include <arch/register.h>	29	#include <arch/register.h>
30		30
31	.text	31	.text
32		32
33	/** Copy memory from/to userspace.	33	/** Copy memory from/to userspace.
34	*	34	*
35	* This memcpy() has been taken from the assembler output of	35	* This memcpy() has been taken from the assembler output of
36	* the generic _memcpy() and modified to have the failover part.	36	* the generic _memcpy() and modified to have the failover part.
37	*	37	*
38	* @param in0 Destination address.	38	* @param in0 Destination address.
39	* @param in1 Source address.	39	* @param in1 Source address.
40	* @param in2 Number of byte to copy.	40	* @param in2 Number of byte to copy.
41	*/	41	*/
42	.global memcpy	42	.global memcpy
43	.global memcpy_from_uspace	43	.global memcpy_from_uspace
44	.global memcpy_to_uspace	44	.global memcpy_to_uspace
45	.global memcpy_from_uspace_failover_address	45	.global memcpy_from_uspace_failover_address
46	.global memcpy_to_uspace_failover_address	46	.global memcpy_to_uspace_failover_address
47	memcpy:	47	memcpy:
48	memcpy_from_uspace:	48	memcpy_from_uspace:
49	memcpy_to_uspace:	49	memcpy_to_uspace:
50	alloc loc0 = ar.pfs, 3, 1, 0, 0	50	alloc loc0 = ar.pfs, 3, 1, 0, 0
51		51
52	adds r14 = 7, in1	52	adds r14 = 7, in1
53	mov r2 = ar.lc	53	mov r2 = ar.lc
54	mov r8 = in1 ;;	54	mov r8 = in1 ;;
55	and r14 = -8, r14 ;;	55	and r14 = -8, r14 ;;
56	cmp.ne p6, p7 = r14, in1	56	cmp.ne p6, p7 = r14, in1
57	(p7) br.cond.dpnt 3f ;;	57	(p7) br.cond.dpnt 3f ;;
58	0:	58	0:
59	cmp.ne p6, p7 = 0, in2	59	cmp.ne p6, p7 = 0, in2
60	(p7) br.cond.dpnt 2f ;;	60	(p7) br.cond.dpnt 2f ;;
61	(p6) adds r14 = -1, in2	61	(p6) adds r14 = -1, in2
62	(p6) mov r16 = r0	62	(p6) mov r16 = r0
63	(p6) mov r17 = r0 ;;	63	(p6) mov r17 = r0 ;;
64	(p6) mov ar.lc = r14	64	(p6) mov ar.lc = r14
65	1:	65	1:
66	add r14 = r16, r8	66	add r14 = r16, r8
67	add r15 = r16, in0	67	add r15 = r16, in0
68	adds r17 = 1, r17 ;;	68	adds r17 = 1, r17 ;;
69	ld1 r14 = [r14]	69	ld1 r14 = [r14]
70	mov r16 = r17 ;;	70	mov r16 = r17 ;;
71	st1 [r15] = r14	71	st1 [r15] = r14
72	br.cloop.sptk.few 1b ;;	72	br.cloop.sptk.few 1b ;;
73	2:	73	2:
74	mov ar.lc = r2	74	mov ar.lc = r2
75		75
76	mov ar.pfs = loc0	76	mov ar.pfs = loc0
77	br.ret.sptk.many rp	77	br.ret.sptk.many rp
78	3:	78	3:
79	adds r14 = 7, in0 ;;	79	adds r14 = 7, in0 ;;
80	and r14 = -8, r14 ;;	80	and r14 = -8, r14 ;;
81	cmp.eq p6, p7 = r14, in0	81	cmp.eq p6, p7 = r14, in0
82	(p7) br.cond.dptk 0b	82	(p7) br.cond.dptk 0b
83	shr.u r18 = in2, 3 ;;	83	shr.u r18 = in2, 3 ;;
84	cmp.ne p6, p7 = 0, r18	84	cmp.ne p6, p7 = 0, r18
85	(p7) br.cond.dpnt 5f ;;	85	(p7) br.cond.dpnt 5f ;;
86	(p6) adds r14 = -1, r18	86	(p6) adds r14 = -1, r18
87	(p6) mov r16 = r0	87	(p6) mov r16 = r0
88	(p6) mov r17 = r0 ;;	88	(p6) mov r17 = r0 ;;
89	(p6) mov ar.lc = r14	89	(p6) mov ar.lc = r14
90	4:	90	4:
91	shladd r14 = r16, 3, r0	91	shladd r14 = r16, 3, r0
92	adds r16 = 1, r17 ;;	92	adds r16 = 1, r17 ;;
93	add r15 = r8, r14	93	add r15 = r8, r14
94	add r14 = in0, r14	94	add r14 = in0, r14
95	mov r17 = r16 ;;	95	mov r17 = r16 ;;
96	ld8 r15 = [r15] ;;	96	ld8 r15 = [r15] ;;
97	st8 [r14] = r15	97	st8 [r14] = r15
98	br.cloop.sptk.few 4b	98	br.cloop.sptk.few 4b
99	5:	99	5:
100	and r15 = 7, in2	100	and r15 = 7, in2
101	shladd r14 = r18, 3, r0	101	shladd r14 = r18, 3, r0
102	mov r16 = r0	102	mov r16 = r0
103	mov r18 = r0 ;;	103	mov r18 = r0 ;;
104	cmp.eq p6, p7 = 0, r15	104	cmp.eq p6, p7 = 0, r15
105	add in0 = r14, in0	105	add in0 = r14, in0
106	adds r15 = -1, r15	106	adds r15 = -1, r15
107	add r17 = r14, r8	107	add r17 = r14, r8
108	(p6) br.cond.dpnt 2b ;;	108	(p6) br.cond.dpnt 2b ;;
109	mov ar.lc = r15	109	mov ar.lc = r15
110	6:	110	6:
111	add r14 = r16, r17	111	add r14 = r16, r17
112	add r15 = r16, in0	112	add r15 = r16, in0
113	adds r16 = 1, r18 ;;	113	adds r16 = 1, r18 ;;
114	ld1 r14 = [r14]	114	ld1 r14 = [r14]
115	mov r18 = r16 ;;	115	mov r18 = r16 ;;
116	st1 [r15] = r14	116	st1 [r15] = r14
117	br.cloop.sptk.few 6b ;;	117	br.cloop.sptk.few 6b ;;
118	mov ar.lc = r2	118	mov ar.lc = r2
119		119
120	mov ar.pfs = loc0	120	mov ar.pfs = loc0
121	br.ret.sptk.many rp	121	br.ret.sptk.many rp
122		122
123	memcpy_from_uspace_failover_address:	123	memcpy_from_uspace_failover_address:
124	memcpy_to_uspace_failover_address:	124	memcpy_to_uspace_failover_address:
125	mov r8 = r0 /* return 0 on failure */	125	mov r8 = r0 /* return 0 on failure */
126	mov ar.pfs = loc0	126	mov ar.pfs = loc0
127	br.ret.sptk.many rp	127	br.ret.sptk.many rp
128		128
129	.global memsetb	129	.global memsetb
130	memsetb:	130	memsetb:
131	br _memsetb	131	br _memsetb
132		132
133	.global cpu_halt	133	.global cpu_halt
134	cpu_halt:	134	cpu_halt:
135	br cpu_halt	135	br cpu_halt
136		136
137	.global panic_printf	137	.global panic_printf
138	panic_printf:	138	panic_printf:
139	{	139	{
140	br.call.sptk.many b0=printf	140	br.call.sptk.many b0=printf
141	}	141	}
142	br halt	142	br halt
143		143
144	/** Switch to userspace - low level code.	144	/** Switch to userspace - low level code.
145	*	145	*
146	* @param in0 Userspace entry point address.	146	* @param in0 Userspace entry point address.
147	* @param in1 Userspace stack pointer address.	147	* @param in1 Userspace stack pointer address.
148	* @param in2 Userspace register stack pointer address.	148	* @param in2 Userspace register stack pointer address.
149	* @param in3 Userspace address of thread uspace_arg_t structure.	149	* @param in3 Userspace address of thread uspace_arg_t structure.
150	* @param in4 Value to be stored in IPSR.	150	* @param in4 Value to be stored in IPSR.
151	* @param in5 Value to be stored in RSC.	151	* @param in5 Value to be stored in RSC.
152	*/	152	*/
153	.global switch_to_userspace	153	.global switch_to_userspace
154	switch_to_userspace:	154	switch_to_userspace:
155	alloc loc0 = ar.pfs, 6, 3, 0, 0	155	alloc loc0 = ar.pfs, 6, 3, 0, 0
156	rsm (PSR_IC_MASK \| PSR_I_MASK) /* disable interruption collection and interrupts */	156	rsm (PSR_IC_MASK \| PSR_I_MASK) /* disable interruption collection and interrupts */
157	srlz.d ;;	157	srlz.d ;;
158	srlz.i ;;	158	srlz.i ;;
159		159
160	mov cr.ipsr = in4	160	mov cr.ipsr = in4
161	mov cr.iip = in0	161	mov cr.iip = in0
162	mov r12 = in1	162	mov r12 = in1
163		163
164	xor r1 = r1, r1	164	xor r1 = r1, r1
165		165
166	mov loc1 = cr.ifs	166	mov loc1 = cr.ifs
167	movl loc2 = PFM_MASK ;;	167	movl loc2 = PFM_MASK ;;
168	and loc1 = loc2, loc1 ;;	168	and loc1 = loc2, loc1 ;;
169	mov cr.ifs = loc1 ;; /* prevent decrementing BSP by rfi */	169	mov cr.ifs = loc1 ;; /* prevent decrementing BSP by rfi */
170		170
171	invala	171	invala
172		172
173	mov loc1 = ar.rsc ;;	173	mov loc1 = ar.rsc ;;
174	and loc1 = ~3, loc1 ;;	174	and loc1 = ~3, loc1 ;;
175	mov ar.rsc = loc1 ;; /* put RSE into enforced lazy mode */	175	mov ar.rsc = loc1 ;; /* put RSE into enforced lazy mode */
176		176
177	flushrs ;;	177	flushrs ;;
178		178
179	mov ar.bspstore = in2 ;;	179	mov ar.bspstore = in2 ;;
180	mov ar.rsc = in5 ;;	180	mov ar.rsc = in5 ;;
181		181
182	mov r8 = in3	182	mov r8 = in3
183		183
184	rfi ;;	184	rfi ;;
185		185

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(root)/trunk/kernel/arch/ia64/src/asm.S – Rev 1787 → 2071