WebSVN – HelenOS – Diff – /trunk/kernel/arch/ia64/include/mm/page.h


/*
 * Copyright (c) 2005 - 2006 Jakub Jermar
 * Copyright (c) 2006 Jakub Vana
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup ia64mm 
 * @{
 */
/** @file
 */
 
#ifndef KERN_ia64_PAGE_H_
#define KERN_ia64_PAGE_H_
 
#include <arch/mm/frame.h>
 
#define PAGE_SIZE   FRAME_SIZE
#define PAGE_WIDTH  FRAME_WIDTH
 
 
 
#ifdef KERNEL
 
/** Bit width of the TLB-locked portion of kernel address space. */
#define KERNEL_PAGE_WIDTH       28  /* 256M */
#define IO_PAGE_WIDTH           26  /* 64M */
 
 
#define PPN_SHIFT           12
 
#define VRN_SHIFT           61
#define VRN_MASK            (7LL << VRN_SHIFT)
#define VA2VRN(va)          ((va)>>VRN_SHIFT)
 
#ifdef __ASM__
#define VRN_KERNEL          7
#else
#define VRN_KERNEL          7LL
#endif
 
#define REGION_REGISTERS        8
 
#define KA2PA(x)    ((uintptr_t) (x-(VRN_KERNEL<<VRN_SHIFT)))
#define PA2KA(x)    ((uintptr_t) (x+(VRN_KERNEL<<VRN_SHIFT)))
 
#define VHPT_WIDTH          20  /* 1M */
#define VHPT_SIZE           (1 << VHPT_WIDTH)
 
#define PTA_BASE_SHIFT          15
 
/** Memory Attributes. */
#define MA_WRITEBACK    0x0
#define MA_UNCACHEABLE  0x4
 
/** Privilege Levels. Only the most and the least privileged ones are ever used. */
#define PL_KERNEL   0x0
#define PL_USER     0x3
 
/* Access Rigths. Only certain combinations are used by the kernel. */
#define AR_READ     0x0
#define AR_EXECUTE  0x1
#define AR_WRITE    0x2
 
#ifndef __ASM__
 
#include <arch/mm/as.h>
#include <arch/mm/frame.h>
#include <arch/interrupt.h>
#include <arch/barrier.h>
#include <arch/mm/asid.h>
#include <arch/types.h>
#include <debug.h>
 
struct vhpt_tag_info {
    unsigned long long tag : 63;
    unsigned ti : 1;
} __attribute__ ((packed));
 
union vhpt_tag {
    struct vhpt_tag_info tag_info;
    unsigned tag_word;
};
 
struct vhpt_entry_present {
    /* Word 0 */
    unsigned p : 1;
    unsigned : 1;
    unsigned ma : 3;
    unsigned a : 1;
    unsigned d : 1;
    unsigned pl : 2;
    unsigned ar : 3;
    unsigned long long ppn : 38;
    unsigned : 2;
    unsigned ed : 1;
    unsigned ig1 : 11;
   
    /* Word 1 */
    unsigned : 2;
    unsigned ps : 6;
    unsigned key : 24;
    unsigned : 32;
   
    /* Word 2 */
    union vhpt_tag tag;
   
    /* Word 3 */                                                   
    uint64_t ig3 : 64;
} __attribute__ ((packed));
 
struct vhpt_entry_not_present {
    /* Word 0 */
    unsigned p : 1;
    unsigned long long ig0 : 52;
    unsigned ig1 : 11;
   
    /* Word 1 */
    unsigned : 2;
    unsigned ps : 6;
    unsigned long long ig2 : 56;
 
    /* Word 2 */
    union vhpt_tag tag;
   
    /* Word 3 */                                                   
    uint64_t ig3 : 64;
} __attribute__ ((packed));
 
typedef union vhpt_entry {
    struct vhpt_entry_present present;
    struct vhpt_entry_not_present not_present;
    uint64_t word[4];
} vhpt_entry_t;
 
struct region_register_map {
    unsigned ve : 1;
    unsigned : 1;
    unsigned ps : 6;
    unsigned rid : 24;
    unsigned : 32;
} __attribute__ ((packed));
 
typedef union region_register {
    struct region_register_map map;
    unsigned long long word;
} region_register;
 
struct pta_register_map {
    unsigned ve : 1;
    unsigned : 1;
    unsigned size : 6;
    unsigned vf : 1;
    unsigned : 6;
    unsigned long long base : 49;
} __attribute__ ((packed));
 
typedef union pta_register {
    struct pta_register_map map;
    uint64_t word;
} pta_register;
 
/** Return Translation Hashed Entry Address.
 *
 * VRN bits are used to read RID (ASID) from one
 * of the eight region registers registers.
 *
 * @param va Virtual address including VRN bits.
 *
 * @return Address of the head of VHPT collision chain.
 */
static inline uint64_t thash(uint64_t va)
{
    uint64_t ret;
 
    asm volatile ("thash %0 = %1\n" : "=r" (ret) : "r" (va));
 
    return ret;
}
 
/** Return Translation Hashed Entry Tag.
 *
 * VRN bits are used to read RID (ASID) from one
 * of the eight region registers.
 *
 * @param va Virtual address including VRN bits.
 *
 * @return The unique tag for VPN and RID in the collision chain returned by thash().
 */
static inline uint64_t ttag(uint64_t va)
{
    uint64_t ret;
 
    asm volatile ("ttag %0 = %1\n" : "=r" (ret) : "r" (va));
 
    return ret;
}
 
/** Read Region Register.
 *
 * @param i Region register index.
 *
 * @return Current contents of rr[i].
 */
static inline uint64_t rr_read(index_t i)
{
    uint64_t ret;
    ASSERT(i < REGION_REGISTERS);
    asm volatile ("mov %0 = rr[%1]\n" : "=r" (ret) : "r" (i << VRN_SHIFT));
    return ret;
}
 
/** Write Region Register.
 *
 * @param i Region register index.
 * @param v Value to be written to rr[i].
 */
static inline void rr_write(index_t i, uint64_t v)
{
    ASSERT(i < REGION_REGISTERS);
    asm volatile (
        "mov rr[%0] = %1\n"
        :
        : "r" (i << VRN_SHIFT), "r" (v)
    );
}
 
/** Read Page Table Register.
 *
 * @return Current value stored in PTA.
 */
static inline uint64_t pta_read(void)
{
    uint64_t ret;
   
    asm volatile ("mov %0 = cr.pta\n" : "=r" (ret));
   
    return ret;
}
 
/** Write Page Table Register.
 *
 * @param v New value to be stored in PTA.
 */
static inline void pta_write(uint64_t v)
{
    asm volatile ("mov cr.pta = %0\n" : : "r" (v));
}
 
extern void page_arch_init(void);
 
extern vhpt_entry_t *vhpt_hash(uintptr_t page, asid_t asid);
extern bool vhpt_compare(uintptr_t page, asid_t asid, vhpt_entry_t *v);
extern void vhpt_set_record(vhpt_entry_t *v, uintptr_t page, asid_t asid, uintptr_t frame, int flags);
 
#endif /* __ASM__ */
 
#endif /* KERNEL */
 
#endif
 
/** @}
 */
 

Rev 2726	Rev 3233
1	/*	1	/*
2	* Copyright (c) 2005 - 2006 Jakub Jermar	2	* Copyright (c) 2005 - 2006 Jakub Jermar
3	* Copyright (c) 2006 Jakub Vana	3	* Copyright (c) 2006 Jakub Vana
4	* All rights reserved.	4	* All rights reserved.
5	*	5	*
6	* Redistribution and use in source and binary forms, with or without	6	* Redistribution and use in source and binary forms, with or without
7	* modification, are permitted provided that the following conditions	7	* modification, are permitted provided that the following conditions
8	* are met:	8	* are met:
9	*	9	*
10	* - Redistributions of source code must retain the above copyright	10	* - Redistributions of source code must retain the above copyright
11	* notice, this list of conditions and the following disclaimer.	11	* notice, this list of conditions and the following disclaimer.
12	* - Redistributions in binary form must reproduce the above copyright	12	* - Redistributions in binary form must reproduce the above copyright
13	* notice, this list of conditions and the following disclaimer in the	13	* notice, this list of conditions and the following disclaimer in the
14	* documentation and/or other materials provided with the distribution.	14	* documentation and/or other materials provided with the distribution.
15	* - The name of the author may not be used to endorse or promote products	15	* - The name of the author may not be used to endorse or promote products
16	* derived from this software without specific prior written permission.	16	* derived from this software without specific prior written permission.
17	*	17	*
18	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	18	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	19	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	20	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	21	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	22	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	23	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	24	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	25	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	26	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	27	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28	*/	28	*/
29		29
30	/** @addtogroup ia64mm	30	/** @addtogroup ia64mm
31	* @{	31	* @{
32	*/	32	*/
33	/** @file	33	/** @file
34	*/	34	*/
35		35
36	#ifndef KERN_ia64_PAGE_H_	36	#ifndef KERN_ia64_PAGE_H_
37	#define KERN_ia64_PAGE_H_	37	#define KERN_ia64_PAGE_H_
38		38
39	#include <arch/mm/frame.h>	39	#include <arch/mm/frame.h>
40		40
41	#define PAGE_SIZE FRAME_SIZE	41	#define PAGE_SIZE FRAME_SIZE
42	#define PAGE_WIDTH FRAME_WIDTH	42	#define PAGE_WIDTH FRAME_WIDTH
43		43
44	#define PAGE_COLOR_BITS 0 /* dummy */	-
45		-
46	#ifdef KERNEL	44	#ifdef KERNEL
47		45
48	/** Bit width of the TLB-locked portion of kernel address space. */	46	/** Bit width of the TLB-locked portion of kernel address space. */
49	#define KERNEL_PAGE_WIDTH 28 /* 256M */	47	#define KERNEL_PAGE_WIDTH 28 /* 256M */
50	#define IO_PAGE_WIDTH 26 /* 64M */	48	#define IO_PAGE_WIDTH 26 /* 64M */
51		49
52		50
53	#define PPN_SHIFT 12	51	#define PPN_SHIFT 12
54		52
55	#define VRN_SHIFT 61	53	#define VRN_SHIFT 61
56	#define VRN_MASK (7LL << VRN_SHIFT)	54	#define VRN_MASK (7LL << VRN_SHIFT)
57	#define VA2VRN(va) ((va)>>VRN_SHIFT)	55	#define VA2VRN(va) ((va)>>VRN_SHIFT)
58		56
59	#ifdef __ASM__	57	#ifdef __ASM__
60	#define VRN_KERNEL 7	58	#define VRN_KERNEL 7
61	#else	59	#else
62	#define VRN_KERNEL 7LL	60	#define VRN_KERNEL 7LL
63	#endif	61	#endif
64		62
65	#define REGION_REGISTERS 8	63	#define REGION_REGISTERS 8
66		64
67	#define KA2PA(x) ((uintptr_t) (x-(VRN_KERNEL<<VRN_SHIFT)))	65	#define KA2PA(x) ((uintptr_t) (x-(VRN_KERNEL<<VRN_SHIFT)))
68	#define PA2KA(x) ((uintptr_t) (x+(VRN_KERNEL<<VRN_SHIFT)))	66	#define PA2KA(x) ((uintptr_t) (x+(VRN_KERNEL<<VRN_SHIFT)))
69		67
70	#define VHPT_WIDTH 20 /* 1M */	68	#define VHPT_WIDTH 20 /* 1M */
71	#define VHPT_SIZE (1 << VHPT_WIDTH)	69	#define VHPT_SIZE (1 << VHPT_WIDTH)
72		70
73	#define PTA_BASE_SHIFT 15	71	#define PTA_BASE_SHIFT 15
74		72
75	/** Memory Attributes. */	73	/** Memory Attributes. */
76	#define MA_WRITEBACK 0x0	74	#define MA_WRITEBACK 0x0
77	#define MA_UNCACHEABLE 0x4	75	#define MA_UNCACHEABLE 0x4
78		76
79	/** Privilege Levels. Only the most and the least privileged ones are ever used. */	77	/** Privilege Levels. Only the most and the least privileged ones are ever used. */
80	#define PL_KERNEL 0x0	78	#define PL_KERNEL 0x0
81	#define PL_USER 0x3	79	#define PL_USER 0x3
82		80
83	/* Access Rigths. Only certain combinations are used by the kernel. */	81	/* Access Rigths. Only certain combinations are used by the kernel. */
84	#define AR_READ 0x0	82	#define AR_READ 0x0
85	#define AR_EXECUTE 0x1	83	#define AR_EXECUTE 0x1
86	#define AR_WRITE 0x2	84	#define AR_WRITE 0x2
87		85
88	#ifndef __ASM__	86	#ifndef __ASM__
89		87
90	#include <arch/mm/as.h>	88	#include <arch/mm/as.h>
91	#include <arch/mm/frame.h>	89	#include <arch/mm/frame.h>
92	#include <arch/interrupt.h>	90	#include <arch/interrupt.h>
93	#include <arch/barrier.h>	91	#include <arch/barrier.h>
94	#include <arch/mm/asid.h>	92	#include <arch/mm/asid.h>
95	#include <arch/types.h>	93	#include <arch/types.h>
96	#include <debug.h>	94	#include <debug.h>
97		95
98	struct vhpt_tag_info {	96	struct vhpt_tag_info {
99	unsigned long long tag : 63;	97	unsigned long long tag : 63;
100	unsigned ti : 1;	98	unsigned ti : 1;
101	} __attribute__ ((packed));	99	} __attribute__ ((packed));
102		100
103	union vhpt_tag {	101	union vhpt_tag {
104	struct vhpt_tag_info tag_info;	102	struct vhpt_tag_info tag_info;
105	unsigned tag_word;	103	unsigned tag_word;
106	};	104	};
107		105
108	struct vhpt_entry_present {	106	struct vhpt_entry_present {
109	/* Word 0 */	107	/* Word 0 */
110	unsigned p : 1;	108	unsigned p : 1;
111	unsigned : 1;	109	unsigned : 1;
112	unsigned ma : 3;	110	unsigned ma : 3;
113	unsigned a : 1;	111	unsigned a : 1;
114	unsigned d : 1;	112	unsigned d : 1;
115	unsigned pl : 2;	113	unsigned pl : 2;
116	unsigned ar : 3;	114	unsigned ar : 3;
117	unsigned long long ppn : 38;	115	unsigned long long ppn : 38;
118	unsigned : 2;	116	unsigned : 2;
119	unsigned ed : 1;	117	unsigned ed : 1;
120	unsigned ig1 : 11;	118	unsigned ig1 : 11;
121		119
122	/* Word 1 */	120	/* Word 1 */
123	unsigned : 2;	121	unsigned : 2;
124	unsigned ps : 6;	122	unsigned ps : 6;
125	unsigned key : 24;	123	unsigned key : 24;
126	unsigned : 32;	124	unsigned : 32;
127		125
128	/* Word 2 */	126	/* Word 2 */
129	union vhpt_tag tag;	127	union vhpt_tag tag;
130		128
131	/* Word 3 */	129	/* Word 3 */
132	uint64_t ig3 : 64;	130	uint64_t ig3 : 64;
133	} __attribute__ ((packed));	131	} __attribute__ ((packed));
134		132
135	struct vhpt_entry_not_present {	133	struct vhpt_entry_not_present {
136	/* Word 0 */	134	/* Word 0 */
137	unsigned p : 1;	135	unsigned p : 1;
138	unsigned long long ig0 : 52;	136	unsigned long long ig0 : 52;
139	unsigned ig1 : 11;	137	unsigned ig1 : 11;
140		138
141	/* Word 1 */	139	/* Word 1 */
142	unsigned : 2;	140	unsigned : 2;
143	unsigned ps : 6;	141	unsigned ps : 6;
144	unsigned long long ig2 : 56;	142	unsigned long long ig2 : 56;
145		143
146	/* Word 2 */	144	/* Word 2 */
147	union vhpt_tag tag;	145	union vhpt_tag tag;
148		146
149	/* Word 3 */	147	/* Word 3 */
150	uint64_t ig3 : 64;	148	uint64_t ig3 : 64;
151	} __attribute__ ((packed));	149	} __attribute__ ((packed));
152		150
153	typedef union vhpt_entry {	151	typedef union vhpt_entry {
154	struct vhpt_entry_present present;	152	struct vhpt_entry_present present;
155	struct vhpt_entry_not_present not_present;	153	struct vhpt_entry_not_present not_present;
156	uint64_t word[4];	154	uint64_t word[4];
157	} vhpt_entry_t;	155	} vhpt_entry_t;
158		156
159	struct region_register_map {	157	struct region_register_map {
160	unsigned ve : 1;	158	unsigned ve : 1;
161	unsigned : 1;	159	unsigned : 1;
162	unsigned ps : 6;	160	unsigned ps : 6;
163	unsigned rid : 24;	161	unsigned rid : 24;
164	unsigned : 32;	162	unsigned : 32;
165	} __attribute__ ((packed));	163	} __attribute__ ((packed));
166		164
167	typedef union region_register {	165	typedef union region_register {
168	struct region_register_map map;	166	struct region_register_map map;
169	unsigned long long word;	167	unsigned long long word;
170	} region_register;	168	} region_register;
171		169
172	struct pta_register_map {	170	struct pta_register_map {
173	unsigned ve : 1;	171	unsigned ve : 1;
174	unsigned : 1;	172	unsigned : 1;
175	unsigned size : 6;	173	unsigned size : 6;
176	unsigned vf : 1;	174	unsigned vf : 1;
177	unsigned : 6;	175	unsigned : 6;
178	unsigned long long base : 49;	176	unsigned long long base : 49;
179	} __attribute__ ((packed));	177	} __attribute__ ((packed));
180		178
181	typedef union pta_register {	179	typedef union pta_register {
182	struct pta_register_map map;	180	struct pta_register_map map;
183	uint64_t word;	181	uint64_t word;
184	} pta_register;	182	} pta_register;
185		183
186	/** Return Translation Hashed Entry Address.	184	/** Return Translation Hashed Entry Address.
187	*	185	*
188	* VRN bits are used to read RID (ASID) from one	186	* VRN bits are used to read RID (ASID) from one
189	* of the eight region registers registers.	187	* of the eight region registers registers.
190	*	188	*
191	* @param va Virtual address including VRN bits.	189	* @param va Virtual address including VRN bits.
192	*	190	*
193	* @return Address of the head of VHPT collision chain.	191	* @return Address of the head of VHPT collision chain.
194	*/	192	*/
195	static inline uint64_t thash(uint64_t va)	193	static inline uint64_t thash(uint64_t va)
196	{	194	{
197	uint64_t ret;	195	uint64_t ret;
198		196
199	asm volatile ("thash %0 = %1\n" : "=r" (ret) : "r" (va));	197	asm volatile ("thash %0 = %1\n" : "=r" (ret) : "r" (va));
200		198
201	return ret;	199	return ret;
202	}	200	}
203		201
204	/** Return Translation Hashed Entry Tag.	202	/** Return Translation Hashed Entry Tag.
205	*	203	*
206	* VRN bits are used to read RID (ASID) from one	204	* VRN bits are used to read RID (ASID) from one
207	* of the eight region registers.	205	* of the eight region registers.
208	*	206	*
209	* @param va Virtual address including VRN bits.	207	* @param va Virtual address including VRN bits.
210	*	208	*
211	* @return The unique tag for VPN and RID in the collision chain returned by thash().	209	* @return The unique tag for VPN and RID in the collision chain returned by thash().
212	*/	210	*/
213	static inline uint64_t ttag(uint64_t va)	211	static inline uint64_t ttag(uint64_t va)
214	{	212	{
215	uint64_t ret;	213	uint64_t ret;
216		214
217	asm volatile ("ttag %0 = %1\n" : "=r" (ret) : "r" (va));	215	asm volatile ("ttag %0 = %1\n" : "=r" (ret) : "r" (va));
218		216
219	return ret;	217	return ret;
220	}	218	}
221		219
222	/** Read Region Register.	220	/** Read Region Register.
223	*	221	*
224	* @param i Region register index.	222	* @param i Region register index.
225	*	223	*
226	* @return Current contents of rr[i].	224	* @return Current contents of rr[i].
227	*/	225	*/
228	static inline uint64_t rr_read(index_t i)	226	static inline uint64_t rr_read(index_t i)
229	{	227	{
230	uint64_t ret;	228	uint64_t ret;
231	ASSERT(i < REGION_REGISTERS);	229	ASSERT(i < REGION_REGISTERS);
232	asm volatile ("mov %0 = rr[%1]\n" : "=r" (ret) : "r" (i << VRN_SHIFT));	230	asm volatile ("mov %0 = rr[%1]\n" : "=r" (ret) : "r" (i << VRN_SHIFT));
233	return ret;	231	return ret;
234	}	232	}
235		233
236	/** Write Region Register.	234	/** Write Region Register.
237	*	235	*
238	* @param i Region register index.	236	* @param i Region register index.
239	* @param v Value to be written to rr[i].	237	* @param v Value to be written to rr[i].
240	*/	238	*/
241	static inline void rr_write(index_t i, uint64_t v)	239	static inline void rr_write(index_t i, uint64_t v)
242	{	240	{
243	ASSERT(i < REGION_REGISTERS);	241	ASSERT(i < REGION_REGISTERS);
244	asm volatile (	242	asm volatile (
245	"mov rr[%0] = %1\n"	243	"mov rr[%0] = %1\n"
246	:	244	:
247	: "r" (i << VRN_SHIFT), "r" (v)	245	: "r" (i << VRN_SHIFT), "r" (v)
248	);	246	);
249	}	247	}
250		248
251	/** Read Page Table Register.	249	/** Read Page Table Register.
252	*	250	*
253	* @return Current value stored in PTA.	251	* @return Current value stored in PTA.
254	*/	252	*/
255	static inline uint64_t pta_read(void)	253	static inline uint64_t pta_read(void)
256	{	254	{
257	uint64_t ret;	255	uint64_t ret;
258		256
259	asm volatile ("mov %0 = cr.pta\n" : "=r" (ret));	257	asm volatile ("mov %0 = cr.pta\n" : "=r" (ret));
260		258
261	return ret;	259	return ret;
262	}	260	}
263		261
264	/** Write Page Table Register.	262	/** Write Page Table Register.
265	*	263	*
266	* @param v New value to be stored in PTA.	264	* @param v New value to be stored in PTA.
267	*/	265	*/
268	static inline void pta_write(uint64_t v)	266	static inline void pta_write(uint64_t v)
269	{	267	{
270	asm volatile ("mov cr.pta = %0\n" : : "r" (v));	268	asm volatile ("mov cr.pta = %0\n" : : "r" (v));
271	}	269	}
272		270
273	extern void page_arch_init(void);	271	extern void page_arch_init(void);
274		272
275	extern vhpt_entry_t *vhpt_hash(uintptr_t page, asid_t asid);	273	extern vhpt_entry_t *vhpt_hash(uintptr_t page, asid_t asid);
276	extern bool vhpt_compare(uintptr_t page, asid_t asid, vhpt_entry_t *v);	274	extern bool vhpt_compare(uintptr_t page, asid_t asid, vhpt_entry_t *v);
277	extern void vhpt_set_record(vhpt_entry_t *v, uintptr_t page, asid_t asid, uintptr_t frame, int flags);	275	extern void vhpt_set_record(vhpt_entry_t *v, uintptr_t page, asid_t asid, uintptr_t frame, int flags);
278		276
279	#endif /* __ASM__ */	277	#endif /* __ASM__ */
280		278
281	#endif /* KERNEL */	279	#endif /* KERNEL */
282		280
283	#endif	281	#endif
284		282
285	/** @}	283	/** @}
286	*/	284	*/
287		285

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(root)/trunk/kernel/arch/ia64/include/mm/page.h – Rev 2726 → 3233