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| 1 | /* |
1 | /* |
| 2 | * Copyright (c) 2005 Jakub Jermar |
2 | * Copyright (c) 2005 Jakub Jermar |
| 3 | * All rights reserved. |
3 | * All rights reserved. |
| 4 | * |
4 | * |
| 5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
| 6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
| 7 | * are met: |
7 | * are met: |
| 8 | * |
8 | * |
| 9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
| 10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
| 11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
| 12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
| 13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
| 14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
| 15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
| 16 | * |
16 | * |
| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | */ |
27 | */ |
| 28 | 28 | ||
| 29 | /** @addtogroup ia64interrupt |
29 | /** @addtogroup ia64interrupt |
| 30 | * @{ |
30 | * @{ |
| 31 | */ |
31 | */ |
| 32 | /** @file |
32 | /** @file |
| 33 | */ |
33 | */ |
| 34 | 34 | ||
| 35 | #ifndef KERN_ia64_INTERRUPT_H_ |
35 | #ifndef KERN_ia64_INTERRUPT_H_ |
| 36 | #define KERN_ia64_INTERRUPT_H_ |
36 | #define KERN_ia64_INTERRUPT_H_ |
| 37 | 37 | ||
| 38 | #include <typedefs.h> |
- | |
| 39 | #include <arch/types.h> |
38 | #include <arch/types.h> |
| 40 | #include <arch/register.h> |
39 | #include <arch/register.h> |
| 41 | 40 | ||
| 42 | /** ia64 has 256 INRs. */ |
41 | /** ia64 has 256 INRs. */ |
| 43 | #define INR_COUNT 256 |
42 | #define INR_COUNT 256 |
| 44 | 43 | ||
| 45 | /* |
44 | /* |
| 46 | * We need to keep this just to compile. |
45 | * We need to keep this just to compile. |
| 47 | * We might eventually move interrupt/ stuff |
46 | * We might eventually move interrupt/ stuff |
| 48 | * to genarch. |
47 | * to genarch. |
| 49 | */ |
48 | */ |
| 50 | #define IVT_ITEMS 0 |
49 | #define IVT_ITEMS 0 |
| 51 | #define IVT_FIRST 0 |
50 | #define IVT_FIRST 0 |
| 52 | 51 | ||
| 53 | /** External Interrupt vectors. */ |
52 | /** External Interrupt vectors. */ |
| 54 | #define INTERRUPT_TIMER 255 |
53 | #define INTERRUPT_TIMER 255 |
| 55 | #define INTERRUPT_SPURIOUS 15 |
54 | #define INTERRUPT_SPURIOUS 15 |
| 56 | 55 | ||
| 57 | /** General Exception codes. */ |
56 | /** General Exception codes. */ |
| 58 | #define GE_ILLEGALOP 0 |
57 | #define GE_ILLEGALOP 0 |
| 59 | #define GE_PRIVOP 1 |
58 | #define GE_PRIVOP 1 |
| 60 | #define GE_PRIVREG 2 |
59 | #define GE_PRIVREG 2 |
| 61 | #define GE_RESREGFLD 3 |
60 | #define GE_RESREGFLD 3 |
| 62 | #define GE_DISBLDISTRAN 4 |
61 | #define GE_DISBLDISTRAN 4 |
| 63 | #define GE_ILLEGALDEP 8 |
62 | #define GE_ILLEGALDEP 8 |
| 64 | 63 | ||
| 65 | #define EOI 0 /**< The actual value doesn't matter. */ |
64 | #define EOI 0 /**< The actual value doesn't matter. */ |
| 66 | 65 | ||
| 67 | struct istate { |
66 | typedef struct { |
| 68 | __r128 f2; |
67 | uint128_t f2; |
| 69 | __r128 f3; |
68 | uint128_t f3; |
| 70 | __r128 f4; |
69 | uint128_t f4; |
| 71 | __r128 f5; |
70 | uint128_t f5; |
| 72 | __r128 f6; |
71 | uint128_t f6; |
| 73 | __r128 f7; |
72 | uint128_t f7; |
| 74 | __r128 f8; |
73 | uint128_t f8; |
| 75 | __r128 f9; |
74 | uint128_t f9; |
| 76 | __r128 f10; |
75 | uint128_t f10; |
| 77 | __r128 f11; |
76 | uint128_t f11; |
| 78 | __r128 f12; |
77 | uint128_t f12; |
| 79 | __r128 f13; |
78 | uint128_t f13; |
| 80 | __r128 f14; |
79 | uint128_t f14; |
| 81 | __r128 f15; |
80 | uint128_t f15; |
| 82 | __r128 f16; |
81 | uint128_t f16; |
| 83 | __r128 f17; |
82 | uint128_t f17; |
| 84 | __r128 f18; |
83 | uint128_t f18; |
| 85 | __r128 f19; |
84 | uint128_t f19; |
| 86 | __r128 f20; |
85 | uint128_t f20; |
| 87 | __r128 f21; |
86 | uint128_t f21; |
| 88 | __r128 f22; |
87 | uint128_t f22; |
| 89 | __r128 f23; |
88 | uint128_t f23; |
| 90 | __r128 f24; |
89 | uint128_t f24; |
| 91 | __r128 f25; |
90 | uint128_t f25; |
| 92 | __r128 f26; |
91 | uint128_t f26; |
| 93 | __r128 f27; |
92 | uint128_t f27; |
| 94 | __r128 f28; |
93 | uint128_t f28; |
| 95 | __r128 f29; |
94 | uint128_t f29; |
| 96 | __r128 f30; |
95 | uint128_t f30; |
| 97 | __r128 f31; |
96 | uint128_t f31; |
| 98 | 97 | ||
| 99 | uintptr_t ar_bsp; |
98 | uintptr_t ar_bsp; |
| 100 | uintptr_t ar_bspstore; |
99 | uintptr_t ar_bspstore; |
| 101 | uintptr_t ar_bspstore_new; |
100 | uintptr_t ar_bspstore_new; |
| 102 | uint64_t ar_rnat; |
101 | uint64_t ar_rnat; |
| 103 | uint64_t ar_ifs; |
102 | uint64_t ar_ifs; |
| 104 | uint64_t ar_pfs; |
103 | uint64_t ar_pfs; |
| 105 | uint64_t ar_rsc; |
104 | uint64_t ar_rsc; |
| 106 | uintptr_t cr_ifa; |
105 | uintptr_t cr_ifa; |
| 107 | cr_isr_t cr_isr; |
106 | cr_isr_t cr_isr; |
| 108 | uintptr_t cr_iipa; |
107 | uintptr_t cr_iipa; |
| 109 | psr_t cr_ipsr; |
108 | psr_t cr_ipsr; |
| 110 | uintptr_t cr_iip; |
109 | uintptr_t cr_iip; |
| 111 | uint64_t pr; |
110 | uint64_t pr; |
| 112 | uintptr_t sp; |
111 | uintptr_t sp; |
| 113 | 112 | ||
| 114 | /* |
113 | /* |
| 115 | * The following variables are defined only for break_instruction handler. |
114 | * The following variables are defined only for break_instruction handler. |
| 116 | */ |
115 | */ |
| 117 | uint64_t in0; |
116 | uint64_t in0; |
| 118 | uint64_t in1; |
117 | uint64_t in1; |
| 119 | uint64_t in2; |
118 | uint64_t in2; |
| 120 | uint64_t in3; |
119 | uint64_t in3; |
| 121 | uint64_t in4; |
120 | uint64_t in4; |
| 122 | }; |
121 | } istate_t; |
| 123 | 122 | ||
| 124 | static inline void istate_set_retaddr(istate_t *istate, uintptr_t retaddr) |
123 | static inline void istate_set_retaddr(istate_t *istate, uintptr_t retaddr) |
| 125 | { |
124 | { |
| 126 | istate->cr_iip = retaddr; |
125 | istate->cr_iip = retaddr; |
| 127 | istate->cr_ipsr.ri = 0; /* return to instruction slot #0 */ |
126 | istate->cr_ipsr.ri = 0; /* return to instruction slot #0 */ |
| 128 | } |
127 | } |
| 129 | 128 | ||
| 130 | static inline unative_t istate_get_pc(istate_t *istate) |
129 | static inline unative_t istate_get_pc(istate_t *istate) |
| 131 | { |
130 | { |
| 132 | return istate->cr_iip; |
131 | return istate->cr_iip; |
| 133 | } |
132 | } |
| 134 | 133 | ||
| 135 | static inline int istate_from_uspace(istate_t *istate) |
134 | static inline int istate_from_uspace(istate_t *istate) |
| 136 | { |
135 | { |
| 137 | return (istate->cr_iip) < 0xe000000000000000ULL; |
136 | return (istate->cr_iip) < 0xe000000000000000ULL; |
| 138 | } |
137 | } |
| 139 | 138 | ||
| 140 | extern void *ivt; |
139 | extern void *ivt; |
| 141 | 140 | ||
| 142 | extern void general_exception(uint64_t vector, istate_t *istate); |
141 | extern void general_exception(uint64_t vector, istate_t *istate); |
| 143 | extern int break_instruction(uint64_t vector, istate_t *istate); |
142 | extern int break_instruction(uint64_t vector, istate_t *istate); |
| 144 | extern void universal_handler(uint64_t vector, istate_t *istate); |
143 | extern void universal_handler(uint64_t vector, istate_t *istate); |
| 145 | extern void nop_handler(uint64_t vector, istate_t *istate); |
144 | extern void nop_handler(uint64_t vector, istate_t *istate); |
| 146 | extern void external_interrupt(uint64_t vector, istate_t *istate); |
145 | extern void external_interrupt(uint64_t vector, istate_t *istate); |
| 147 | extern void disabled_fp_register(uint64_t vector, istate_t *istate); |
146 | extern void disabled_fp_register(uint64_t vector, istate_t *istate); |
| 148 | 147 | ||
| 149 | #endif |
148 | #endif |
| 150 | 149 | ||
| 151 | /** @} |
150 | /** @} |
| 152 | */ |
151 | */ |
| 153 | 152 | ||