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| Rev 2101 | Rev 2107 | ||
|---|---|---|---|
| Line 149... | Line 149... | ||
| 149 | 149 | ||
| 150 | /* |
150 | /* |
| 151 | * Ensure that io_apic has unique ID. |
151 | * Ensure that io_apic has unique ID. |
| 152 | */ |
152 | */ |
| 153 | idreg.value = io_apic_read(IOAPICID); |
153 | idreg.value = io_apic_read(IOAPICID); |
| 154 | if ((1<<idreg.apic_id) & apic_id_mask) { /* see if IO APIC ID is used already */ |
154 | if ((1 << idreg.apic_id) & apic_id_mask) { /* see if IO APIC ID is used already */ |
| 155 | for (i = 0; i < APIC_ID_COUNT; i++) { |
155 | for (i = 0; i < APIC_ID_COUNT; i++) { |
| 156 | if (!((1<<i) & apic_id_mask)) { |
156 | if (!((1<<i) & apic_id_mask)) { |
| 157 | idreg.apic_id = i; |
157 | idreg.apic_id = i; |
| 158 | io_apic_write(IOAPICID, idreg.value); |
158 | io_apic_write(IOAPICID, idreg.value); |
| 159 | break; |
159 | break; |
| Line 300... | Line 300... | ||
| 300 | 300 | ||
| 301 | if (!is_82489DX_apic(l_apic[LAVR])) { |
301 | if (!is_82489DX_apic(l_apic[LAVR])) { |
| 302 | /* |
302 | /* |
| 303 | * If this is not 82489DX-based l_apic we must send two STARTUP IPI's. |
303 | * If this is not 82489DX-based l_apic we must send two STARTUP IPI's. |
| 304 | */ |
304 | */ |
| 305 | for (i = 0; i<2; i++) { |
305 | for (i = 0; i < 2; i++) { |
| 306 | icr.lo = l_apic[ICRlo]; |
306 | icr.lo = l_apic[ICRlo]; |
| 307 | icr.delmod = DELMOD_STARTUP; |
307 | icr.delmod = DELMOD_STARTUP; |
| 308 | icr.destmod = DESTMOD_PHYS; |
308 | icr.destmod = DESTMOD_PHYS; |
| 309 | icr.level = LEVEL_ASSERT; |
309 | icr.level = LEVEL_ASSERT; |
| 310 | icr.shorthand = SHORTHAND_NONE; |
310 | icr.shorthand = SHORTHAND_NONE; |
| Line 399... | Line 399... | ||
| 399 | 399 | ||
| 400 | l_apic[ICRT] = t1-t2; |
400 | l_apic[ICRT] = t1-t2; |
| 401 | 401 | ||
| 402 | /* Program Logical Destination Register. */ |
402 | /* Program Logical Destination Register. */ |
| 403 | ldr.value = l_apic[LDR]; |
403 | ldr.value = l_apic[LDR]; |
| 404 | if (CPU->id < sizeof(CPU->id)*8) /* size in bits */ |
404 | if (CPU->id < sizeof(CPU->id) * 8) /* size in bits */ |
| 405 | ldr.id = (1<<CPU->id); |
405 | ldr.id = (1 << CPU->id); |
| 406 | l_apic[LDR] = ldr.value; |
406 | l_apic[LDR] = ldr.value; |
| 407 | 407 | ||
| 408 | /* Program Destination Format Register for Flat mode. */ |
408 | /* Program Destination Format Register for Flat mode. */ |
| 409 | dfr.value = l_apic[DFR]; |
409 | dfr.value = l_apic[DFR]; |
| 410 | dfr.model = MODEL_FLAT; |
410 | dfr.model = MODEL_FLAT; |
| Line 505... | Line 505... | ||
| 505 | int dlvr = DELMOD_FIXED; |
505 | int dlvr = DELMOD_FIXED; |
| 506 | 506 | ||
| 507 | if (flags & LOPRI) |
507 | if (flags & LOPRI) |
| 508 | dlvr = DELMOD_LOWPRI; |
508 | dlvr = DELMOD_LOWPRI; |
| 509 | 509 | ||
| 510 | reg.lo = io_apic_read(IOREDTBL + pin*2); |
510 | reg.lo = io_apic_read(IOREDTBL + pin * 2); |
| 511 | reg.hi = io_apic_read(IOREDTBL + pin*2 + 1); |
511 | reg.hi = io_apic_read(IOREDTBL + pin * 2 + 1); |
| 512 | 512 | ||
| 513 | reg.dest = dest; |
513 | reg.dest = dest; |
| 514 | reg.destmod = DESTMOD_LOGIC; |
514 | reg.destmod = DESTMOD_LOGIC; |
| 515 | reg.trigger_mode = TRIGMOD_EDGE; |
515 | reg.trigger_mode = TRIGMOD_EDGE; |
| 516 | reg.intpol = POLARITY_HIGH; |
516 | reg.intpol = POLARITY_HIGH; |
| 517 | reg.delmod = dlvr; |
517 | reg.delmod = dlvr; |
| 518 | reg.intvec = v; |
518 | reg.intvec = v; |
| 519 | 519 | ||
| 520 | io_apic_write(IOREDTBL + pin*2, reg.lo); |
520 | io_apic_write(IOREDTBL + pin * 2, reg.lo); |
| 521 | io_apic_write(IOREDTBL + pin*2 + 1, reg.hi); |
521 | io_apic_write(IOREDTBL + pin * 2 + 1, reg.hi); |
| 522 | } |
522 | } |
| 523 | 523 | ||
| 524 | /** Mask IRQs in IO APIC. |
524 | /** Mask IRQs in IO APIC. |
| 525 | * |
525 | * |
| 526 | * @param irqmask Bitmask of IRQs to be masked (0 = do not mask, 1 = mask). |
526 | * @param irqmask Bitmask of IRQs to be masked (0 = do not mask, 1 = mask). |
| Line 537... | Line 537... | ||
| 537 | * Mask the signal input in IO APIC if there is a |
537 | * Mask the signal input in IO APIC if there is a |
| 538 | * mapping for the respective IRQ number. |
538 | * mapping for the respective IRQ number. |
| 539 | */ |
539 | */ |
| 540 | pin = smp_irq_to_pin(i); |
540 | pin = smp_irq_to_pin(i); |
| 541 | if (pin != -1) { |
541 | if (pin != -1) { |
| 542 | reg.lo = io_apic_read(IOREDTBL + pin*2); |
542 | reg.lo = io_apic_read(IOREDTBL + pin * 2); |
| 543 | reg.masked = true; |
543 | reg.masked = true; |
| 544 | io_apic_write(IOREDTBL + pin*2, reg.lo); |
544 | io_apic_write(IOREDTBL + pin*2, reg.lo); |
| 545 | } |
545 | } |
| 546 | 546 | ||
| 547 | } |
547 | } |
| Line 564... | Line 564... | ||
| 564 | * Unmask the signal input in IO APIC if there is a |
564 | * Unmask the signal input in IO APIC if there is a |
| 565 | * mapping for the respective IRQ number. |
565 | * mapping for the respective IRQ number. |
| 566 | */ |
566 | */ |
| 567 | pin = smp_irq_to_pin(i); |
567 | pin = smp_irq_to_pin(i); |
| 568 | if (pin != -1) { |
568 | if (pin != -1) { |
| 569 | reg.lo = io_apic_read(IOREDTBL + pin*2); |
569 | reg.lo = io_apic_read(IOREDTBL + pin * 2); |
| 570 | reg.masked = false; |
570 | reg.masked = false; |
| 571 | io_apic_write(IOREDTBL + pin*2, reg.lo); |
571 | io_apic_write(IOREDTBL + pin*2, reg.lo); |
| 572 | } |
572 | } |
| 573 | 573 | ||
| 574 | } |
574 | } |