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| 1 | /* |
1 | /* |
| 2 | * Copyright (c) 2001-2004 Jakub Jermar |
2 | * Copyright (c) 2001-2004 Jakub Jermar |
| 3 | * All rights reserved. |
3 | * All rights reserved. |
| 4 | * |
4 | * |
| 5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
| 6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
| 7 | * are met: |
7 | * are met: |
| 8 | * |
8 | * |
| 9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
| 10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
| 11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
| 12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
| 13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
| 14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
| 15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
| 16 | * |
16 | * |
| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | */ |
27 | */ |
| 28 | 28 | ||
| 29 | /** @addtogroup ia32xen |
29 | /** @addtogroup ia32xen |
| 30 | * @{ |
30 | * @{ |
| 31 | */ |
31 | */ |
| 32 | /** @file |
32 | /** @file |
| 33 | */ |
33 | */ |
| 34 | 34 | ||
| 35 | #include <arch/types.h> |
35 | #include <arch/types.h> |
| 36 | #include <arch/smp/apic.h> |
36 | #include <arch/smp/apic.h> |
| 37 | #include <arch/smp/ap.h> |
37 | #include <arch/smp/ap.h> |
| 38 | #include <arch/smp/mps.h> |
38 | #include <arch/smp/mps.h> |
| 39 | #include <arch/boot/boot.h> |
- | |
| 40 | #include <mm/page.h> |
39 | #include <mm/page.h> |
| 41 | #include <time/delay.h> |
40 | #include <time/delay.h> |
| 42 | #include <interrupt.h> |
41 | #include <interrupt.h> |
| 43 | #include <arch/interrupt.h> |
42 | #include <arch/interrupt.h> |
| 44 | #include <print.h> |
43 | #include <print.h> |
| 45 | #include <arch/asm.h> |
44 | #include <arch/asm.h> |
| 46 | #include <arch.h> |
45 | #include <arch.h> |
| 47 | 46 | ||
| 48 | #ifdef CONFIG_SMP |
47 | #ifdef CONFIG_SMP |
| 49 | 48 | ||
| 50 | /* |
49 | /* |
| 51 | * Advanced Programmable Interrupt Controller for SMP systems. |
50 | * Advanced Programmable Interrupt Controller for SMP systems. |
| 52 | * Tested on: |
51 | * Tested on: |
| 53 | * Bochs 2.0.2 - Bochs 2.2.6 with 2-8 CPUs |
52 | * Bochs 2.0.2 - Bochs 2.2.6 with 2-8 CPUs |
| 54 | * Simics 2.0.28 - Simics 2.2.19 2-15 CPUs |
53 | * Simics 2.0.28 - Simics 2.2.19 2-15 CPUs |
| 55 | * VMware Workstation 5.5 with 2 CPUs |
54 | * VMware Workstation 5.5 with 2 CPUs |
| 56 | * QEMU 0.8.0 with 2-15 CPUs |
55 | * QEMU 0.8.0 with 2-15 CPUs |
| 57 | * ASUS P/I-P65UP5 + ASUS C-P55T2D REV. 1.41 with 2x 200Mhz Pentium CPUs |
56 | * ASUS P/I-P65UP5 + ASUS C-P55T2D REV. 1.41 with 2x 200Mhz Pentium CPUs |
| 58 | * ASUS PCH-DL with 2x 3000Mhz Pentium 4 Xeon (HT) CPUs |
57 | * ASUS PCH-DL with 2x 3000Mhz Pentium 4 Xeon (HT) CPUs |
| 59 | * MSI K7D Master-L with 2x 2100MHz Athlon MP CPUs |
58 | * MSI K7D Master-L with 2x 2100MHz Athlon MP CPUs |
| 60 | */ |
59 | */ |
| 61 | 60 | ||
| 62 | /* |
61 | /* |
| 63 | * These variables either stay configured as initilalized, or are changed by |
62 | * These variables either stay configured as initilalized, or are changed by |
| 64 | * the MP configuration code. |
63 | * the MP configuration code. |
| 65 | * |
64 | * |
| 66 | * Pay special attention to the volatile keyword. Without it, gcc -O2 would |
65 | * Pay special attention to the volatile keyword. Without it, gcc -O2 would |
| 67 | * optimize the code too much and accesses to l_apic and io_apic, that must |
66 | * optimize the code too much and accesses to l_apic and io_apic, that must |
| 68 | * always be 32-bit, would use byte oriented instructions. |
67 | * always be 32-bit, would use byte oriented instructions. |
| 69 | */ |
68 | */ |
| 70 | volatile uint32_t *l_apic = (uint32_t *) 0xfee00000; |
69 | volatile uint32_t *l_apic = (uint32_t *) 0xfee00000; |
| 71 | volatile uint32_t *io_apic = (uint32_t *) 0xfec00000; |
70 | volatile uint32_t *io_apic = (uint32_t *) 0xfec00000; |
| 72 | 71 | ||
| 73 | uint32_t apic_id_mask = 0; |
72 | uint32_t apic_id_mask = 0; |
| 74 | 73 | ||
| 75 | static int apic_poll_errors(void); |
74 | static int apic_poll_errors(void); |
| 76 | 75 | ||
| 77 | #ifdef LAPIC_VERBOSE |
76 | #ifdef LAPIC_VERBOSE |
| 78 | static char *delmod_str[] = { |
77 | static char *delmod_str[] = { |
| 79 | "Fixed", |
78 | "Fixed", |
| 80 | "Lowest Priority", |
79 | "Lowest Priority", |
| 81 | "SMI", |
80 | "SMI", |
| 82 | "Reserved", |
81 | "Reserved", |
| 83 | "NMI", |
82 | "NMI", |
| 84 | "INIT", |
83 | "INIT", |
| 85 | "STARTUP", |
84 | "STARTUP", |
| 86 | "ExtInt" |
85 | "ExtInt" |
| 87 | }; |
86 | }; |
| 88 | 87 | ||
| 89 | static char *destmod_str[] = { |
88 | static char *destmod_str[] = { |
| 90 | "Physical", |
89 | "Physical", |
| 91 | "Logical" |
90 | "Logical" |
| 92 | }; |
91 | }; |
| 93 | 92 | ||
| 94 | static char *trigmod_str[] = { |
93 | static char *trigmod_str[] = { |
| 95 | "Edge", |
94 | "Edge", |
| 96 | "Level" |
95 | "Level" |
| 97 | }; |
96 | }; |
| 98 | 97 | ||
| 99 | static char *mask_str[] = { |
98 | static char *mask_str[] = { |
| 100 | "Unmasked", |
99 | "Unmasked", |
| 101 | "Masked" |
100 | "Masked" |
| 102 | }; |
101 | }; |
| 103 | 102 | ||
| 104 | static char *delivs_str[] = { |
103 | static char *delivs_str[] = { |
| 105 | "Idle", |
104 | "Idle", |
| 106 | "Send Pending" |
105 | "Send Pending" |
| 107 | }; |
106 | }; |
| 108 | 107 | ||
| 109 | static char *tm_mode_str[] = { |
108 | static char *tm_mode_str[] = { |
| 110 | "One-shot", |
109 | "One-shot", |
| 111 | "Periodic" |
110 | "Periodic" |
| 112 | }; |
111 | }; |
| 113 | 112 | ||
| 114 | static char *intpol_str[] = { |
113 | static char *intpol_str[] = { |
| 115 | "Polarity High", |
114 | "Polarity High", |
| 116 | "Polarity Low" |
115 | "Polarity Low" |
| 117 | }; |
116 | }; |
| 118 | #endif /* LAPIC_VERBOSE */ |
117 | #endif /* LAPIC_VERBOSE */ |
| 119 | 118 | ||
| 120 | 119 | ||
| 121 | static void apic_spurious(int n, istate_t *istate); |
120 | static void apic_spurious(int n, istate_t *istate); |
| 122 | static void l_apic_timer_interrupt(int n, istate_t *istate); |
121 | static void l_apic_timer_interrupt(int n, istate_t *istate); |
| 123 | 122 | ||
| 124 | /** Initialize APIC on BSP. */ |
123 | /** Initialize APIC on BSP. */ |
| 125 | void apic_init(void) |
124 | void apic_init(void) |
| 126 | { |
125 | { |
| 127 | io_apic_id_t idreg; |
126 | io_apic_id_t idreg; |
| 128 | int i; |
127 | int i; |
| 129 | 128 | ||
| 130 | exc_register(VECTOR_APIC_SPUR, "apic_spurious", (iroutine) apic_spurious); |
129 | exc_register(VECTOR_APIC_SPUR, "apic_spurious", (iroutine) apic_spurious); |
| 131 | 130 | ||
| 132 | enable_irqs_function = io_apic_enable_irqs; |
131 | enable_irqs_function = io_apic_enable_irqs; |
| 133 | disable_irqs_function = io_apic_disable_irqs; |
132 | disable_irqs_function = io_apic_disable_irqs; |
| 134 | eoi_function = l_apic_eoi; |
133 | eoi_function = l_apic_eoi; |
| 135 | 134 | ||
| 136 | /* |
135 | /* |
| 137 | * Configure interrupt routing. |
136 | * Configure interrupt routing. |
| 138 | * IRQ 0 remains masked as the time signal is generated by l_apic's themselves. |
137 | * IRQ 0 remains masked as the time signal is generated by l_apic's themselves. |
| 139 | * Other interrupts will be forwarded to the lowest priority CPU. |
138 | * Other interrupts will be forwarded to the lowest priority CPU. |
| 140 | */ |
139 | */ |
| 141 | io_apic_disable_irqs(0xffff); |
140 | io_apic_disable_irqs(0xffff); |
| 142 | exc_register(VECTOR_CLK, "l_apic_timer", (iroutine) l_apic_timer_interrupt); |
141 | exc_register(VECTOR_CLK, "l_apic_timer", (iroutine) l_apic_timer_interrupt); |
| 143 | for (i = 0; i < IRQ_COUNT; i++) { |
142 | for (i = 0; i < IRQ_COUNT; i++) { |
| 144 | int pin; |
143 | int pin; |
| 145 | 144 | ||
| 146 | if ((pin = smp_irq_to_pin(i)) != -1) { |
145 | if ((pin = smp_irq_to_pin(i)) != -1) { |
| 147 | io_apic_change_ioredtbl(pin, DEST_ALL, IVT_IRQBASE+i, LOPRI); |
146 | io_apic_change_ioredtbl(pin, DEST_ALL, IVT_IRQBASE+i, LOPRI); |
| 148 | } |
147 | } |
| 149 | } |
148 | } |
| 150 | 149 | ||
| 151 | /* |
150 | /* |
| 152 | * Ensure that io_apic has unique ID. |
151 | * Ensure that io_apic has unique ID. |
| 153 | */ |
152 | */ |
| 154 | idreg.value = io_apic_read(IOAPICID); |
153 | idreg.value = io_apic_read(IOAPICID); |
| 155 | if ((1<<idreg.apic_id) & apic_id_mask) { /* see if IO APIC ID is used already */ |
154 | if ((1<<idreg.apic_id) & apic_id_mask) { /* see if IO APIC ID is used already */ |
| 156 | for (i = 0; i < APIC_ID_COUNT; i++) { |
155 | for (i = 0; i < APIC_ID_COUNT; i++) { |
| 157 | if (!((1<<i) & apic_id_mask)) { |
156 | if (!((1<<i) & apic_id_mask)) { |
| 158 | idreg.apic_id = i; |
157 | idreg.apic_id = i; |
| 159 | io_apic_write(IOAPICID, idreg.value); |
158 | io_apic_write(IOAPICID, idreg.value); |
| 160 | break; |
159 | break; |
| 161 | } |
160 | } |
| 162 | } |
161 | } |
| 163 | } |
162 | } |
| 164 | 163 | ||
| 165 | /* |
164 | /* |
| 166 | * Configure the BSP's lapic. |
165 | * Configure the BSP's lapic. |
| 167 | */ |
166 | */ |
| 168 | l_apic_init(); |
167 | l_apic_init(); |
| 169 | 168 | ||
| 170 | l_apic_debug(); |
169 | l_apic_debug(); |
| 171 | } |
170 | } |
| 172 | 171 | ||
| 173 | /** APIC spurious interrupt handler. |
172 | /** APIC spurious interrupt handler. |
| 174 | * |
173 | * |
| 175 | * @param n Interrupt vector. |
174 | * @param n Interrupt vector. |
| 176 | * @param istate Interrupted state. |
175 | * @param istate Interrupted state. |
| 177 | */ |
176 | */ |
| 178 | void apic_spurious(int n, istate_t *istate) |
177 | void apic_spurious(int n, istate_t *istate) |
| 179 | { |
178 | { |
| 180 | #ifdef CONFIG_DEBUG |
179 | #ifdef CONFIG_DEBUG |
| 181 | printf("cpu%d: APIC spurious interrupt\n", CPU->id); |
180 | printf("cpu%d: APIC spurious interrupt\n", CPU->id); |
| 182 | #endif |
181 | #endif |
| 183 | } |
182 | } |
| 184 | 183 | ||
| 185 | /** Poll for APIC errors. |
184 | /** Poll for APIC errors. |
| 186 | * |
185 | * |
| 187 | * Examine Error Status Register and report all errors found. |
186 | * Examine Error Status Register and report all errors found. |
| 188 | * |
187 | * |
| 189 | * @return 0 on error, 1 on success. |
188 | * @return 0 on error, 1 on success. |
| 190 | */ |
189 | */ |
| 191 | int apic_poll_errors(void) |
190 | int apic_poll_errors(void) |
| 192 | { |
191 | { |
| 193 | esr_t esr; |
192 | esr_t esr; |
| 194 | 193 | ||
| 195 | esr.value = l_apic[ESR]; |
194 | esr.value = l_apic[ESR]; |
| 196 | 195 | ||
| 197 | if (esr.send_checksum_error) |
196 | if (esr.send_checksum_error) |
| 198 | printf("Send Checksum Error\n"); |
197 | printf("Send Checksum Error\n"); |
| 199 | if (esr.receive_checksum_error) |
198 | if (esr.receive_checksum_error) |
| 200 | printf("Receive Checksum Error\n"); |
199 | printf("Receive Checksum Error\n"); |
| 201 | if (esr.send_accept_error) |
200 | if (esr.send_accept_error) |
| 202 | printf("Send Accept Error\n"); |
201 | printf("Send Accept Error\n"); |
| 203 | if (esr.receive_accept_error) |
202 | if (esr.receive_accept_error) |
| 204 | printf("Receive Accept Error\n"); |
203 | printf("Receive Accept Error\n"); |
| 205 | if (esr.send_illegal_vector) |
204 | if (esr.send_illegal_vector) |
| 206 | printf("Send Illegal Vector\n"); |
205 | printf("Send Illegal Vector\n"); |
| 207 | if (esr.received_illegal_vector) |
206 | if (esr.received_illegal_vector) |
| 208 | printf("Received Illegal Vector\n"); |
207 | printf("Received Illegal Vector\n"); |
| 209 | if (esr.illegal_register_address) |
208 | if (esr.illegal_register_address) |
| 210 | printf("Illegal Register Address\n"); |
209 | printf("Illegal Register Address\n"); |
| 211 | 210 | ||
| 212 | return !esr.err_bitmap; |
211 | return !esr.err_bitmap; |
| 213 | } |
212 | } |
| 214 | 213 | ||
| 215 | /** Send all CPUs excluding CPU IPI vector. |
214 | /** Send all CPUs excluding CPU IPI vector. |
| 216 | * |
215 | * |
| 217 | * @param vector Interrupt vector to be sent. |
216 | * @param vector Interrupt vector to be sent. |
| 218 | * |
217 | * |
| 219 | * @return 0 on failure, 1 on success. |
218 | * @return 0 on failure, 1 on success. |
| 220 | */ |
219 | */ |
| 221 | int l_apic_broadcast_custom_ipi(uint8_t vector) |
220 | int l_apic_broadcast_custom_ipi(uint8_t vector) |
| 222 | { |
221 | { |
| 223 | icr_t icr; |
222 | icr_t icr; |
| 224 | 223 | ||
| 225 | icr.lo = l_apic[ICRlo]; |
224 | icr.lo = l_apic[ICRlo]; |
| 226 | icr.delmod = DELMOD_FIXED; |
225 | icr.delmod = DELMOD_FIXED; |
| 227 | icr.destmod = DESTMOD_LOGIC; |
226 | icr.destmod = DESTMOD_LOGIC; |
| 228 | icr.level = LEVEL_ASSERT; |
227 | icr.level = LEVEL_ASSERT; |
| 229 | icr.shorthand = SHORTHAND_ALL_EXCL; |
228 | icr.shorthand = SHORTHAND_ALL_EXCL; |
| 230 | icr.trigger_mode = TRIGMOD_LEVEL; |
229 | icr.trigger_mode = TRIGMOD_LEVEL; |
| 231 | icr.vector = vector; |
230 | icr.vector = vector; |
| 232 | 231 | ||
| 233 | l_apic[ICRlo] = icr.lo; |
232 | l_apic[ICRlo] = icr.lo; |
| 234 | 233 | ||
| 235 | icr.lo = l_apic[ICRlo]; |
234 | icr.lo = l_apic[ICRlo]; |
| 236 | if (icr.delivs == DELIVS_PENDING) { |
235 | if (icr.delivs == DELIVS_PENDING) { |
| 237 | #ifdef CONFIG_DEBUG |
236 | #ifdef CONFIG_DEBUG |
| 238 | printf("IPI is pending.\n"); |
237 | printf("IPI is pending.\n"); |
| 239 | #endif |
238 | #endif |
| 240 | } |
239 | } |
| 241 | 240 | ||
| 242 | return apic_poll_errors(); |
241 | return apic_poll_errors(); |
| 243 | } |
242 | } |
| 244 | 243 | ||
| 245 | /** Universal Start-up Algorithm for bringing up the AP processors. |
244 | /** Universal Start-up Algorithm for bringing up the AP processors. |
| 246 | * |
245 | * |
| 247 | * @param apicid APIC ID of the processor to be brought up. |
246 | * @param apicid APIC ID of the processor to be brought up. |
| 248 | * |
247 | * |
| 249 | * @return 0 on failure, 1 on success. |
248 | * @return 0 on failure, 1 on success. |
| 250 | */ |
249 | */ |
| 251 | int l_apic_send_init_ipi(uint8_t apicid) |
250 | int l_apic_send_init_ipi(uint8_t apicid) |
| 252 | { |
251 | { |
| 253 | icr_t icr; |
252 | icr_t icr; |
| 254 | int i; |
253 | int i; |
| 255 | 254 | ||
| 256 | /* |
255 | /* |
| 257 | * Read the ICR register in and zero all non-reserved fields. |
256 | * Read the ICR register in and zero all non-reserved fields. |
| 258 | */ |
257 | */ |
| 259 | icr.lo = l_apic[ICRlo]; |
258 | icr.lo = l_apic[ICRlo]; |
| 260 | icr.hi = l_apic[ICRhi]; |
259 | icr.hi = l_apic[ICRhi]; |
| 261 | 260 | ||
| 262 | icr.delmod = DELMOD_INIT; |
261 | icr.delmod = DELMOD_INIT; |
| 263 | icr.destmod = DESTMOD_PHYS; |
262 | icr.destmod = DESTMOD_PHYS; |
| 264 | icr.level = LEVEL_ASSERT; |
263 | icr.level = LEVEL_ASSERT; |
| 265 | icr.trigger_mode = TRIGMOD_LEVEL; |
264 | icr.trigger_mode = TRIGMOD_LEVEL; |
| 266 | icr.shorthand = SHORTHAND_NONE; |
265 | icr.shorthand = SHORTHAND_NONE; |
| 267 | icr.vector = 0; |
266 | icr.vector = 0; |
| 268 | icr.dest = apicid; |
267 | icr.dest = apicid; |
| 269 | 268 | ||
| 270 | l_apic[ICRhi] = icr.hi; |
269 | l_apic[ICRhi] = icr.hi; |
| 271 | l_apic[ICRlo] = icr.lo; |
270 | l_apic[ICRlo] = icr.lo; |
| 272 | 271 | ||
| 273 | /* |
272 | /* |
| 274 | * According to MP Specification, 20us should be enough to |
273 | * According to MP Specification, 20us should be enough to |
| 275 | * deliver the IPI. |
274 | * deliver the IPI. |
| 276 | */ |
275 | */ |
| 277 | delay(20); |
276 | delay(20); |
| 278 | 277 | ||
| 279 | if (!apic_poll_errors()) |
278 | if (!apic_poll_errors()) |
| 280 | return 0; |
279 | return 0; |
| 281 | 280 | ||
| 282 | icr.lo = l_apic[ICRlo]; |
281 | icr.lo = l_apic[ICRlo]; |
| 283 | if (icr.delivs == DELIVS_PENDING) { |
282 | if (icr.delivs == DELIVS_PENDING) { |
| 284 | #ifdef CONFIG_DEBUG |
283 | #ifdef CONFIG_DEBUG |
| 285 | printf("IPI is pending.\n"); |
284 | printf("IPI is pending.\n"); |
| 286 | #endif |
285 | #endif |
| 287 | } |
286 | } |
| 288 | 287 | ||
| 289 | icr.delmod = DELMOD_INIT; |
288 | icr.delmod = DELMOD_INIT; |
| 290 | icr.destmod = DESTMOD_PHYS; |
289 | icr.destmod = DESTMOD_PHYS; |
| 291 | icr.level = LEVEL_DEASSERT; |
290 | icr.level = LEVEL_DEASSERT; |
| 292 | icr.shorthand = SHORTHAND_NONE; |
291 | icr.shorthand = SHORTHAND_NONE; |
| 293 | icr.trigger_mode = TRIGMOD_LEVEL; |
292 | icr.trigger_mode = TRIGMOD_LEVEL; |
| 294 | icr.vector = 0; |
293 | icr.vector = 0; |
| 295 | l_apic[ICRlo] = icr.lo; |
294 | l_apic[ICRlo] = icr.lo; |
| 296 | 295 | ||
| 297 | /* |
296 | /* |
| 298 | * Wait 10ms as MP Specification specifies. |
297 | * Wait 10ms as MP Specification specifies. |
| 299 | */ |
298 | */ |
| 300 | delay(10000); |
299 | delay(10000); |
| 301 | 300 | ||
| 302 | if (!is_82489DX_apic(l_apic[LAVR])) { |
301 | if (!is_82489DX_apic(l_apic[LAVR])) { |
| 303 | /* |
302 | /* |
| 304 | * If this is not 82489DX-based l_apic we must send two STARTUP IPI's. |
303 | * If this is not 82489DX-based l_apic we must send two STARTUP IPI's. |
| 305 | */ |
304 | */ |
| 306 | for (i = 0; i<2; i++) { |
305 | for (i = 0; i<2; i++) { |
| 307 | icr.lo = l_apic[ICRlo]; |
306 | icr.lo = l_apic[ICRlo]; |
| 308 | icr.delmod = DELMOD_STARTUP; |
307 | icr.delmod = DELMOD_STARTUP; |
| 309 | icr.destmod = DESTMOD_PHYS; |
308 | icr.destmod = DESTMOD_PHYS; |
| 310 | icr.level = LEVEL_ASSERT; |
309 | icr.level = LEVEL_ASSERT; |
| 311 | icr.shorthand = SHORTHAND_NONE; |
310 | icr.shorthand = SHORTHAND_NONE; |
| 312 | icr.trigger_mode = TRIGMOD_LEVEL; |
311 | icr.trigger_mode = TRIGMOD_LEVEL; |
| 313 | l_apic[ICRlo] = icr.lo; |
312 | l_apic[ICRlo] = icr.lo; |
| 314 | delay(200); |
313 | delay(200); |
| 315 | } |
314 | } |
| 316 | } |
315 | } |
| 317 | 316 | ||
| 318 | return apic_poll_errors(); |
317 | return apic_poll_errors(); |
| 319 | } |
318 | } |
| 320 | 319 | ||
| 321 | /** Initialize Local APIC. */ |
320 | /** Initialize Local APIC. */ |
| 322 | void l_apic_init(void) |
321 | void l_apic_init(void) |
| 323 | { |
322 | { |
| 324 | lvt_error_t error; |
323 | lvt_error_t error; |
| 325 | lvt_lint_t lint; |
324 | lvt_lint_t lint; |
| 326 | tpr_t tpr; |
325 | tpr_t tpr; |
| 327 | svr_t svr; |
326 | svr_t svr; |
| 328 | icr_t icr; |
327 | icr_t icr; |
| 329 | tdcr_t tdcr; |
328 | tdcr_t tdcr; |
| 330 | lvt_tm_t tm; |
329 | lvt_tm_t tm; |
| 331 | ldr_t ldr; |
330 | ldr_t ldr; |
| 332 | dfr_t dfr; |
331 | dfr_t dfr; |
| 333 | uint32_t t1, t2; |
332 | uint32_t t1, t2; |
| 334 | 333 | ||
| 335 | /* Initialize LVT Error register. */ |
334 | /* Initialize LVT Error register. */ |
| 336 | error.value = l_apic[LVT_Err]; |
335 | error.value = l_apic[LVT_Err]; |
| 337 | error.masked = true; |
336 | error.masked = true; |
| 338 | l_apic[LVT_Err] = error.value; |
337 | l_apic[LVT_Err] = error.value; |
| 339 | 338 | ||
| 340 | /* Initialize LVT LINT0 register. */ |
339 | /* Initialize LVT LINT0 register. */ |
| 341 | lint.value = l_apic[LVT_LINT0]; |
340 | lint.value = l_apic[LVT_LINT0]; |
| 342 | lint.masked = true; |
341 | lint.masked = true; |
| 343 | l_apic[LVT_LINT0] = lint.value; |
342 | l_apic[LVT_LINT0] = lint.value; |
| 344 | 343 | ||
| 345 | /* Initialize LVT LINT1 register. */ |
344 | /* Initialize LVT LINT1 register. */ |
| 346 | lint.value = l_apic[LVT_LINT1]; |
345 | lint.value = l_apic[LVT_LINT1]; |
| 347 | lint.masked = true; |
346 | lint.masked = true; |
| 348 | l_apic[LVT_LINT1] = lint.value; |
347 | l_apic[LVT_LINT1] = lint.value; |
| 349 | 348 | ||
| 350 | /* Task Priority Register initialization. */ |
349 | /* Task Priority Register initialization. */ |
| 351 | tpr.value = l_apic[TPR]; |
350 | tpr.value = l_apic[TPR]; |
| 352 | tpr.pri_sc = 0; |
351 | tpr.pri_sc = 0; |
| 353 | tpr.pri = 0; |
352 | tpr.pri = 0; |
| 354 | l_apic[TPR] = tpr.value; |
353 | l_apic[TPR] = tpr.value; |
| 355 | 354 | ||
| 356 | /* Spurious-Interrupt Vector Register initialization. */ |
355 | /* Spurious-Interrupt Vector Register initialization. */ |
| 357 | svr.value = l_apic[SVR]; |
356 | svr.value = l_apic[SVR]; |
| 358 | svr.vector = VECTOR_APIC_SPUR; |
357 | svr.vector = VECTOR_APIC_SPUR; |
| 359 | svr.lapic_enabled = true; |
358 | svr.lapic_enabled = true; |
| 360 | svr.focus_checking = true; |
359 | svr.focus_checking = true; |
| 361 | l_apic[SVR] = svr.value; |
360 | l_apic[SVR] = svr.value; |
| 362 | 361 | ||
| 363 | if (CPU->arch.family >= 6) |
362 | if (CPU->arch.family >= 6) |
| 364 | enable_l_apic_in_msr(); |
363 | enable_l_apic_in_msr(); |
| 365 | 364 | ||
| 366 | /* Interrupt Command Register initialization. */ |
365 | /* Interrupt Command Register initialization. */ |
| 367 | icr.lo = l_apic[ICRlo]; |
366 | icr.lo = l_apic[ICRlo]; |
| 368 | icr.delmod = DELMOD_INIT; |
367 | icr.delmod = DELMOD_INIT; |
| 369 | icr.destmod = DESTMOD_PHYS; |
368 | icr.destmod = DESTMOD_PHYS; |
| 370 | icr.level = LEVEL_DEASSERT; |
369 | icr.level = LEVEL_DEASSERT; |
| 371 | icr.shorthand = SHORTHAND_ALL_INCL; |
370 | icr.shorthand = SHORTHAND_ALL_INCL; |
| 372 | icr.trigger_mode = TRIGMOD_LEVEL; |
371 | icr.trigger_mode = TRIGMOD_LEVEL; |
| 373 | l_apic[ICRlo] = icr.lo; |
372 | l_apic[ICRlo] = icr.lo; |
| 374 | 373 | ||
| 375 | /* Timer Divide Configuration Register initialization. */ |
374 | /* Timer Divide Configuration Register initialization. */ |
| 376 | tdcr.value = l_apic[TDCR]; |
375 | tdcr.value = l_apic[TDCR]; |
| 377 | tdcr.div_value = DIVIDE_1; |
376 | tdcr.div_value = DIVIDE_1; |
| 378 | l_apic[TDCR] = tdcr.value; |
377 | l_apic[TDCR] = tdcr.value; |
| 379 | 378 | ||
| 380 | /* Program local timer. */ |
379 | /* Program local timer. */ |
| 381 | tm.value = l_apic[LVT_Tm]; |
380 | tm.value = l_apic[LVT_Tm]; |
| 382 | tm.vector = VECTOR_CLK; |
381 | tm.vector = VECTOR_CLK; |
| 383 | tm.mode = TIMER_PERIODIC; |
382 | tm.mode = TIMER_PERIODIC; |
| 384 | tm.masked = false; |
383 | tm.masked = false; |
| 385 | l_apic[LVT_Tm] = tm.value; |
384 | l_apic[LVT_Tm] = tm.value; |
| 386 | 385 | ||
| 387 | /* |
386 | /* |
| 388 | * Measure and configure the timer to generate timer |
387 | * Measure and configure the timer to generate timer |
| 389 | * interrupt with period 1s/HZ seconds. |
388 | * interrupt with period 1s/HZ seconds. |
| 390 | */ |
389 | */ |
| 391 | t1 = l_apic[CCRT]; |
390 | t1 = l_apic[CCRT]; |
| 392 | l_apic[ICRT] = 0xffffffff; |
391 | l_apic[ICRT] = 0xffffffff; |
| 393 | 392 | ||
| 394 | while (l_apic[CCRT] == t1) |
393 | while (l_apic[CCRT] == t1) |
| 395 | ; |
394 | ; |
| 396 | 395 | ||
| 397 | t1 = l_apic[CCRT]; |
396 | t1 = l_apic[CCRT]; |
| 398 | delay(1000000/HZ); |
397 | delay(1000000/HZ); |
| 399 | t2 = l_apic[CCRT]; |
398 | t2 = l_apic[CCRT]; |
| 400 | 399 | ||
| 401 | l_apic[ICRT] = t1-t2; |
400 | l_apic[ICRT] = t1-t2; |
| 402 | 401 | ||
| 403 | /* Program Logical Destination Register. */ |
402 | /* Program Logical Destination Register. */ |
| 404 | ldr.value = l_apic[LDR]; |
403 | ldr.value = l_apic[LDR]; |
| 405 | if (CPU->id < sizeof(CPU->id)*8) /* size in bits */ |
404 | if (CPU->id < sizeof(CPU->id)*8) /* size in bits */ |
| 406 | ldr.id = (1<<CPU->id); |
405 | ldr.id = (1<<CPU->id); |
| 407 | l_apic[LDR] = ldr.value; |
406 | l_apic[LDR] = ldr.value; |
| 408 | 407 | ||
| 409 | /* Program Destination Format Register for Flat mode. */ |
408 | /* Program Destination Format Register for Flat mode. */ |
| 410 | dfr.value = l_apic[DFR]; |
409 | dfr.value = l_apic[DFR]; |
| 411 | dfr.model = MODEL_FLAT; |
410 | dfr.model = MODEL_FLAT; |
| 412 | l_apic[DFR] = dfr.value; |
411 | l_apic[DFR] = dfr.value; |
| 413 | } |
412 | } |
| 414 | 413 | ||
| 415 | /** Local APIC End of Interrupt. */ |
414 | /** Local APIC End of Interrupt. */ |
| 416 | void l_apic_eoi(void) |
415 | void l_apic_eoi(void) |
| 417 | { |
416 | { |
| 418 | l_apic[EOI] = 0; |
417 | l_apic[EOI] = 0; |
| 419 | } |
418 | } |
| 420 | 419 | ||
| 421 | /** Dump content of Local APIC registers. */ |
420 | /** Dump content of Local APIC registers. */ |
| 422 | void l_apic_debug(void) |
421 | void l_apic_debug(void) |
| 423 | { |
422 | { |
| 424 | #ifdef LAPIC_VERBOSE |
423 | #ifdef LAPIC_VERBOSE |
| 425 | lvt_tm_t tm; |
424 | lvt_tm_t tm; |
| 426 | lvt_lint_t lint; |
425 | lvt_lint_t lint; |
| 427 | lvt_error_t error; |
426 | lvt_error_t error; |
| 428 | 427 | ||
| 429 | printf("LVT on cpu%d, LAPIC ID: %d\n", CPU->id, l_apic_id()); |
428 | printf("LVT on cpu%d, LAPIC ID: %d\n", CPU->id, l_apic_id()); |
| 430 | 429 | ||
| 431 | tm.value = l_apic[LVT_Tm]; |
430 | tm.value = l_apic[LVT_Tm]; |
| 432 | printf("LVT Tm: vector=%hhd, %s, %s, %s\n", tm.vector, delivs_str[tm.delivs], mask_str[tm.masked], tm_mode_str[tm.mode]); |
431 | printf("LVT Tm: vector=%hhd, %s, %s, %s\n", tm.vector, delivs_str[tm.delivs], mask_str[tm.masked], tm_mode_str[tm.mode]); |
| 433 | lint.value = l_apic[LVT_LINT0]; |
432 | lint.value = l_apic[LVT_LINT0]; |
| 434 | printf("LVT LINT0: vector=%hhd, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]); |
433 | printf("LVT LINT0: vector=%hhd, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]); |
| 435 | lint.value = l_apic[LVT_LINT1]; |
434 | lint.value = l_apic[LVT_LINT1]; |
| 436 | printf("LVT LINT1: vector=%hhd, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]); |
435 | printf("LVT LINT1: vector=%hhd, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]); |
| 437 | error.value = l_apic[LVT_Err]; |
436 | error.value = l_apic[LVT_Err]; |
| 438 | printf("LVT Err: vector=%hhd, %s, %s\n", error.vector, delivs_str[error.delivs], mask_str[error.masked]); |
437 | printf("LVT Err: vector=%hhd, %s, %s\n", error.vector, delivs_str[error.delivs], mask_str[error.masked]); |
| 439 | #endif |
438 | #endif |
| 440 | } |
439 | } |
| 441 | 440 | ||
| 442 | /** Local APIC Timer Interrupt. |
441 | /** Local APIC Timer Interrupt. |
| 443 | * |
442 | * |
| 444 | * @param n Interrupt vector number. |
443 | * @param n Interrupt vector number. |
| 445 | * @param istate Interrupted state. |
444 | * @param istate Interrupted state. |
| 446 | */ |
445 | */ |
| 447 | void l_apic_timer_interrupt(int n, istate_t *istate) |
446 | void l_apic_timer_interrupt(int n, istate_t *istate) |
| 448 | { |
447 | { |
| 449 | l_apic_eoi(); |
448 | l_apic_eoi(); |
| 450 | clock(); |
449 | clock(); |
| 451 | } |
450 | } |
| 452 | 451 | ||
| 453 | /** Get Local APIC ID. |
452 | /** Get Local APIC ID. |
| 454 | * |
453 | * |
| 455 | * @return Local APIC ID. |
454 | * @return Local APIC ID. |
| 456 | */ |
455 | */ |
| 457 | uint8_t l_apic_id(void) |
456 | uint8_t l_apic_id(void) |
| 458 | { |
457 | { |
| 459 | l_apic_id_t idreg; |
458 | l_apic_id_t idreg; |
| 460 | 459 | ||
| 461 | idreg.value = l_apic[L_APIC_ID]; |
460 | idreg.value = l_apic[L_APIC_ID]; |
| 462 | return idreg.apic_id; |
461 | return idreg.apic_id; |
| 463 | } |
462 | } |
| 464 | 463 | ||
| 465 | /** Read from IO APIC register. |
464 | /** Read from IO APIC register. |
| 466 | * |
465 | * |
| 467 | * @param address IO APIC register address. |
466 | * @param address IO APIC register address. |
| 468 | * |
467 | * |
| 469 | * @return Content of the addressed IO APIC register. |
468 | * @return Content of the addressed IO APIC register. |
| 470 | */ |
469 | */ |
| 471 | uint32_t io_apic_read(uint8_t address) |
470 | uint32_t io_apic_read(uint8_t address) |
| 472 | { |
471 | { |
| 473 | io_regsel_t regsel; |
472 | io_regsel_t regsel; |
| 474 | 473 | ||
| 475 | regsel.value = io_apic[IOREGSEL]; |
474 | regsel.value = io_apic[IOREGSEL]; |
| 476 | regsel.reg_addr = address; |
475 | regsel.reg_addr = address; |
| 477 | io_apic[IOREGSEL] = regsel.value; |
476 | io_apic[IOREGSEL] = regsel.value; |
| 478 | return io_apic[IOWIN]; |
477 | return io_apic[IOWIN]; |
| 479 | } |
478 | } |
| 480 | 479 | ||
| 481 | /** Write to IO APIC register. |
480 | /** Write to IO APIC register. |
| 482 | * |
481 | * |
| 483 | * @param address IO APIC register address. |
482 | * @param address IO APIC register address. |
| 484 | * @param x Content to be written to the addressed IO APIC register. |
483 | * @param x Content to be written to the addressed IO APIC register. |
| 485 | */ |
484 | */ |
| 486 | void io_apic_write(uint8_t address, uint32_t x) |
485 | void io_apic_write(uint8_t address, uint32_t x) |
| 487 | { |
486 | { |
| 488 | io_regsel_t regsel; |
487 | io_regsel_t regsel; |
| 489 | 488 | ||
| 490 | regsel.value = io_apic[IOREGSEL]; |
489 | regsel.value = io_apic[IOREGSEL]; |
| 491 | regsel.reg_addr = address; |
490 | regsel.reg_addr = address; |
| 492 | io_apic[IOREGSEL] = regsel.value; |
491 | io_apic[IOREGSEL] = regsel.value; |
| 493 | io_apic[IOWIN] = x; |
492 | io_apic[IOWIN] = x; |
| 494 | } |
493 | } |
| 495 | 494 | ||
| 496 | /** Change some attributes of one item in I/O Redirection Table. |
495 | /** Change some attributes of one item in I/O Redirection Table. |
| 497 | * |
496 | * |
| 498 | * @param pin IO APIC pin number. |
497 | * @param pin IO APIC pin number. |
| 499 | * @param dest Interrupt destination address. |
498 | * @param dest Interrupt destination address. |
| 500 | * @param v Interrupt vector to trigger. |
499 | * @param v Interrupt vector to trigger. |
| 501 | * @param flags Flags. |
500 | * @param flags Flags. |
| 502 | */ |
501 | */ |
| 503 | void io_apic_change_ioredtbl(int pin, int dest, uint8_t v, int flags) |
502 | void io_apic_change_ioredtbl(int pin, int dest, uint8_t v, int flags) |
| 504 | { |
503 | { |
| 505 | io_redirection_reg_t reg; |
504 | io_redirection_reg_t reg; |
| 506 | int dlvr = DELMOD_FIXED; |
505 | int dlvr = DELMOD_FIXED; |
| 507 | 506 | ||
| 508 | if (flags & LOPRI) |
507 | if (flags & LOPRI) |
| 509 | dlvr = DELMOD_LOWPRI; |
508 | dlvr = DELMOD_LOWPRI; |
| 510 | 509 | ||
| 511 | reg.lo = io_apic_read(IOREDTBL + pin*2); |
510 | reg.lo = io_apic_read(IOREDTBL + pin*2); |
| 512 | reg.hi = io_apic_read(IOREDTBL + pin*2 + 1); |
511 | reg.hi = io_apic_read(IOREDTBL + pin*2 + 1); |
| 513 | 512 | ||
| 514 | reg.dest = dest; |
513 | reg.dest = dest; |
| 515 | reg.destmod = DESTMOD_LOGIC; |
514 | reg.destmod = DESTMOD_LOGIC; |
| 516 | reg.trigger_mode = TRIGMOD_EDGE; |
515 | reg.trigger_mode = TRIGMOD_EDGE; |
| 517 | reg.intpol = POLARITY_HIGH; |
516 | reg.intpol = POLARITY_HIGH; |
| 518 | reg.delmod = dlvr; |
517 | reg.delmod = dlvr; |
| 519 | reg.intvec = v; |
518 | reg.intvec = v; |
| 520 | 519 | ||
| 521 | io_apic_write(IOREDTBL + pin*2, reg.lo); |
520 | io_apic_write(IOREDTBL + pin*2, reg.lo); |
| 522 | io_apic_write(IOREDTBL + pin*2 + 1, reg.hi); |
521 | io_apic_write(IOREDTBL + pin*2 + 1, reg.hi); |
| 523 | } |
522 | } |
| 524 | 523 | ||
| 525 | /** Mask IRQs in IO APIC. |
524 | /** Mask IRQs in IO APIC. |
| 526 | * |
525 | * |
| 527 | * @param irqmask Bitmask of IRQs to be masked (0 = do not mask, 1 = mask). |
526 | * @param irqmask Bitmask of IRQs to be masked (0 = do not mask, 1 = mask). |
| 528 | */ |
527 | */ |
| 529 | void io_apic_disable_irqs(uint16_t irqmask) |
528 | void io_apic_disable_irqs(uint16_t irqmask) |
| 530 | { |
529 | { |
| 531 | io_redirection_reg_t reg; |
530 | io_redirection_reg_t reg; |
| 532 | int i, pin; |
531 | int i, pin; |
| 533 | 532 | ||
| 534 | for (i=0;i<16;i++) { |
533 | for (i=0;i<16;i++) { |
| 535 | if (irqmask & (1<<i)) { |
534 | if (irqmask & (1<<i)) { |
| 536 | /* |
535 | /* |
| 537 | * Mask the signal input in IO APIC if there is a |
536 | * Mask the signal input in IO APIC if there is a |
| 538 | * mapping for the respective IRQ number. |
537 | * mapping for the respective IRQ number. |
| 539 | */ |
538 | */ |
| 540 | pin = smp_irq_to_pin(i); |
539 | pin = smp_irq_to_pin(i); |
| 541 | if (pin != -1) { |
540 | if (pin != -1) { |
| 542 | reg.lo = io_apic_read(IOREDTBL + pin*2); |
541 | reg.lo = io_apic_read(IOREDTBL + pin*2); |
| 543 | reg.masked = true; |
542 | reg.masked = true; |
| 544 | io_apic_write(IOREDTBL + pin*2, reg.lo); |
543 | io_apic_write(IOREDTBL + pin*2, reg.lo); |
| 545 | } |
544 | } |
| 546 | 545 | ||
| 547 | } |
546 | } |
| 548 | } |
547 | } |
| 549 | } |
548 | } |
| 550 | 549 | ||
| 551 | /** Unmask IRQs in IO APIC. |
550 | /** Unmask IRQs in IO APIC. |
| 552 | * |
551 | * |
| 553 | * @param irqmask Bitmask of IRQs to be unmasked (0 = do not unmask, 1 = unmask). |
552 | * @param irqmask Bitmask of IRQs to be unmasked (0 = do not unmask, 1 = unmask). |
| 554 | */ |
553 | */ |
| 555 | void io_apic_enable_irqs(uint16_t irqmask) |
554 | void io_apic_enable_irqs(uint16_t irqmask) |
| 556 | { |
555 | { |
| 557 | int i, pin; |
556 | int i, pin; |
| 558 | io_redirection_reg_t reg; |
557 | io_redirection_reg_t reg; |
| 559 | 558 | ||
| 560 | for (i=0;i<16;i++) { |
559 | for (i=0;i<16;i++) { |
| 561 | if (irqmask & (1<<i)) { |
560 | if (irqmask & (1<<i)) { |
| 562 | /* |
561 | /* |
| 563 | * Unmask the signal input in IO APIC if there is a |
562 | * Unmask the signal input in IO APIC if there is a |
| 564 | * mapping for the respective IRQ number. |
563 | * mapping for the respective IRQ number. |
| 565 | */ |
564 | */ |
| 566 | pin = smp_irq_to_pin(i); |
565 | pin = smp_irq_to_pin(i); |
| 567 | if (pin != -1) { |
566 | if (pin != -1) { |
| 568 | reg.lo = io_apic_read(IOREDTBL + pin*2); |
567 | reg.lo = io_apic_read(IOREDTBL + pin*2); |
| 569 | reg.masked = false; |
568 | reg.masked = false; |
| 570 | io_apic_write(IOREDTBL + pin*2, reg.lo); |
569 | io_apic_write(IOREDTBL + pin*2, reg.lo); |
| 571 | } |
570 | } |
| 572 | 571 | ||
| 573 | } |
572 | } |
| 574 | } |
573 | } |
| 575 | } |
574 | } |
| 576 | 575 | ||
| 577 | #endif /* CONFIG_SMP */ |
576 | #endif /* CONFIG_SMP */ |
| 578 | 577 | ||
| 579 | /** @} |
578 | /** @} |
| 580 | */ |
579 | */ |
| 581 | 580 | ||