WebSVN – HelenOS – Diff – /trunk/kernel/arch/ia32xen/src/pm.c


/*
 * Copyright (c) 2006 Martin Decky
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup ia32xen
 * @{
 */
/** @file
 */
 
#include <arch/pm.h>
#include <config.h>
#include <arch/types.h>
#include <arch/interrupt.h>
#include <arch/asm.h>
#include <arch/context.h>
#include <panic.h>
#include <arch/mm/page.h>
#include <mm/slab.h>
#include <memstr.h>
#include <interrupt.h>
 
/*
 * Early ia32xen configuration functions and data structures.
 */
 
/*
 * We have no use for segmentation so we set up flat mode. In this
 * mode, we use, for each privilege level, two segments spanning the
 * whole memory. One is for code and one is for data.
 *
 * One is for GS register which holds pointer to the TLS thread
 * structure in it's base.
 */
descriptor_t gdt[GDT_ITEMS] = {
    /* NULL descriptor */
    { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
    /* KTEXT descriptor */
    { 0xffff, 0, 0, AR_PRESENT | AR_CODE | DPL_KERNEL, 0xf, 0, 0, 1, 1, 0 },
    /* KDATA descriptor */
    { 0xffff, 0, 0, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_KERNEL, 0xf, 0, 0, 1, 1, 0 },
    /* UTEXT descriptor */
    { 0xffff, 0, 0, AR_PRESENT | AR_CODE | DPL_USER, 0xf, 0, 0, 1, 1, 0 },
    /* UDATA descriptor */
    { 0xffff, 0, 0, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER, 0xf, 0, 0, 1, 1, 0 },
    /* TSS descriptor - set up will be completed later */
    { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
    /* TLS descriptor */
    { 0xffff, 0, 0, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER, 0xf, 0, 0, 1, 1, 0 },
};
 
static trap_info_t traps[IDT_ITEMS + 1];
 
static tss_t tss;
 
tss_t *tss_p = NULL;
 
/* gdtr is changed by kmp before next CPU is initialized */
ptr_16_32_t bootstrap_gdtr = { .limit = sizeof(gdt), .base = KA2PA((uintptr_t) gdt) };
ptr_16_32_t gdtr = { .limit = sizeof(gdt), .base = (uintptr_t) gdt };
 
void gdt_setbase(descriptor_t *d, uintptr_t base)
{
    d->base_0_15 = base & 0xffff;
    d->base_16_23 = ((base) >> 16) & 0xff;
    d->base_24_31 = ((base) >> 24) & 0xff;
}
 
void gdt_setlimit(descriptor_t *d, uint32_t limit)
{
    d->limit_0_15 = limit & 0xffff;
    d->limit_16_19 = (limit >> 16) & 0xf;
}
 
void tss_initialize(tss_t *t)
{
    memsetb(t, sizeof(struct tss), 0);
}
 
static void trap(void)
{
}
 
void traps_init(void)
{
    index_t i;
   
    for (i = 0; i < IDT_ITEMS; i++) {
        traps[i].vector = i;
       
        if (i == VECTOR_SYSCALL)
            traps[i].flags = 3;
        else
            traps[i].flags = 0;
       
        traps[i].cs = XEN_CS;
        traps[i].address = trap;
    }
    traps[IDT_ITEMS].vector = 0;
    traps[IDT_ITEMS].flags = 0;
    traps[IDT_ITEMS].cs = 0;
    traps[IDT_ITEMS].address = NULL;
}
 
 
/* Clean IOPL(12,13) and NT(14) flags in EFLAGS register */
static void clean_IOPL_NT_flags(void)
{
//  asm volatile (
//      "pushfl\n"
//      "pop %%eax\n"
//      "and $0xffff8fff, %%eax\n"
//      "push %%eax\n"
//      "popfl\n"
//      : : : "eax"
//  );
}
 
/* Clean AM(18) flag in CR0 register */
static void clean_AM_flag(void)
{
//  asm volatile (
//      "mov %%cr0, %%eax\n"
//      "and $0xfffbffff, %%eax\n"
//      "mov %%eax, %%cr0\n"
//      : : : "eax"
//  );
}
 
void pm_init(void)
{
    descriptor_t *gdt_p = (descriptor_t *) gdtr.base;
 
//  gdtr_load(&gdtr);
   
    if (config.cpu_active == 1) {
        traps_init();
        xen_set_trap_table(traps);
        /*
         * NOTE: bootstrap CPU has statically allocated TSS, because
         * the heap hasn't been initialized so far.
         */
        tss_p = &tss;
    } else {
        tss_p = (tss_t *) malloc(sizeof(tss_t), FRAME_ATOMIC);
        if (!tss_p)
            panic("Cannot allocate TSS.");
    }
 
//  tss_initialize(tss_p);
   
    gdt_p[TSS_DES].access = AR_PRESENT | AR_TSS | DPL_KERNEL;
    gdt_p[TSS_DES].special = 1;
    gdt_p[TSS_DES].granularity = 0;
   
    gdt_setbase(&gdt_p[TSS_DES], (uintptr_t) tss_p);
    gdt_setlimit(&gdt_p[TSS_DES], TSS_BASIC_SIZE - 1);
 
    /*
     * As of this moment, the current CPU has its own GDT pointing
     * to its own TSS. We just need to load the TR register.
     */
//  tr_load(selector(TSS_DES));
   
    clean_IOPL_NT_flags();    /* Disable I/O on nonprivileged levels and clear NT flag. */
    clean_AM_flag();          /* Disable alignment check */
}
 
void set_tls_desc(uintptr_t tls)
{
    ptr_16_32_t cpugdtr;
    descriptor_t *gdt_p;
 
    gdtr_store(&cpugdtr);
    gdt_p = (descriptor_t *) cpugdtr.base;
    gdt_setbase(&gdt_p[TLS_DES], tls);
    /* Reload gdt register to update GS in CPU */
    gdtr_load(&cpugdtr);
}
 
/** @}
 */
 

Rev 3104	Rev 3790
1	/*	1	/*
2	* Copyright (c) 2006 Martin Decky	2	* Copyright (c) 2006 Martin Decky
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	/** @addtogroup ia32xen	29	/** @addtogroup ia32xen
30	* @{	30	* @{
31	*/	31	*/
32	/** @file	32	/** @file
33	*/	33	*/
34		34
35	#include <arch/pm.h>	35	#include <arch/pm.h>
36	#include <config.h>	36	#include <config.h>
37	#include <arch/types.h>	37	#include <arch/types.h>
38	#include <arch/interrupt.h>	38	#include <arch/interrupt.h>
39	#include <arch/asm.h>	39	#include <arch/asm.h>
40	#include <arch/context.h>	40	#include <arch/context.h>
41	#include <panic.h>	41	#include <panic.h>
42	#include <arch/mm/page.h>	42	#include <arch/mm/page.h>
43	#include <mm/slab.h>	43	#include <mm/slab.h>
44	#include <memstr.h>	44	#include <memstr.h>
45	#include <interrupt.h>	45	#include <interrupt.h>
46		46
47	/*	47	/*
48	* Early ia32xen configuration functions and data structures.	48	* Early ia32xen configuration functions and data structures.
49	*/	49	*/
50		50
51	/*	51	/*
52	* We have no use for segmentation so we set up flat mode. In this	52	* We have no use for segmentation so we set up flat mode. In this
53	* mode, we use, for each privilege level, two segments spanning the	53	* mode, we use, for each privilege level, two segments spanning the
54	* whole memory. One is for code and one is for data.	54	* whole memory. One is for code and one is for data.
55	*	55	*
56	* One is for GS register which holds pointer to the TLS thread	56	* One is for GS register which holds pointer to the TLS thread
57	* structure in it's base.	57	* structure in it's base.
58	*/	58	*/
59	descriptor_t gdt[GDT_ITEMS] = {	59	descriptor_t gdt[GDT_ITEMS] = {
60	/* NULL descriptor */	60	/* NULL descriptor */
61	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },	61	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
62	/* KTEXT descriptor */	62	/* KTEXT descriptor */
63	{ 0xffff, 0, 0, AR_PRESENT \| AR_CODE \| DPL_KERNEL, 0xf, 0, 0, 1, 1, 0 },	63	{ 0xffff, 0, 0, AR_PRESENT \| AR_CODE \| DPL_KERNEL, 0xf, 0, 0, 1, 1, 0 },
64	/* KDATA descriptor */	64	/* KDATA descriptor */
65	{ 0xffff, 0, 0, AR_PRESENT \| AR_DATA \| AR_WRITABLE \| DPL_KERNEL, 0xf, 0, 0, 1, 1, 0 },	65	{ 0xffff, 0, 0, AR_PRESENT \| AR_DATA \| AR_WRITABLE \| DPL_KERNEL, 0xf, 0, 0, 1, 1, 0 },
66	/* UTEXT descriptor */	66	/* UTEXT descriptor */
67	{ 0xffff, 0, 0, AR_PRESENT \| AR_CODE \| DPL_USER, 0xf, 0, 0, 1, 1, 0 },	67	{ 0xffff, 0, 0, AR_PRESENT \| AR_CODE \| DPL_USER, 0xf, 0, 0, 1, 1, 0 },
68	/* UDATA descriptor */	68	/* UDATA descriptor */
69	{ 0xffff, 0, 0, AR_PRESENT \| AR_DATA \| AR_WRITABLE \| DPL_USER, 0xf, 0, 0, 1, 1, 0 },	69	{ 0xffff, 0, 0, AR_PRESENT \| AR_DATA \| AR_WRITABLE \| DPL_USER, 0xf, 0, 0, 1, 1, 0 },
70	/* TSS descriptor - set up will be completed later */	70	/* TSS descriptor - set up will be completed later */
71	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },	71	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
72	/* TLS descriptor */	72	/* TLS descriptor */
73	{ 0xffff, 0, 0, AR_PRESENT \| AR_DATA \| AR_WRITABLE \| DPL_USER, 0xf, 0, 0, 1, 1, 0 },	73	{ 0xffff, 0, 0, AR_PRESENT \| AR_DATA \| AR_WRITABLE \| DPL_USER, 0xf, 0, 0, 1, 1, 0 },
74	};	74	};
75		75
76	static trap_info_t traps[IDT_ITEMS + 1];	76	static trap_info_t traps[IDT_ITEMS + 1];
77		77
78	static tss_t tss;	78	static tss_t tss;
79		79
80	tss_t *tss_p = NULL;	80	tss_t *tss_p = NULL;
81		81
82	/* gdtr is changed by kmp before next CPU is initialized */	82	/* gdtr is changed by kmp before next CPU is initialized */
83	ptr_16_32_t bootstrap_gdtr = { .limit = sizeof(gdt), .base = KA2PA((uintptr_t) gdt) };	83	ptr_16_32_t bootstrap_gdtr = { .limit = sizeof(gdt), .base = KA2PA((uintptr_t) gdt) };
84	ptr_16_32_t gdtr = { .limit = sizeof(gdt), .base = (uintptr_t) gdt };	84	ptr_16_32_t gdtr = { .limit = sizeof(gdt), .base = (uintptr_t) gdt };
85		85
86	void gdt_setbase(descriptor_t *d, uintptr_t base)	86	void gdt_setbase(descriptor_t *d, uintptr_t base)
87	{	87	{
88	d->base_0_15 = base & 0xffff;	88	d->base_0_15 = base & 0xffff;
89	d->base_16_23 = ((base) >> 16) & 0xff;	89	d->base_16_23 = ((base) >> 16) & 0xff;
90	d->base_24_31 = ((base) >> 24) & 0xff;	90	d->base_24_31 = ((base) >> 24) & 0xff;
91	}	91	}
92		92
93	void gdt_setlimit(descriptor_t *d, uint32_t limit)	93	void gdt_setlimit(descriptor_t *d, uint32_t limit)
94	{	94	{
95	d->limit_0_15 = limit & 0xffff;	95	d->limit_0_15 = limit & 0xffff;
96	d->limit_16_19 = (limit >> 16) & 0xf;	96	d->limit_16_19 = (limit >> 16) & 0xf;
97	}	97	}
98		98
99	void tss_initialize(tss_t *t)	99	void tss_initialize(tss_t *t)
100	{	100	{
101	memsetb(t, sizeof(struct tss), 0);	101	memsetb(t, sizeof(struct tss), 0);
102	}	102	}
103		103
104	static void trap(void)	104	static void trap(void)
105	{	105	{
106	}	106	}
107		107
108	void traps_init(void)	108	void traps_init(void)
109	{	109	{
110	index_t i;	110	index_t i;
111		111
112	for (i = 0; i < IDT_ITEMS; i++) {	112	for (i = 0; i < IDT_ITEMS; i++) {
113	traps[i].vector = i;	113	traps[i].vector = i;
114		114
115	if (i == VECTOR_SYSCALL)	115	if (i == VECTOR_SYSCALL)
116	traps[i].flags = 3;	116	traps[i].flags = 3;
117	else	117	else
118	traps[i].flags = 0;	118	traps[i].flags = 0;
119		119
120	traps[i].cs = XEN_CS;	120	traps[i].cs = XEN_CS;
121	traps[i].address = trap;	121	traps[i].address = trap;
122	}	122	}
123	traps[IDT_ITEMS].vector = 0;	123	traps[IDT_ITEMS].vector = 0;
124	traps[IDT_ITEMS].flags = 0;	124	traps[IDT_ITEMS].flags = 0;
125	traps[IDT_ITEMS].cs = 0;	125	traps[IDT_ITEMS].cs = 0;
126	traps[IDT_ITEMS].address = NULL;	126	traps[IDT_ITEMS].address = NULL;
127	}	127	}
128		128
129		129
130	/* Clean IOPL(12,13) and NT(14) flags in EFLAGS register */	130	/* Clean IOPL(12,13) and NT(14) flags in EFLAGS register */
131	static void clean_IOPL_NT_flags(void)	131	static void clean_IOPL_NT_flags(void)
132	{	132	{
133	// asm volatile (	133	// asm volatile (
134	// "pushfl\n"	134	// "pushfl\n"
135	// "pop %%eax\n"	135	// "pop %%eax\n"
136	// "and $0xffff8fff, %%eax\n"	136	// "and $0xffff8fff, %%eax\n"
137	// "push %%eax\n"	137	// "push %%eax\n"
138	// "popfl\n"	138	// "popfl\n"
139	// : : : "eax"	139	// : : : "eax"
140	// );	140	// );
141	}	141	}
142		142
143	/* Clean AM(18) flag in CR0 register */	143	/* Clean AM(18) flag in CR0 register */
144	static void clean_AM_flag(void)	144	static void clean_AM_flag(void)
145	{	145	{
146	// asm volatile (	146	// asm volatile (
147	// "mov %%cr0, %%eax\n"	147	// "mov %%cr0, %%eax\n"
148	// "and $0xfffbffff, %%eax\n"	148	// "and $0xfffbffff, %%eax\n"
149	// "mov %%eax, %%cr0\n"	149	// "mov %%eax, %%cr0\n"
150	// : : : "eax"	150	// : : : "eax"
151	// );	151	// );
152	}	152	}
153		153
154	void pm_init(void)	154	void pm_init(void)
155	{	155	{
156	descriptor_t gdt_p = (descriptor_t ) gdtr.base;	156	descriptor_t gdt_p = (descriptor_t ) gdtr.base;
157		157
158	// gdtr_load(&gdtr);	158	// gdtr_load(&gdtr);
159		159
160	if (config.cpu_active == 1) {	160	if (config.cpu_active == 1) {
161	traps_init();	161	traps_init();
162	xen_set_trap_table(traps);	162	xen_set_trap_table(traps);
163	/*	163	/*
164	* NOTE: bootstrap CPU has statically allocated TSS, because	164	* NOTE: bootstrap CPU has statically allocated TSS, because
165	* the heap hasn't been initialized so far.	165	* the heap hasn't been initialized so far.
166	*/	166	*/
167	tss_p = &tss;	167	tss_p = &tss;
168	} else {	168	} else {
169	tss_p = (tss_t *) malloc(sizeof(tss_t), FRAME_ATOMIC);	169	tss_p = (tss_t *) malloc(sizeof(tss_t), FRAME_ATOMIC);
170	if (!tss_p)	170	if (!tss_p)
171	panic("could not allocate TSS\n");	171	panic("Cannot allocate TSS.");
172	}	172	}
173		173
174	// tss_initialize(tss_p);	174	// tss_initialize(tss_p);
175		175
176	gdt_p[TSS_DES].access = AR_PRESENT \| AR_TSS \| DPL_KERNEL;	176	gdt_p[TSS_DES].access = AR_PRESENT \| AR_TSS \| DPL_KERNEL;
177	gdt_p[TSS_DES].special = 1;	177	gdt_p[TSS_DES].special = 1;
178	gdt_p[TSS_DES].granularity = 0;	178	gdt_p[TSS_DES].granularity = 0;
179		179
180	gdt_setbase(&gdt_p[TSS_DES], (uintptr_t) tss_p);	180	gdt_setbase(&gdt_p[TSS_DES], (uintptr_t) tss_p);
181	gdt_setlimit(&gdt_p[TSS_DES], TSS_BASIC_SIZE - 1);	181	gdt_setlimit(&gdt_p[TSS_DES], TSS_BASIC_SIZE - 1);
182		182
183	/*	183	/*
184	* As of this moment, the current CPU has its own GDT pointing	184	* As of this moment, the current CPU has its own GDT pointing
185	* to its own TSS. We just need to load the TR register.	185	* to its own TSS. We just need to load the TR register.
186	*/	186	*/
187	// tr_load(selector(TSS_DES));	187	// tr_load(selector(TSS_DES));
188		188
189	clean_IOPL_NT_flags(); /* Disable I/O on nonprivileged levels and clear NT flag. */	189	clean_IOPL_NT_flags(); /* Disable I/O on nonprivileged levels and clear NT flag. */
190	clean_AM_flag(); /* Disable alignment check */	190	clean_AM_flag(); /* Disable alignment check */
191	}	191	}
192		192
193	void set_tls_desc(uintptr_t tls)	193	void set_tls_desc(uintptr_t tls)
194	{	194	{
195	ptr_16_32_t cpugdtr;	195	ptr_16_32_t cpugdtr;
196	descriptor_t *gdt_p;	196	descriptor_t *gdt_p;
197		197
198	gdtr_store(&cpugdtr);	198	gdtr_store(&cpugdtr);
199	gdt_p = (descriptor_t *) cpugdtr.base;	199	gdt_p = (descriptor_t *) cpugdtr.base;
200	gdt_setbase(&gdt_p[TLS_DES], tls);	200	gdt_setbase(&gdt_p[TLS_DES], tls);
201	/* Reload gdt register to update GS in CPU */	201	/* Reload gdt register to update GS in CPU */
202	gdtr_load(&cpugdtr);	202	gdtr_load(&cpugdtr);
203	}	203	}
204		204
205	/** @}	205	/** @}
206	*/	206	*/
207		207

Subversion Repositories HelenOS

(root)/trunk/kernel/arch/ia32xen/src/pm.c – Rev 3104 → 3790