WebSVN – HelenOS – Diff – /trunk/kernel/arch/ia32xen/include/mm/page.h


/*
 * Copyright (c) 2006 Martin Decky
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup ia32xen_mm 
 * @{
 */
/** @file
 */
 
#ifndef KERN_ia32xen_PAGE_H_
#define KERN_ia32xen_PAGE_H_
 
#include <arch/mm/frame.h>
 
#define PAGE_WIDTH  FRAME_WIDTH
#define PAGE_SIZE   FRAME_SIZE
 
#define PAGE_COLOR_BITS 0           /* dummy */
 
#ifdef KERNEL
 
#ifndef __ASM__
#   define KA2PA(x) (((uintptr_t) (x)) - 0x80000000)
#   define PA2KA(x) (((uintptr_t) (x)) + 0x80000000)
#else
#   define KA2PA(x) ((x) - 0x80000000)
#   define PA2KA(x) ((x) + 0x80000000)
#endif
 
/*
 * Implementation of generic 4-level page table interface.
 * IA-32 has 2-level page tables, so PTL1 and PTL2 are left out.
 */
#define PTL0_ENTRIES_ARCH   1024
#define PTL1_ENTRIES_ARCH   0
#define PTL2_ENTRIES_ARCH   0
#define PTL3_ENTRIES_ARCH   1024
 
#define PTL0_SIZE_ARCH       ONE_FRAME
#define PTL1_SIZE_ARCH       0
#define PTL2_SIZE_ARCH       0
#define PTL3_SIZE_ARCH       ONE_FRAME
 
#define PTL0_INDEX_ARCH(vaddr)  (((vaddr) >> 22) & 0x3ff)
#define PTL1_INDEX_ARCH(vaddr)  0
#define PTL2_INDEX_ARCH(vaddr)  0
#define PTL3_INDEX_ARCH(vaddr)  (((vaddr) >> 12) & 0x3ff)
 
#define GET_PTL1_ADDRESS_ARCH(ptl0, i)      ((pte_t *) MA2PA((((pte_t *) (ptl0))[(i)].frame_address) << 12))
#define GET_PTL2_ADDRESS_ARCH(ptl1, i)      (ptl1)
#define GET_PTL3_ADDRESS_ARCH(ptl2, i)      (ptl2)
#define GET_FRAME_ADDRESS_ARCH(ptl3, i)     ((uintptr_t) MA2PA((((pte_t *) (ptl3))[(i)].frame_address) << 12))
 
#define SET_PTL0_ADDRESS_ARCH(ptl0) { \
    mmuext_op_t mmu_ext; \
    \
    mmu_ext.cmd = MMUEXT_NEW_BASEPTR; \
    mmu_ext.mfn = ADDR2PFN(PA2MA(ptl0)); \
    ASSERT(xen_mmuext_op(&mmu_ext, 1, NULL, DOMID_SELF) == 0); \
}
 
#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) { \
    mmuext_op_t mmu_ext; \
    \
    mmu_ext.cmd = MMUEXT_PIN_L1_TABLE; \
    mmu_ext.mfn = ADDR2PFN(PA2MA(a)); \
    ASSERT(xen_mmuext_op(&mmu_ext, 1, NULL, DOMID_SELF) == 0); \
    \
    mmu_update_t update; \
    \
    update.ptr = PA2MA(KA2PA(&((pte_t *) (ptl0))[(i)])); \
    update.val = PA2MA(a); \
    ASSERT(xen_mmu_update(&update, 1, NULL, DOMID_SELF) == 0); \
}
 
#define SET_PTL2_ADDRESS_ARCH(ptl1, i, a)
#define SET_PTL3_ADDRESS_ARCH(ptl2, i, a)
#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) { \
    mmu_update_t update; \
    \
    update.ptr = PA2MA(KA2PA(&((pte_t *) (ptl3))[(i)])); \
    update.val = PA2MA(a); \
    ASSERT(xen_mmu_update(&update, 1, NULL, DOMID_SELF) == 0); \
}
 
#define GET_PTL1_FLAGS_ARCH(ptl0, i)        get_pt_flags((pte_t *) (ptl0), (index_t)(i))
#define GET_PTL2_FLAGS_ARCH(ptl1, i)        PAGE_PRESENT
#define GET_PTL3_FLAGS_ARCH(ptl2, i)        PAGE_PRESENT
#define GET_FRAME_FLAGS_ARCH(ptl3, i)       get_pt_flags((pte_t *) (ptl3), (index_t)(i))
 
#define SET_PTL1_FLAGS_ARCH(ptl0, i, x)     set_pt_flags((pte_t *) (ptl0), (index_t)(i), (x))
#define SET_PTL2_FLAGS_ARCH(ptl1, i, x)
#define SET_PTL3_FLAGS_ARCH(ptl2, i, x)
#define SET_FRAME_FLAGS_ARCH(ptl3, i, x)        set_pt_flags((pte_t *) (ptl3), (index_t)(i), (x))
 
#define PTE_VALID_ARCH(p)           (*((uint32_t *) (p)) != 0)
#define PTE_PRESENT_ARCH(p)         ((p)->present != 0)
#define PTE_GET_FRAME_ARCH(p)           ((p)->frame_address << FRAME_WIDTH)
#define PTE_WRITABLE_ARCH(p)            ((p)->writeable != 0)
#define PTE_EXECUTABLE_ARCH(p)          1
 
#ifndef __ASM__
 
#include <mm/mm.h>
#include <arch/hypercall.h>
#include <arch/interrupt.h>
 
/* Page fault error codes. */
 
/** When bit on this position is 0, the page fault was caused by a not-present page. */
#define PFERR_CODE_P        (1 << 0)
 
/** When bit on this position is 1, the page fault was caused by a write. */
#define PFERR_CODE_RW       (1 << 1)
 
/** When bit on this position is 1, the page fault was caused in user mode. */
#define PFERR_CODE_US       (1 << 2)
 
/** When bit on this position is 1, a reserved bit was set in page directory. */
#define PFERR_CODE_RSVD     (1 << 3)
 
typedef struct {
    uint64_t ptr;      /**< Machine address of PTE */
    union {            /**< New contents of PTE */
        uint64_t val;
        pte_t pte;
    };
} mmu_update_t;
 
typedef struct {
    unsigned int cmd;
    union {
        unsigned long mfn;
        unsigned long linear_addr;
    };
    union {
        unsigned int nr_ents;
        void *vcpumask;
    };
} mmuext_op_t;
 
static inline int xen_update_va_mapping(const void *va, const pte_t pte, const unsigned int flags)
{
    return hypercall4(XEN_UPDATE_VA_MAPPING, va, pte, 0, flags);
}
 
static inline int xen_mmu_update(const mmu_update_t *req, const unsigned int count, unsigned int *success_count, domid_t domid)
{
    return hypercall4(XEN_MMU_UPDATE, req, count, success_count, domid);
}
 
static inline int xen_mmuext_op(const mmuext_op_t *op, const unsigned int count, unsigned int *success_count, domid_t domid)
{
    return hypercall4(XEN_MMUEXT_OP, op, count, success_count, domid);
}
 
static inline int get_pt_flags(pte_t *pt, index_t i)
{
    pte_t *p = &pt[i];
   
    return (
        (!p->page_cache_disable)<<PAGE_CACHEABLE_SHIFT |
        (!p->present)<<PAGE_PRESENT_SHIFT |
        p->uaccessible<<PAGE_USER_SHIFT |
        1<<PAGE_READ_SHIFT |
        p->writeable<<PAGE_WRITE_SHIFT |
        1<<PAGE_EXEC_SHIFT |
        p->global<<PAGE_GLOBAL_SHIFT
    );
}
 
static inline void set_pt_flags(pte_t *pt, index_t i, int flags)
{
    pte_t p = pt[i];
   
    p.page_cache_disable = !(flags & PAGE_CACHEABLE);
    p.present = !(flags & PAGE_NOT_PRESENT);
    p.uaccessible = (flags & PAGE_USER) != 0;
    p.writeable = (flags & PAGE_WRITE) != 0;
    p.global = (flags & PAGE_GLOBAL) != 0;
   
    /*
     * Ensure that there is at least one bit set even if the present bit is cleared.
     */
    p.soft_valid = true;
   
    mmu_update_t update;
   
    update.ptr = PA2MA(KA2PA(&(pt[i])));
    update.pte = p;
    xen_mmu_update(&update, 1, NULL, DOMID_SELF);
}
 
extern void page_arch_init(void);
extern void page_fault(int n, istate_t *istate);
 
#endif /* __ASM__ */
 
#endif /* KERNEL */
 
#endif
 
/** @}
 */
 

Subversion Repositories HelenOS

(root)/trunk/kernel/arch/ia32xen/include/mm/page.h – Rev 2089 → 2465

Rev 2089		Rev 2465
1	/*	1	/*
2	* Copyright (c) 2006 Martin Decky	2	* Copyright (c) 2006 Martin Decky
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	/** @addtogroup ia32xen_mm	29	/** @addtogroup ia32xen_mm
30	* @{	30	* @{
31	*/	31	*/
32	/** @file	32	/** @file
33	*/	33	*/
34		34
35	#ifndef KERN_ia32xen_PAGE_H_	35	#ifndef KERN_ia32xen_PAGE_H_
36	#define KERN_ia32xen_PAGE_H_	36	#define KERN_ia32xen_PAGE_H_
37		37
38	#include <arch/mm/frame.h>	38	#include <arch/mm/frame.h>
39		39
40	#define PAGE_WIDTH FRAME_WIDTH	40	#define PAGE_WIDTH FRAME_WIDTH
41	#define PAGE_SIZE FRAME_SIZE	41	#define PAGE_SIZE FRAME_SIZE
42		42
43	#define PAGE_COLOR_BITS 0 /* dummy */	43	#define PAGE_COLOR_BITS 0 /* dummy */
44		44
45	#ifdef KERNEL	45	#ifdef KERNEL
46		46
47	#ifndef __ASM__	47	#ifndef __ASM__
48	# define KA2PA(x) (((uintptr_t) (x)) - 0x80000000)	48	# define KA2PA(x) (((uintptr_t) (x)) - 0x80000000)
49	# define PA2KA(x) (((uintptr_t) (x)) + 0x80000000)	49	# define PA2KA(x) (((uintptr_t) (x)) + 0x80000000)
50	#else	50	#else
51	# define KA2PA(x) ((x) - 0x80000000)	51	# define KA2PA(x) ((x) - 0x80000000)
52	# define PA2KA(x) ((x) + 0x80000000)	52	# define PA2KA(x) ((x) + 0x80000000)
53	#endif	53	#endif
54		54
55	/*	55	/*
56	* Implementation of generic 4-level page table interface.	56	* Implementation of generic 4-level page table interface.
57	* IA-32 has 2-level page tables, so PTL1 and PTL2 are left out.	57	* IA-32 has 2-level page tables, so PTL1 and PTL2 are left out.
58	*/	58	*/
59	#define PTL0_ENTRIES_ARCH 1024	59	#define PTL0_ENTRIES_ARCH 1024
60	#define PTL1_ENTRIES_ARCH 0	60	#define PTL1_ENTRIES_ARCH 0
61	#define PTL2_ENTRIES_ARCH 0	61	#define PTL2_ENTRIES_ARCH 0
62	#define PTL3_ENTRIES_ARCH 1024	62	#define PTL3_ENTRIES_ARCH 1024
63		63
-		64	#define PTL0_SIZE_ARCH ONE_FRAME
-		65	#define PTL1_SIZE_ARCH 0
-		66	#define PTL2_SIZE_ARCH 0
-		67	#define PTL3_SIZE_ARCH ONE_FRAME
-		68
64	#define PTL0_INDEX_ARCH(vaddr) (((vaddr) >> 22) & 0x3ff)	69	#define PTL0_INDEX_ARCH(vaddr) (((vaddr) >> 22) & 0x3ff)
65	#define PTL1_INDEX_ARCH(vaddr) 0	70	#define PTL1_INDEX_ARCH(vaddr) 0
66	#define PTL2_INDEX_ARCH(vaddr) 0	71	#define PTL2_INDEX_ARCH(vaddr) 0
67	#define PTL3_INDEX_ARCH(vaddr) (((vaddr) >> 12) & 0x3ff)	72	#define PTL3_INDEX_ARCH(vaddr) (((vaddr) >> 12) & 0x3ff)
68		73
69	#define GET_PTL1_ADDRESS_ARCH(ptl0, i) ((pte_t ) MA2PA((((pte_t ) (ptl0))[(i)].frame_address) << 12))	74	#define GET_PTL1_ADDRESS_ARCH(ptl0, i) ((pte_t ) MA2PA((((pte_t ) (ptl0))[(i)].frame_address) << 12))
70	#define GET_PTL2_ADDRESS_ARCH(ptl1, i) (ptl1)	75	#define GET_PTL2_ADDRESS_ARCH(ptl1, i) (ptl1)
71	#define GET_PTL3_ADDRESS_ARCH(ptl2, i) (ptl2)	76	#define GET_PTL3_ADDRESS_ARCH(ptl2, i) (ptl2)
72	#define GET_FRAME_ADDRESS_ARCH(ptl3, i) ((uintptr_t) MA2PA((((pte_t *) (ptl3))[(i)].frame_address) << 12))	77	#define GET_FRAME_ADDRESS_ARCH(ptl3, i) ((uintptr_t) MA2PA((((pte_t *) (ptl3))[(i)].frame_address) << 12))
73		78
74	#define SET_PTL0_ADDRESS_ARCH(ptl0) { \	79	#define SET_PTL0_ADDRESS_ARCH(ptl0) { \
75	mmuext_op_t mmu_ext; \	80	mmuext_op_t mmu_ext; \
76	\	81	\
77	mmu_ext.cmd = MMUEXT_NEW_BASEPTR; \	82	mmu_ext.cmd = MMUEXT_NEW_BASEPTR; \
78	mmu_ext.mfn = ADDR2PFN(PA2MA(ptl0)); \	83	mmu_ext.mfn = ADDR2PFN(PA2MA(ptl0)); \
79	ASSERT(xen_mmuext_op(&mmu_ext, 1, NULL, DOMID_SELF) == 0); \	84	ASSERT(xen_mmuext_op(&mmu_ext, 1, NULL, DOMID_SELF) == 0); \
80	}	85	}
81		86
82	#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) { \	87	#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) { \
83	mmuext_op_t mmu_ext; \	88	mmuext_op_t mmu_ext; \
84	\	89	\
85	mmu_ext.cmd = MMUEXT_PIN_L1_TABLE; \	90	mmu_ext.cmd = MMUEXT_PIN_L1_TABLE; \
86	mmu_ext.mfn = ADDR2PFN(PA2MA(a)); \	91	mmu_ext.mfn = ADDR2PFN(PA2MA(a)); \
87	ASSERT(xen_mmuext_op(&mmu_ext, 1, NULL, DOMID_SELF) == 0); \	92	ASSERT(xen_mmuext_op(&mmu_ext, 1, NULL, DOMID_SELF) == 0); \
88	\	93	\
89	mmu_update_t update; \	94	mmu_update_t update; \
90	\	95	\
91	update.ptr = PA2MA(KA2PA(&((pte_t *) (ptl0))[(i)])); \	96	update.ptr = PA2MA(KA2PA(&((pte_t *) (ptl0))[(i)])); \
92	update.val = PA2MA(a); \	97	update.val = PA2MA(a); \
93	ASSERT(xen_mmu_update(&update, 1, NULL, DOMID_SELF) == 0); \	98	ASSERT(xen_mmu_update(&update, 1, NULL, DOMID_SELF) == 0); \
94	}	99	}
95		100
96	#define SET_PTL2_ADDRESS_ARCH(ptl1, i, a)	101	#define SET_PTL2_ADDRESS_ARCH(ptl1, i, a)
97	#define SET_PTL3_ADDRESS_ARCH(ptl2, i, a)	102	#define SET_PTL3_ADDRESS_ARCH(ptl2, i, a)
98	#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) { \	103	#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) { \
99	mmu_update_t update; \	104	mmu_update_t update; \
100	\	105	\
101	update.ptr = PA2MA(KA2PA(&((pte_t *) (ptl3))[(i)])); \	106	update.ptr = PA2MA(KA2PA(&((pte_t *) (ptl3))[(i)])); \
102	update.val = PA2MA(a); \	107	update.val = PA2MA(a); \
103	ASSERT(xen_mmu_update(&update, 1, NULL, DOMID_SELF) == 0); \	108	ASSERT(xen_mmu_update(&update, 1, NULL, DOMID_SELF) == 0); \
104	}	109	}
105		110
106	#define GET_PTL1_FLAGS_ARCH(ptl0, i) get_pt_flags((pte_t *) (ptl0), (index_t)(i))	111	#define GET_PTL1_FLAGS_ARCH(ptl0, i) get_pt_flags((pte_t *) (ptl0), (index_t)(i))
107	#define GET_PTL2_FLAGS_ARCH(ptl1, i) PAGE_PRESENT	112	#define GET_PTL2_FLAGS_ARCH(ptl1, i) PAGE_PRESENT
108	#define GET_PTL3_FLAGS_ARCH(ptl2, i) PAGE_PRESENT	113	#define GET_PTL3_FLAGS_ARCH(ptl2, i) PAGE_PRESENT
109	#define GET_FRAME_FLAGS_ARCH(ptl3, i) get_pt_flags((pte_t *) (ptl3), (index_t)(i))	114	#define GET_FRAME_FLAGS_ARCH(ptl3, i) get_pt_flags((pte_t *) (ptl3), (index_t)(i))
110		115
111	#define SET_PTL1_FLAGS_ARCH(ptl0, i, x) set_pt_flags((pte_t *) (ptl0), (index_t)(i), (x))	116	#define SET_PTL1_FLAGS_ARCH(ptl0, i, x) set_pt_flags((pte_t *) (ptl0), (index_t)(i), (x))
112	#define SET_PTL2_FLAGS_ARCH(ptl1, i, x)	117	#define SET_PTL2_FLAGS_ARCH(ptl1, i, x)
113	#define SET_PTL3_FLAGS_ARCH(ptl2, i, x)	118	#define SET_PTL3_FLAGS_ARCH(ptl2, i, x)
114	#define SET_FRAME_FLAGS_ARCH(ptl3, i, x) set_pt_flags((pte_t *) (ptl3), (index_t)(i), (x))	119	#define SET_FRAME_FLAGS_ARCH(ptl3, i, x) set_pt_flags((pte_t *) (ptl3), (index_t)(i), (x))
115		120
116	#define PTE_VALID_ARCH(p) (((uint32_t ) (p)) != 0)	121	#define PTE_VALID_ARCH(p) (((uint32_t ) (p)) != 0)
117	#define PTE_PRESENT_ARCH(p) ((p)->present != 0)	122	#define PTE_PRESENT_ARCH(p) ((p)->present != 0)
118	#define PTE_GET_FRAME_ARCH(p) ((p)->frame_address << FRAME_WIDTH)	123	#define PTE_GET_FRAME_ARCH(p) ((p)->frame_address << FRAME_WIDTH)
119	#define PTE_WRITABLE_ARCH(p) ((p)->writeable != 0)	124	#define PTE_WRITABLE_ARCH(p) ((p)->writeable != 0)
120	#define PTE_EXECUTABLE_ARCH(p) 1	125	#define PTE_EXECUTABLE_ARCH(p) 1
121		126
122	#ifndef __ASM__	127	#ifndef __ASM__
123		128
124	#include <mm/mm.h>	129	#include <mm/mm.h>
125	#include <arch/hypercall.h>	130	#include <arch/hypercall.h>
126	#include <arch/interrupt.h>	131	#include <arch/interrupt.h>
127		132
128	/* Page fault error codes. */	133	/* Page fault error codes. */
129		134
130	/** When bit on this position is 0, the page fault was caused by a not-present page. */	135	/** When bit on this position is 0, the page fault was caused by a not-present page. */
131	#define PFERR_CODE_P (1 << 0)	136	#define PFERR_CODE_P (1 << 0)
132		137
133	/** When bit on this position is 1, the page fault was caused by a write. */	138	/** When bit on this position is 1, the page fault was caused by a write. */
134	#define PFERR_CODE_RW (1 << 1)	139	#define PFERR_CODE_RW (1 << 1)
135		140
136	/** When bit on this position is 1, the page fault was caused in user mode. */	141	/** When bit on this position is 1, the page fault was caused in user mode. */
137	#define PFERR_CODE_US (1 << 2)	142	#define PFERR_CODE_US (1 << 2)
138		143
139	/** When bit on this position is 1, a reserved bit was set in page directory. */	144	/** When bit on this position is 1, a reserved bit was set in page directory. */
140	#define PFERR_CODE_RSVD (1 << 3)	145	#define PFERR_CODE_RSVD (1 << 3)
141		146
142	typedef struct {	147	typedef struct {
143	uint64_t ptr; /*< Machine address of PTE /	148	uint64_t ptr; /*< Machine address of PTE /
144	union { /*< New contents of PTE /	149	union { /*< New contents of PTE /
145	uint64_t val;	150	uint64_t val;
146	pte_t pte;	151	pte_t pte;
147	};	152	};
148	} mmu_update_t;	153	} mmu_update_t;
149		154
150	typedef struct {	155	typedef struct {
151	unsigned int cmd;	156	unsigned int cmd;
152	union {	157	union {
153	unsigned long mfn;	158	unsigned long mfn;
154	unsigned long linear_addr;	159	unsigned long linear_addr;
155	};	160	};
156	union {	161	union {
157	unsigned int nr_ents;	162	unsigned int nr_ents;
158	void *vcpumask;	163	void *vcpumask;
159	};	164	};
160	} mmuext_op_t;	165	} mmuext_op_t;
161		166
162	static inline int xen_update_va_mapping(const void *va, const pte_t pte, const unsigned int flags)	167	static inline int xen_update_va_mapping(const void *va, const pte_t pte, const unsigned int flags)
163	{	168	{
164	return hypercall4(XEN_UPDATE_VA_MAPPING, va, pte, 0, flags);	169	return hypercall4(XEN_UPDATE_VA_MAPPING, va, pte, 0, flags);
165	}	170	}
166		171
167	static inline int xen_mmu_update(const mmu_update_t req, const unsigned int count, unsigned int success_count, domid_t domid)	172	static inline int xen_mmu_update(const mmu_update_t req, const unsigned int count, unsigned int success_count, domid_t domid)
168	{	173	{
169	return hypercall4(XEN_MMU_UPDATE, req, count, success_count, domid);	174	return hypercall4(XEN_MMU_UPDATE, req, count, success_count, domid);
170	}	175	}
171		176
172	static inline int xen_mmuext_op(const mmuext_op_t op, const unsigned int count, unsigned int success_count, domid_t domid)	177	static inline int xen_mmuext_op(const mmuext_op_t op, const unsigned int count, unsigned int success_count, domid_t domid)
173	{	178	{
174	return hypercall4(XEN_MMUEXT_OP, op, count, success_count, domid);	179	return hypercall4(XEN_MMUEXT_OP, op, count, success_count, domid);
175	}	180	}
176		181
177	static inline int get_pt_flags(pte_t *pt, index_t i)	182	static inline int get_pt_flags(pte_t *pt, index_t i)
178	{	183	{
179	pte_t *p = &pt[i];	184	pte_t *p = &pt[i];
180		185
181	return (	186	return (
182	(!p->page_cache_disable)<<PAGE_CACHEABLE_SHIFT \|	187	(!p->page_cache_disable)<<PAGE_CACHEABLE_SHIFT \|
183	(!p->present)<<PAGE_PRESENT_SHIFT \|	188	(!p->present)<<PAGE_PRESENT_SHIFT \|
184	p->uaccessible<<PAGE_USER_SHIFT \|	189	p->uaccessible<<PAGE_USER_SHIFT \|
185	1<<PAGE_READ_SHIFT \|	190	1<<PAGE_READ_SHIFT \|
186	p->writeable<<PAGE_WRITE_SHIFT \|	191	p->writeable<<PAGE_WRITE_SHIFT \|
187	1<<PAGE_EXEC_SHIFT \|	192	1<<PAGE_EXEC_SHIFT \|
188	p->global<<PAGE_GLOBAL_SHIFT	193	p->global<<PAGE_GLOBAL_SHIFT
189	);	194	);
190	}	195	}
191		196
192	static inline void set_pt_flags(pte_t *pt, index_t i, int flags)	197	static inline void set_pt_flags(pte_t *pt, index_t i, int flags)
193	{	198	{
194	pte_t p = pt[i];	199	pte_t p = pt[i];
195		200
196	p.page_cache_disable = !(flags & PAGE_CACHEABLE);	201	p.page_cache_disable = !(flags & PAGE_CACHEABLE);
197	p.present = !(flags & PAGE_NOT_PRESENT);	202	p.present = !(flags & PAGE_NOT_PRESENT);
198	p.uaccessible = (flags & PAGE_USER) != 0;	203	p.uaccessible = (flags & PAGE_USER) != 0;
199	p.writeable = (flags & PAGE_WRITE) != 0;	204	p.writeable = (flags & PAGE_WRITE) != 0;
200	p.global = (flags & PAGE_GLOBAL) != 0;	205	p.global = (flags & PAGE_GLOBAL) != 0;
201		206
202	/*	207	/*
203	* Ensure that there is at least one bit set even if the present bit is cleared.	208	* Ensure that there is at least one bit set even if the present bit is cleared.
204	*/	209	*/
205	p.soft_valid = true;	210	p.soft_valid = true;
206		211
207	mmu_update_t update;	212	mmu_update_t update;
208		213
209	update.ptr = PA2MA(KA2PA(&(pt[i])));	214	update.ptr = PA2MA(KA2PA(&(pt[i])));
210	update.pte = p;	215	update.pte = p;
211	xen_mmu_update(&update, 1, NULL, DOMID_SELF);	216	xen_mmu_update(&update, 1, NULL, DOMID_SELF);
212	}	217	}
213		218
214	extern void page_arch_init(void);	219	extern void page_arch_init(void);
215	extern void page_fault(int n, istate_t *istate);	220	extern void page_fault(int n, istate_t *istate);
216		221
217	#endif /* __ASM__ */	222	#endif /* __ASM__ */
218		223
219	#endif /* KERNEL */	224	#endif /* KERNEL */
220		225
221	#endif	226	#endif
222		227
223	/** @}	228	/** @}
224	*/	229	*/
225		230