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Line 74... Line 74...
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#define SET_PTL0_ADDRESS_ARCH(ptl0) { \
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#define SET_PTL0_ADDRESS_ARCH(ptl0) { \
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    mmuext_op_t mmu_ext; \
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    mmuext_op_t mmu_ext; \
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    \
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    \
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    mmu_ext.cmd = MMUEXT_NEW_BASEPTR; \
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    mmu_ext.cmd = MMUEXT_NEW_BASEPTR; \
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    mmu_ext.mfn = ADDR2PFN(PA2MA(ptl0)); \
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    mmu_ext.mfn = ADDR2PFN(PA2MA(ptl0)); \
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    xen_mmuext_op(&mmu_ext, 1, NULL, DOMID_SELF); \
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    ASSERT(xen_mmuext_op(&mmu_ext, 1, NULL, DOMID_SELF) == 0); \
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}
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}
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#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) { \
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#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) { \
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    mmuext_op_t mmu_ext; \
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    \
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    mmu_ext.cmd = MMUEXT_PIN_L1_TABLE; \
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    mmu_ext.mfn = ADDR2PFN(PA2MA(a)); \
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    ASSERT(xen_mmuext_op(&mmu_ext, 1, NULL, DOMID_SELF) == 0); \
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    \
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    mmu_update_t update; \
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    mmu_update_t update; \
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    \
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    \
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    update.ptr = PA2MA(KA2PA(&((pte_t *) (ptl0))[(i)])); \
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    update.ptr = PA2MA(KA2PA(&((pte_t *) (ptl0))[(i)])); \
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    update.val = PA2MA(a) | 0x0003; \
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    update.val = PA2MA(a); \
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    xen_mmu_update(&update, 1, NULL, DOMID_SELF); \
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    ASSERT(xen_mmu_update(&update, 1, NULL, DOMID_SELF) == 0); \
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}
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}
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#define SET_PTL2_ADDRESS_ARCH(ptl1, i, a)
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#define SET_PTL2_ADDRESS_ARCH(ptl1, i, a)
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#define SET_PTL3_ADDRESS_ARCH(ptl2, i, a)
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#define SET_PTL3_ADDRESS_ARCH(ptl2, i, a)
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#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a)  (((pte_t *) (ptl3))[(i)].frame_address = PA2MA(a) >> 12)
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#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) { \
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    mmu_update_t update; \
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    \
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    update.ptr = PA2MA(KA2PA(&((pte_t *) (ptl3))[(i)])); \
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    update.val = PA2MA(a); \
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    ASSERT(xen_mmu_update(&update, 1, NULL, DOMID_SELF) == 0); \
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}
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#define GET_PTL1_FLAGS_ARCH(ptl0, i)        get_pt_flags((pte_t *) (ptl0), (index_t)(i))
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#define GET_PTL1_FLAGS_ARCH(ptl0, i)        get_pt_flags((pte_t *) (ptl0), (index_t)(i))
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#define GET_PTL2_FLAGS_ARCH(ptl1, i)        PAGE_PRESENT
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#define GET_PTL2_FLAGS_ARCH(ptl1, i)        PAGE_PRESENT
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#define GET_PTL3_FLAGS_ARCH(ptl2, i)        PAGE_PRESENT
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#define GET_PTL3_FLAGS_ARCH(ptl2, i)        PAGE_PRESENT
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#define GET_FRAME_FLAGS_ARCH(ptl3, i)       get_pt_flags((pte_t *) (ptl3), (index_t)(i))
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#define GET_FRAME_FLAGS_ARCH(ptl3, i)       get_pt_flags((pte_t *) (ptl3), (index_t)(i))
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    );
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    );
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}
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}
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static inline void set_pt_flags(pte_t *pt, index_t i, int flags)
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static inline void set_pt_flags(pte_t *pt, index_t i, int flags)
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{
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{
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    pte_t *p = &pt[i];
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    pte_t p = pt[i];
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    p->page_cache_disable = !(flags & PAGE_CACHEABLE);
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    p.page_cache_disable = !(flags & PAGE_CACHEABLE);
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    p->present = !(flags & PAGE_NOT_PRESENT);
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    p.present = !(flags & PAGE_NOT_PRESENT);
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    p->uaccessible = (flags & PAGE_USER) != 0;
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    p.uaccessible = (flags & PAGE_USER) != 0;
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    p->writeable = (flags & PAGE_WRITE) != 0;
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    p.writeable = (flags & PAGE_WRITE) != 0;
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    p->global = (flags & PAGE_GLOBAL) != 0;
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    p.global = (flags & PAGE_GLOBAL) != 0;
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    /*
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    /*
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     * Ensure that there is at least one bit set even if the present bit is cleared.
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     * Ensure that there is at least one bit set even if the present bit is cleared.
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     */
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     */
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    p->soft_valid = true;
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    p.soft_valid = true;
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    mmu_update_t update;
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    update.ptr = PA2MA(KA2PA(&(pt[i])));
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    update.pte = p;
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    xen_mmu_update(&update, 1, NULL, DOMID_SELF);
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}
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}
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extern void page_arch_init(void);
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extern void page_arch_init(void);
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extern void page_fault(int n, istate_t *istate);
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extern void page_fault(int n, istate_t *istate);
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