WebSVN – HelenOS – Diff – /trunk/kernel/arch/ia32xen/include/asm.h



#define cpu_sleep() ((void) 0)
 
#define GEN_READ_REG(reg) static inline unative_t read_ ##reg (void) \
    { \
    unative_t res; \
    asm volatile ("movl %%" #reg ", %0" : "=r" (res) ); \
    return res; \
    }
 
#define GEN_WRITE_REG(reg) static inline void write_ ##reg (unative_t regn) \
    { \
    asm volatile ("movl %0, %%" #reg : : "r" (regn)); \
    }
 
GEN_READ_REG(cr0);
GEN_READ_REG(cr2);
 

 * Output byte to port
 *
 * @param port Port to write to
 * @param val Value to write
 */
static inline void outb(uint16_t port, uint8_t val) { asm volatile ("outb %b0, %w1\n" : : "a" (val), "d" (port) ); }
 
/** Word to port
 *
 * Output word to port
 *
 * @param port Port to write to
 * @param val Value to write
 */
static inline void outw(uint16_t port, uint16_t val) { asm volatile ("outw %w0, %w1\n" : : "a" (val), "d" (port) ); }
 
/** Double word to port
 *
 * Output double word to port
 *
 * @param port Port to write to
 * @param val Value to write
 */
static inline void outl(uint16_t port, uint32_t val) { asm volatile ("outl %l0, %w1\n" : : "a" (val), "d" (port) ); }
 
/** Byte from port
 *
 * Get byte from port
 *
 * @param port Port to read from
 * @return Value read
 */
static inline uint8_t inb(uint16_t port) { uint8_t val; asm volatile ("inb %w1, %b0 \n" : "=a" (val) : "d" (port) ); return val; }
 
/** Word from port
 *
 * Get word from port
 *
 * @param port Port to read from
 * @return Value read
 */
static inline uint16_t inw(uint16_t port) { uint16_t val; asm volatile ("inw %w1, %w0 \n" : "=a" (val) : "d" (port) ); return val; }
 
/** Double word from port
 *
 * Get double word from port
 *
 * @param port Port to read from
 * @return Value read
 */
static inline uint32_t inl(uint16_t port) { uint32_t val; asm volatile ("inl %w1, %l0 \n" : "=a" (val) : "d" (port) ); return val; }
 
/** Enable interrupts.
 *
 * Enable interrupts and return previous
 * value of EFLAGS.

 */
static inline uintptr_t get_stack_base(void)
{
    uintptr_t v;
   
    asm volatile ("andl %%esp, %0\n" : "=r" (v) : "0" (~(STACK_SIZE-1)));
   
    return v;
}
 
/** Return current IP address */
static inline uintptr_t * get_ip()
{
    uintptr_t *ip;
 
    asm volatile (
        "mov %%eip, %0"
        : "=r" (ip)
        );
    return ip;
}

 *
 * @param addr Address on a page whose TLB entry is to be invalidated.
 */
static inline void invlpg(uintptr_t addr)
{
    asm volatile ("invlpg %0\n" :: "m" (*(unative_t *)addr));
}
 
/** Load GDTR register from memory.
 *
 * @param gdtr_reg Address of memory from where to load GDTR.
 */
static inline void gdtr_load(ptr_16_32_t *gdtr_reg)
{
    asm volatile ("lgdtl %0\n" : : "m" (*gdtr_reg));
}
 
/** Store GDTR register to memory.
 *
 * @param gdtr_reg Address of memory to where to load GDTR.
 */
static inline void gdtr_store(ptr_16_32_t *gdtr_reg)
{
    asm volatile ("sgdtl %0\n" : : "m" (*gdtr_reg));
}
 
/** Load TR from descriptor table.
 *
 * @param sel Selector specifying descriptor of TSS segment.
 */
static inline void tr_load(uint16_t sel)
{
    asm volatile ("ltr %0" : : "r" (sel));
}
 
#endif
 
/** @}

Rev 2071	Rev 2082
Line 57...	Line 57...
57	#define cpu_sleep() ((void) 0)	57	#define cpu_sleep() ((void) 0)
58		58
59	#define GEN_READ_REG(reg) static inline unative_t read_ ##reg (void) \	59	#define GEN_READ_REG(reg) static inline unative_t read_ ##reg (void) \
60	{ \	60	{ \
61	unative_t res; \	61	unative_t res; \
62	__asm__ volatile ("movl %%" #reg ", %0" : "=r" (res) ); \	62	asm volatile ("movl %%" #reg ", %0" : "=r" (res) ); \
63	return res; \	63	return res; \
64	}	64	}
65		65
66	#define GEN_WRITE_REG(reg) static inline void write_ ##reg (unative_t regn) \	66	#define GEN_WRITE_REG(reg) static inline void write_ ##reg (unative_t regn) \
67	{ \	67	{ \
68	__asm__ volatile ("movl %0, %%" #reg : : "r" (regn)); \	68	asm volatile ("movl %0, %%" #reg : : "r" (regn)); \
69	}	69	}
70		70
71	GEN_READ_REG(cr0);	71	GEN_READ_REG(cr0);
72	GEN_READ_REG(cr2);	72	GEN_READ_REG(cr2);
73		73
Line 90...	Line 90...
90	* Output byte to port	90	* Output byte to port
91	*	91	*
92	* @param port Port to write to	92	* @param port Port to write to
93	* @param val Value to write	93	* @param val Value to write
94	*/	94	*/
95	static inline void outb(uint16_t port, uint8_t val) { __asm__ volatile ("outb %b0, %w1\n" : : "a" (val), "d" (port) ); }	95	static inline void outb(uint16_t port, uint8_t val) { asm volatile ("outb %b0, %w1\n" : : "a" (val), "d" (port) ); }
96		96
97	/** Word to port	97	/** Word to port
98	*	98	*
99	* Output word to port	99	* Output word to port
100	*	100	*
101	* @param port Port to write to	101	* @param port Port to write to
102	* @param val Value to write	102	* @param val Value to write
103	*/	103	*/
104	static inline void outw(uint16_t port, uint16_t val) { __asm__ volatile ("outw %w0, %w1\n" : : "a" (val), "d" (port) ); }	104	static inline void outw(uint16_t port, uint16_t val) { asm volatile ("outw %w0, %w1\n" : : "a" (val), "d" (port) ); }
105		105
106	/** Double word to port	106	/** Double word to port
107	*	107	*
108	* Output double word to port	108	* Output double word to port
109	*	109	*
110	* @param port Port to write to	110	* @param port Port to write to
111	* @param val Value to write	111	* @param val Value to write
112	*/	112	*/
113	static inline void outl(uint16_t port, uint32_t val) { __asm__ volatile ("outl %l0, %w1\n" : : "a" (val), "d" (port) ); }	113	static inline void outl(uint16_t port, uint32_t val) { asm volatile ("outl %l0, %w1\n" : : "a" (val), "d" (port) ); }
114		114
115	/** Byte from port	115	/** Byte from port
116	*	116	*
117	* Get byte from port	117	* Get byte from port
118	*	118	*
119	* @param port Port to read from	119	* @param port Port to read from
120	* @return Value read	120	* @return Value read
121	*/	121	*/
122	static inline uint8_t inb(uint16_t port) { uint8_t val; __asm__ volatile ("inb %w1, %b0 \n" : "=a" (val) : "d" (port) ); return val; }	122	static inline uint8_t inb(uint16_t port) { uint8_t val; asm volatile ("inb %w1, %b0 \n" : "=a" (val) : "d" (port) ); return val; }
123		123
124	/** Word from port	124	/** Word from port
125	*	125	*
126	* Get word from port	126	* Get word from port
127	*	127	*
128	* @param port Port to read from	128	* @param port Port to read from
129	* @return Value read	129	* @return Value read
130	*/	130	*/
131	static inline uint16_t inw(uint16_t port) { uint16_t val; __asm__ volatile ("inw %w1, %w0 \n" : "=a" (val) : "d" (port) ); return val; }	131	static inline uint16_t inw(uint16_t port) { uint16_t val; asm volatile ("inw %w1, %w0 \n" : "=a" (val) : "d" (port) ); return val; }
132		132
133	/** Double word from port	133	/** Double word from port
134	*	134	*
135	* Get double word from port	135	* Get double word from port
136	*	136	*
137	* @param port Port to read from	137	* @param port Port to read from
138	* @return Value read	138	* @return Value read
139	*/	139	*/
140	static inline uint32_t inl(uint16_t port) { uint32_t val; __asm__ volatile ("inl %w1, %l0 \n" : "=a" (val) : "d" (port) ); return val; }	140	static inline uint32_t inl(uint16_t port) { uint32_t val; asm volatile ("inl %w1, %l0 \n" : "=a" (val) : "d" (port) ); return val; }
141		141
142	/** Enable interrupts.	142	/** Enable interrupts.
143	*	143	*
144	* Enable interrupts and return previous	144	* Enable interrupts and return previous
145	* value of EFLAGS.	145	* value of EFLAGS.
Line 211...	Line 211...
211	*/	211	*/
212	static inline uintptr_t get_stack_base(void)	212	static inline uintptr_t get_stack_base(void)
213	{	213	{
214	uintptr_t v;	214	uintptr_t v;
215		215
216	__asm__ volatile ("andl %%esp, %0\n" : "=r" (v) : "0" (~(STACK_SIZE-1)));	216	asm volatile ("andl %%esp, %0\n" : "=r" (v) : "0" (~(STACK_SIZE-1)));
217		217
218	return v;	218	return v;
219	}	219	}
220		220
221	/** Return current IP address */	221	/** Return current IP address */
222	static inline uintptr_t * get_ip()	222	static inline uintptr_t * get_ip()
223	{	223	{
224	uintptr_t *ip;	224	uintptr_t *ip;
225		225
226	__asm__ volatile (	226	asm volatile (
227	"mov %%eip, %0"	227	"mov %%eip, %0"
228	: "=r" (ip)	228	: "=r" (ip)
229	);	229	);
230	return ip;	230	return ip;
231	}	231	}
Line 234...	Line 234...
234	*	234	*
235	* @param addr Address on a page whose TLB entry is to be invalidated.	235	* @param addr Address on a page whose TLB entry is to be invalidated.
236	*/	236	*/
237	static inline void invlpg(uintptr_t addr)	237	static inline void invlpg(uintptr_t addr)
238	{	238	{
239	__asm__ volatile ("invlpg %0\n" :: "m" ((unative_t )addr));	239	asm volatile ("invlpg %0\n" :: "m" ((unative_t )addr));
240	}	240	}
241		241
242	/** Load GDTR register from memory.	242	/** Load GDTR register from memory.
243	*	243	*
244	* @param gdtr_reg Address of memory from where to load GDTR.	244	* @param gdtr_reg Address of memory from where to load GDTR.
245	*/	245	*/
246	static inline void gdtr_load(ptr_16_32_t *gdtr_reg)	246	static inline void gdtr_load(ptr_16_32_t *gdtr_reg)
247	{	247	{
248	__asm__ volatile ("lgdtl %0\n" : : "m" (*gdtr_reg));	248	asm volatile ("lgdtl %0\n" : : "m" (*gdtr_reg));
249	}	249	}
250		250
251	/** Store GDTR register to memory.	251	/** Store GDTR register to memory.
252	*	252	*
253	* @param gdtr_reg Address of memory to where to load GDTR.	253	* @param gdtr_reg Address of memory to where to load GDTR.
254	*/	254	*/
255	static inline void gdtr_store(ptr_16_32_t *gdtr_reg)	255	static inline void gdtr_store(ptr_16_32_t *gdtr_reg)
256	{	256	{
257	__asm__ volatile ("sgdtl %0\n" : : "m" (*gdtr_reg));	257	asm volatile ("sgdtl %0\n" : : "m" (*gdtr_reg));
258	}	258	}
259		259
260	/** Load TR from descriptor table.	260	/** Load TR from descriptor table.
261	*	261	*
262	* @param sel Selector specifying descriptor of TSS segment.	262	* @param sel Selector specifying descriptor of TSS segment.
263	*/	263	*/
264	static inline void tr_load(uint16_t sel)	264	static inline void tr_load(uint16_t sel)
265	{	265	{
266	__asm__ volatile ("ltr %0" : : "r" (sel));	266	asm volatile ("ltr %0" : : "r" (sel));
267	}	267	}
268		268
269	#endif	269	#endif
270		270
271	/** @}	271	/** @}

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(root)/trunk/kernel/arch/ia32xen/include/asm.h – Rev 2071 → 2082