WebSVN – HelenOS – Diff – /trunk/kernel/arch/ia32/src/smp/apic.c


/*
 * Copyright (c) 2001-2004 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup ia32   
 * @{
 */
/** @file
 */
 
#include <arch/types.h>
#include <arch/smp/apic.h>
#include <arch/smp/ap.h>
#include <arch/smp/mps.h>
#include <arch/boot/boot.h>
#include <mm/page.h>
#include <time/delay.h>
#include <interrupt.h>
#include <arch/interrupt.h>
#include <print.h>
#include <arch/asm.h>
#include <arch.h>
#include <ddi/irq.h>
#include <ddi/device.h>
 
#ifdef CONFIG_SMP
 
/*
 * Advanced Programmable Interrupt Controller for SMP systems.
 * Tested on:
 *  Bochs 2.0.2 - Bochs 2.2.6 with 2-8 CPUs
 *  Simics 2.0.28 - Simics 2.2.19 2-15 CPUs
 *  VMware Workstation 5.5 with 2 CPUs
 *  QEMU 0.8.0 with 2-15 CPUs
 *  ASUS P/I-P65UP5 + ASUS C-P55T2D REV. 1.41 with 2x 200Mhz Pentium CPUs
 *  ASUS PCH-DL with 2x 3000Mhz Pentium 4 Xeon (HT) CPUs
 *  MSI K7D Master-L with 2x 2100MHz Athlon MP CPUs
 */
 
/*
 * These variables either stay configured as initilalized, or are changed by
 * the MP configuration code.
 *
 * Pay special attention to the volatile keyword. Without it, gcc -O2 would
 * optimize the code too much and accesses to l_apic and io_apic, that must
 * always be 32-bit, would use byte oriented instructions.
 */
volatile uint32_t *l_apic = (uint32_t *) 0xfee00000;
volatile uint32_t *io_apic = (uint32_t *) 0xfec00000;
 
uint32_t apic_id_mask = 0;
static irq_t l_apic_timer_irq;
 
static int apic_poll_errors(void);
 
#ifdef LAPIC_VERBOSE
static char *delmod_str[] = {
    "Fixed",
    "Lowest Priority",
    "SMI",
    "Reserved",
    "NMI",
    "INIT",
    "STARTUP",
    "ExtInt"
};
 
static char *destmod_str[] = {
    "Physical",
    "Logical"
};
 
static char *trigmod_str[] = {
    "Edge",
    "Level"
};
 
static char *mask_str[] = {
    "Unmasked",
    "Masked"
};
 
static char *delivs_str[] = {
    "Idle",
    "Send Pending"
};
 
static char *tm_mode_str[] = {
    "One-shot",
    "Periodic"
};
 
static char *intpol_str[] = {
    "Polarity High",
    "Polarity Low"
};
#endif /* LAPIC_VERBOSE */
 
/** APIC spurious interrupt handler.
 *
 * @param n Interrupt vector.
 * @param istate Interrupted state.
 */
static void apic_spurious(int n, istate_t *istate)
{
#ifdef CONFIG_DEBUG
    printf("cpu%d: APIC spurious interrupt\n", CPU->id);
#endif
}
 
static irq_ownership_t l_apic_timer_claim(void)
{
    return IRQ_ACCEPT;
}
 
static void l_apic_timer_irq_handler(irq_t *irq, void *arg, ...)
{
    /*
     * Holding a spinlock could prevent clock() from preempting
     * the current thread. In this case, we don't need to hold the
     * irq->lock so we just unlock it and then lock it again.
     */
    spinlock_unlock(&irq->lock);
    clock();
    spinlock_lock(&irq->lock);
}
 
/** Initialize APIC on BSP. */
void apic_init(void)
{
    io_apic_id_t idreg;
    unsigned int i;
 
    exc_register(VECTOR_APIC_SPUR, "apic_spurious", (iroutine) apic_spurious);
 
    enable_irqs_function = io_apic_enable_irqs;
    disable_irqs_function = io_apic_disable_irqs;
    eoi_function = l_apic_eoi;
   
    /*
     * Configure interrupt routing.
     * IRQ 0 remains masked as the time signal is generated by l_apic's themselves.
     * Other interrupts will be forwarded to the lowest priority CPU.
     */
    io_apic_disable_irqs(0xffff);
   
    irq_initialize(&l_apic_timer_irq);
    l_apic_timer_irq.preack = true;
    l_apic_timer_irq.devno = device_assign_devno();
    l_apic_timer_irq.inr = IRQ_CLK;
    l_apic_timer_irq.claim = l_apic_timer_claim;
    l_apic_timer_irq.handler = l_apic_timer_irq_handler;
    irq_register(&l_apic_timer_irq);
   
    for (i = 0; i < IRQ_COUNT; i++) {
        int pin;
   
        if ((pin = smp_irq_to_pin(i)) != -1)
            io_apic_change_ioredtbl(pin, DEST_ALL, IVT_IRQBASE + i, LOPRI);
    }
   
    /*
     * Ensure that io_apic has unique ID.
     */
    idreg.value = io_apic_read(IOAPICID);
    if ((1 << idreg.apic_id) & apic_id_mask) {  /* see if IO APIC ID is used already */
        for (i = 0; i < APIC_ID_COUNT; i++) {
            if (!((1 << i) & apic_id_mask)) {
                idreg.apic_id = i;
                io_apic_write(IOAPICID, idreg.value);
                break;
            }
        }
    }
 
    /*
     * Configure the BSP's lapic.
     */
    l_apic_init();
 
    l_apic_debug();
}
 
/** Poll for APIC errors.
 *
 * Examine Error Status Register and report all errors found.
 *
 * @return 0 on error, 1 on success.
 */
int apic_poll_errors(void)
{
    esr_t esr;
   
    esr.value = l_apic[ESR];
   
    if (esr.send_checksum_error)
        printf("Send Checksum Error\n");
    if (esr.receive_checksum_error)
        printf("Receive Checksum Error\n");
    if (esr.send_accept_error)
        printf("Send Accept Error\n");
    if (esr.receive_accept_error)
        printf("Receive Accept Error\n");
    if (esr.send_illegal_vector)
        printf("Send Illegal Vector\n");
    if (esr.received_illegal_vector)
        printf("Received Illegal Vector\n");
    if (esr.illegal_register_address)
        printf("Illegal Register Address\n");
 
    return !esr.err_bitmap;
}
 
/** Send all CPUs excluding CPU IPI vector.
 *
 * @param vector Interrupt vector to be sent.
 *
 * @return 0 on failure, 1 on success.
 */
int l_apic_broadcast_custom_ipi(uint8_t vector)
{
    icr_t icr;
 
    icr.lo = l_apic[ICRlo];
    icr.delmod = DELMOD_FIXED;
    icr.destmod = DESTMOD_LOGIC;
    icr.level = LEVEL_ASSERT;
    icr.shorthand = SHORTHAND_ALL_EXCL;
    icr.trigger_mode = TRIGMOD_LEVEL;
    icr.vector = vector;
 
    l_apic[ICRlo] = icr.lo;
 
    icr.lo = l_apic[ICRlo];
    if (icr.delivs == DELIVS_PENDING) {
#ifdef CONFIG_DEBUG
        printf("IPI is pending.\n");
#endif
    }
 
    return apic_poll_errors();
}
 
/** Universal Start-up Algorithm for bringing up the AP processors.
 *
 * @param apicid APIC ID of the processor to be brought up.
 *
 * @return 0 on failure, 1 on success.
 */
int l_apic_send_init_ipi(uint8_t apicid)
{
    icr_t icr;
    int i;
 
    /*
     * Read the ICR register in and zero all non-reserved fields.
     */
    icr.lo = l_apic[ICRlo];
    icr.hi = l_apic[ICRhi];
   
    icr.delmod = DELMOD_INIT;
    icr.destmod = DESTMOD_PHYS;
    icr.level = LEVEL_ASSERT;
    icr.trigger_mode = TRIGMOD_LEVEL;
    icr.shorthand = SHORTHAND_NONE;
    icr.vector = 0;
    icr.dest = apicid;
   
    l_apic[ICRhi] = icr.hi;
    l_apic[ICRlo] = icr.lo;
 
    /*
     * According to MP Specification, 20us should be enough to
     * deliver the IPI.
     */
    delay(20);
 
    if (!apic_poll_errors())
        return 0;
 
    icr.lo = l_apic[ICRlo];
    if (icr.delivs == DELIVS_PENDING) {
#ifdef CONFIG_DEBUG
        printf("IPI is pending.\n");
#endif
    }
 
    icr.delmod = DELMOD_INIT;
    icr.destmod = DESTMOD_PHYS;
    icr.level = LEVEL_DEASSERT;
    icr.shorthand = SHORTHAND_NONE;
    icr.trigger_mode = TRIGMOD_LEVEL;
    icr.vector = 0;
    l_apic[ICRlo] = icr.lo;
 
    /*
     * Wait 10ms as MP Specification specifies.
     */
    delay(10000);
 
    if (!is_82489DX_apic(l_apic[LAVR])) {
        /*
         * If this is not 82489DX-based l_apic we must send two STARTUP IPI's.
         */
        for (i = 0; i<2; i++) {
            icr.lo = l_apic[ICRlo];
            icr.vector = ((uintptr_t) ap_boot) / 4096; /* calculate the reset vector */
            icr.delmod = DELMOD_STARTUP;
            icr.destmod = DESTMOD_PHYS;
            icr.level = LEVEL_ASSERT;
            icr.shorthand = SHORTHAND_NONE;
            icr.trigger_mode = TRIGMOD_LEVEL;
            l_apic[ICRlo] = icr.lo;
            delay(200);
        }
    }
   
    return apic_poll_errors();
}
 
/** Initialize Local APIC. */
void l_apic_init(void)
{
    lvt_error_t error;
    lvt_lint_t lint;
    tpr_t tpr;
    svr_t svr;
    icr_t icr;
    tdcr_t tdcr;
    lvt_tm_t tm;
    ldr_t ldr;
    dfr_t dfr;
    uint32_t t1, t2;
 
    /* Initialize LVT Error register. */
    error.value = l_apic[LVT_Err];
    error.masked = true;
    l_apic[LVT_Err] = error.value;
 
    /* Initialize LVT LINT0 register. */
    lint.value = l_apic[LVT_LINT0];
    lint.masked = true;
    l_apic[LVT_LINT0] = lint.value;
 
    /* Initialize LVT LINT1 register. */
    lint.value = l_apic[LVT_LINT1];
    lint.masked = true;
    l_apic[LVT_LINT1] = lint.value;
 
    /* Task Priority Register initialization. */
    tpr.value = l_apic[TPR];
    tpr.pri_sc = 0;
    tpr.pri = 0;
    l_apic[TPR] = tpr.value;
   
    /* Spurious-Interrupt Vector Register initialization. */
    svr.value = l_apic[SVR];
    svr.vector = VECTOR_APIC_SPUR;
    svr.lapic_enabled = true;
    svr.focus_checking = true;
    l_apic[SVR] = svr.value;
 
    if (CPU->arch.family >= 6)
        enable_l_apic_in_msr();
   
    /* Interrupt Command Register initialization. */
    icr.lo = l_apic[ICRlo];
    icr.delmod = DELMOD_INIT;
    icr.destmod = DESTMOD_PHYS;
    icr.level = LEVEL_DEASSERT;
    icr.shorthand = SHORTHAND_ALL_INCL;
    icr.trigger_mode = TRIGMOD_LEVEL;
    l_apic[ICRlo] = icr.lo;
   
    /* Timer Divide Configuration Register initialization. */
    tdcr.value = l_apic[TDCR];
    tdcr.div_value = DIVIDE_1;
    l_apic[TDCR] = tdcr.value;
 
    /* Program local timer. */
    tm.value = l_apic[LVT_Tm];
    tm.vector = VECTOR_CLK;
    tm.mode = TIMER_PERIODIC;
    tm.masked = false;
    l_apic[LVT_Tm] = tm.value;
 
    /*
     * Measure and configure the timer to generate timer
     * interrupt with period 1s/HZ seconds.
     */
    t1 = l_apic[CCRT];
    l_apic[ICRT] = 0xffffffff;
 
    while (l_apic[CCRT] == t1)
        ;
       
    t1 = l_apic[CCRT];
    delay(1000000/HZ);
    t2 = l_apic[CCRT];
   
    l_apic[ICRT] = t1-t2;
   
    /* Program Logical Destination Register. */
    ldr.value = l_apic[LDR];
    if (CPU->id < sizeof(CPU->id)*8)    /* size in bits */
        ldr.id = (1<<CPU->id);
    l_apic[LDR] = ldr.value;
   
    /* Program Destination Format Register for Flat mode. */
    dfr.value = l_apic[DFR];
    dfr.model = MODEL_FLAT;
    l_apic[DFR] = dfr.value;
}
 
/** Local APIC End of Interrupt. */
void l_apic_eoi(void)
{
    l_apic[EOI] = 0;
}
 
/** Dump content of Local APIC registers. */
void l_apic_debug(void)
{
#ifdef LAPIC_VERBOSE
    lvt_tm_t tm;
    lvt_lint_t lint;
    lvt_error_t error; 
   
    printf("LVT on cpu%d, LAPIC ID: %d\n", CPU->id, l_apic_id());
 
    tm.value = l_apic[LVT_Tm];
    printf("LVT Tm: vector=%hhd, %s, %s, %s\n", tm.vector, delivs_str[tm.delivs], mask_str[tm.masked], tm_mode_str[tm.mode]);
    lint.value = l_apic[LVT_LINT0];
    printf("LVT LINT0: vector=%hhd, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]);
    lint.value = l_apic[LVT_LINT1];
    printf("LVT LINT1: vector=%hhd, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]); 
    error.value = l_apic[LVT_Err];
    printf("LVT Err: vector=%hhd, %s, %s\n", error.vector, delivs_str[error.delivs], mask_str[error.masked]);
#endif
}
 
/** Get Local APIC ID.
 *
 * @return Local APIC ID.
 */
uint8_t l_apic_id(void)
{
    l_apic_id_t idreg;
   
    idreg.value = l_apic[L_APIC_ID];
    return idreg.apic_id;
}
 
/** Read from IO APIC register.
 *
 * @param address IO APIC register address.
 *
 * @return Content of the addressed IO APIC register.
 */
uint32_t io_apic_read(uint8_t address)
{
    io_regsel_t regsel;
   
    regsel.value = io_apic[IOREGSEL];
    regsel.reg_addr = address;
    io_apic[IOREGSEL] = regsel.value;
    return io_apic[IOWIN];
}
 
/** Write to IO APIC register.
 *
 * @param address IO APIC register address.
 * @param x Content to be written to the addressed IO APIC register.
 */
void io_apic_write(uint8_t address, uint32_t x)
{
    io_regsel_t regsel;
   
    regsel.value = io_apic[IOREGSEL];
    regsel.reg_addr = address;
    io_apic[IOREGSEL] = regsel.value;
    io_apic[IOWIN] = x;
}
 
/** Change some attributes of one item in I/O Redirection Table.
 *
 * @param pin IO APIC pin number.
 * @param dest Interrupt destination address.
 * @param v Interrupt vector to trigger.
 * @param flags Flags.
 */
void io_apic_change_ioredtbl(int pin, int dest, uint8_t v, int flags)
{
    io_redirection_reg_t reg;
    int dlvr = DELMOD_FIXED;
   
    if (flags & LOPRI)
        dlvr = DELMOD_LOWPRI;
 
    reg.lo = io_apic_read(IOREDTBL + pin*2);
    reg.hi = io_apic_read(IOREDTBL + pin*2 + 1);
   
    reg.dest = dest;
    reg.destmod = DESTMOD_LOGIC;
    reg.trigger_mode = TRIGMOD_EDGE;
    reg.intpol = POLARITY_HIGH;
    reg.delmod = dlvr;
    reg.intvec = v;
 
    io_apic_write(IOREDTBL + pin*2, reg.lo);
    io_apic_write(IOREDTBL + pin*2 + 1, reg.hi);
}
 
/** Mask IRQs in IO APIC.
 *
 * @param irqmask Bitmask of IRQs to be masked (0 = do not mask, 1 = mask).
 */
void io_apic_disable_irqs(uint16_t irqmask)
{
    io_redirection_reg_t reg;
    unsigned int i;
    int pin;
   
    for (i = 0; i < 16; i++) {
        if (irqmask & (1 << i)) {
            /*
             * Mask the signal input in IO APIC if there is a
             * mapping for the respective IRQ number.
             */
            pin = smp_irq_to_pin(i);
            if (pin != -1) {
                reg.lo = io_apic_read(IOREDTBL + pin * 2);
                reg.masked = true;
                io_apic_write(IOREDTBL + pin * 2, reg.lo);
            }
           
        }
    }
}
 
/** Unmask IRQs in IO APIC.
 *
 * @param irqmask Bitmask of IRQs to be unmasked (0 = do not unmask, 1 = unmask).
 */
void io_apic_enable_irqs(uint16_t irqmask)
{
    unsigned int i;
    int pin;
    io_redirection_reg_t reg;  
   
    for (i = 0;i < 16; i++) {
        if (irqmask & (1 << i)) {
            /*
             * Unmask the signal input in IO APIC if there is a
             * mapping for the respective IRQ number.
             */
            pin = smp_irq_to_pin(i);
            if (pin != -1) {
                reg.lo = io_apic_read(IOREDTBL + pin * 2);
                reg.masked = false;
                io_apic_write(IOREDTBL + pin * 2, reg.lo);
            }
           
        }
    }
}
 
#endif /* CONFIG_SMP */
 
/** @}
 */
 

Rev 2217	Rev 2218
1	/*	1	/*
2	* Copyright (c) 2001-2004 Jakub Jermar	2	* Copyright (c) 2001-2004 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	/** @addtogroup ia32	29	/** @addtogroup ia32
30	* @{	30	* @{
31	*/	31	*/
32	/** @file	32	/** @file
33	*/	33	*/
34		34
35	#include <arch/types.h>	35	#include <arch/types.h>
36	#include <arch/smp/apic.h>	36	#include <arch/smp/apic.h>
37	#include <arch/smp/ap.h>	37	#include <arch/smp/ap.h>
38	#include <arch/smp/mps.h>	38	#include <arch/smp/mps.h>
39	#include <arch/boot/boot.h>	39	#include <arch/boot/boot.h>
40	#include <mm/page.h>	40	#include <mm/page.h>
41	#include <time/delay.h>	41	#include <time/delay.h>
42	#include <interrupt.h>	42	#include <interrupt.h>
43	#include <arch/interrupt.h>	43	#include <arch/interrupt.h>
44	#include <print.h>	44	#include <print.h>
45	#include <arch/asm.h>	45	#include <arch/asm.h>
46	#include <arch.h>	46	#include <arch.h>
47	#include <ddi/irq.h>	47	#include <ddi/irq.h>
48	#include <ddi/device.h>	48	#include <ddi/device.h>
49		49
50	#ifdef CONFIG_SMP	50	#ifdef CONFIG_SMP
51		51
52	/*	52	/*
53	* Advanced Programmable Interrupt Controller for SMP systems.	53	* Advanced Programmable Interrupt Controller for SMP systems.
54	* Tested on:	54	* Tested on:
55	* Bochs 2.0.2 - Bochs 2.2.6 with 2-8 CPUs	55	* Bochs 2.0.2 - Bochs 2.2.6 with 2-8 CPUs
56	* Simics 2.0.28 - Simics 2.2.19 2-15 CPUs	56	* Simics 2.0.28 - Simics 2.2.19 2-15 CPUs
57	* VMware Workstation 5.5 with 2 CPUs	57	* VMware Workstation 5.5 with 2 CPUs
58	* QEMU 0.8.0 with 2-15 CPUs	58	* QEMU 0.8.0 with 2-15 CPUs
59	* ASUS P/I-P65UP5 + ASUS C-P55T2D REV. 1.41 with 2x 200Mhz Pentium CPUs	59	* ASUS P/I-P65UP5 + ASUS C-P55T2D REV. 1.41 with 2x 200Mhz Pentium CPUs
60	* ASUS PCH-DL with 2x 3000Mhz Pentium 4 Xeon (HT) CPUs	60	* ASUS PCH-DL with 2x 3000Mhz Pentium 4 Xeon (HT) CPUs
61	* MSI K7D Master-L with 2x 2100MHz Athlon MP CPUs	61	* MSI K7D Master-L with 2x 2100MHz Athlon MP CPUs
62	*/	62	*/
63		63
64	/*	64	/*
65	* These variables either stay configured as initilalized, or are changed by	65	* These variables either stay configured as initilalized, or are changed by
66	* the MP configuration code.	66	* the MP configuration code.
67	*	67	*
68	* Pay special attention to the volatile keyword. Without it, gcc -O2 would	68	* Pay special attention to the volatile keyword. Without it, gcc -O2 would
69	* optimize the code too much and accesses to l_apic and io_apic, that must	69	* optimize the code too much and accesses to l_apic and io_apic, that must
70	* always be 32-bit, would use byte oriented instructions.	70	* always be 32-bit, would use byte oriented instructions.
71	*/	71	*/
72	volatile uint32_t l_apic = (uint32_t ) 0xfee00000;	72	volatile uint32_t l_apic = (uint32_t ) 0xfee00000;
73	volatile uint32_t io_apic = (uint32_t ) 0xfec00000;	73	volatile uint32_t io_apic = (uint32_t ) 0xfec00000;
74		74
75	uint32_t apic_id_mask = 0;	75	uint32_t apic_id_mask = 0;
76	static irq_t l_apic_timer_irq;	76	static irq_t l_apic_timer_irq;
77		77
78	static int apic_poll_errors(void);	78	static int apic_poll_errors(void);
79		79
80	#ifdef LAPIC_VERBOSE	80	#ifdef LAPIC_VERBOSE
81	static char *delmod_str[] = {	81	static char *delmod_str[] = {
82	"Fixed",	82	"Fixed",
83	"Lowest Priority",	83	"Lowest Priority",
84	"SMI",	84	"SMI",
85	"Reserved",	85	"Reserved",
86	"NMI",	86	"NMI",
87	"INIT",	87	"INIT",
88	"STARTUP",	88	"STARTUP",
89	"ExtInt"	89	"ExtInt"
90	};	90	};
91		91
92	static char *destmod_str[] = {	92	static char *destmod_str[] = {
93	"Physical",	93	"Physical",
94	"Logical"	94	"Logical"
95	};	95	};
96		96
97	static char *trigmod_str[] = {	97	static char *trigmod_str[] = {
98	"Edge",	98	"Edge",
99	"Level"	99	"Level"
100	};	100	};
101		101
102	static char *mask_str[] = {	102	static char *mask_str[] = {
103	"Unmasked",	103	"Unmasked",
104	"Masked"	104	"Masked"
105	};	105	};
106		106
107	static char *delivs_str[] = {	107	static char *delivs_str[] = {
108	"Idle",	108	"Idle",
109	"Send Pending"	109	"Send Pending"
110	};	110	};
111		111
112	static char *tm_mode_str[] = {	112	static char *tm_mode_str[] = {
113	"One-shot",	113	"One-shot",
114	"Periodic"	114	"Periodic"
115	};	115	};
116		116
117	static char *intpol_str[] = {	117	static char *intpol_str[] = {
118	"Polarity High",	118	"Polarity High",
119	"Polarity Low"	119	"Polarity Low"
120	};	120	};
121	#endif /* LAPIC_VERBOSE */	121	#endif /* LAPIC_VERBOSE */
122		122
123	/** APIC spurious interrupt handler.	123	/** APIC spurious interrupt handler.
124	*	124	*
125	* @param n Interrupt vector.	125	* @param n Interrupt vector.
126	* @param istate Interrupted state.	126	* @param istate Interrupted state.
127	*/	127	*/
128	static void apic_spurious(int n, istate_t *istate)	128	static void apic_spurious(int n, istate_t *istate)
129	{	129	{
130	#ifdef CONFIG_DEBUG	130	#ifdef CONFIG_DEBUG
131	printf("cpu%d: APIC spurious interrupt\n", CPU->id);	131	printf("cpu%d: APIC spurious interrupt\n", CPU->id);
132	#endif	132	#endif
133	}	133	}
134		134
135	static irq_ownership_t l_apic_timer_claim(void)	135	static irq_ownership_t l_apic_timer_claim(void)
136	{	136	{
137	return IRQ_ACCEPT;	137	return IRQ_ACCEPT;
138	}	138	}
139		139
140	static void l_apic_timer_irq_handler(irq_t irq, void arg, ...)	140	static void l_apic_timer_irq_handler(irq_t irq, void arg, ...)
141	{	141	{
142	/*	142	/*
143	* Holding a spinlock could prevent clock() from preempting	143	* Holding a spinlock could prevent clock() from preempting
144	* the current thread. In this case, we don't need to hold the	144	* the current thread. In this case, we don't need to hold the
145	* irq->lock so we just unlock it and then lock it again.	145	* irq->lock so we just unlock it and then lock it again.
146	*/	146	*/
147	spinlock_unlock(&irq->lock);	147	spinlock_unlock(&irq->lock);
148	clock();	148	clock();
149	spinlock_lock(&irq->lock);	149	spinlock_lock(&irq->lock);
150	}	150	}
151		151
152	/** Initialize APIC on BSP. */	152	/** Initialize APIC on BSP. */
153	void apic_init(void)	153	void apic_init(void)
154	{	154	{
155	io_apic_id_t idreg;	155	io_apic_id_t idreg;
156	unsigned int i;	156	unsigned int i;
157		157
158	exc_register(VECTOR_APIC_SPUR, "apic_spurious", (iroutine) apic_spurious);	158	exc_register(VECTOR_APIC_SPUR, "apic_spurious", (iroutine) apic_spurious);
159		159
160	enable_irqs_function = io_apic_enable_irqs;	160	enable_irqs_function = io_apic_enable_irqs;
161	disable_irqs_function = io_apic_disable_irqs;	161	disable_irqs_function = io_apic_disable_irqs;
162	eoi_function = l_apic_eoi;	162	eoi_function = l_apic_eoi;
163		163
164	/*	164	/*
165	* Configure interrupt routing.	165	* Configure interrupt routing.
166	* IRQ 0 remains masked as the time signal is generated by l_apic's themselves.	166	* IRQ 0 remains masked as the time signal is generated by l_apic's themselves.
167	* Other interrupts will be forwarded to the lowest priority CPU.	167	* Other interrupts will be forwarded to the lowest priority CPU.
168	*/	168	*/
169	io_apic_disable_irqs(0xffff);	169	io_apic_disable_irqs(0xffff);
170		170
171	irq_initialize(&l_apic_timer_irq);	171	irq_initialize(&l_apic_timer_irq);
-		172	l_apic_timer_irq.preack = true;
172	l_apic_timer_irq.devno = device_assign_devno();	173	l_apic_timer_irq.devno = device_assign_devno();
173	l_apic_timer_irq.inr = IRQ_CLK;	174	l_apic_timer_irq.inr = IRQ_CLK;
174	l_apic_timer_irq.claim = l_apic_timer_claim;	175	l_apic_timer_irq.claim = l_apic_timer_claim;
175	l_apic_timer_irq.handler = l_apic_timer_irq_handler;	176	l_apic_timer_irq.handler = l_apic_timer_irq_handler;
176	irq_register(&l_apic_timer_irq);	177	irq_register(&l_apic_timer_irq);
177		178
178	for (i = 0; i < IRQ_COUNT; i++) {	179	for (i = 0; i < IRQ_COUNT; i++) {
179	int pin;	180	int pin;
180		181
181	if ((pin = smp_irq_to_pin(i)) != -1)	182	if ((pin = smp_irq_to_pin(i)) != -1)
182	io_apic_change_ioredtbl(pin, DEST_ALL, IVT_IRQBASE + i, LOPRI);	183	io_apic_change_ioredtbl(pin, DEST_ALL, IVT_IRQBASE + i, LOPRI);
183	}	184	}
184		185
185	/*	186	/*
186	* Ensure that io_apic has unique ID.	187	* Ensure that io_apic has unique ID.
187	*/	188	*/
188	idreg.value = io_apic_read(IOAPICID);	189	idreg.value = io_apic_read(IOAPICID);
189	if ((1 << idreg.apic_id) & apic_id_mask) { /* see if IO APIC ID is used already */	190	if ((1 << idreg.apic_id) & apic_id_mask) { /* see if IO APIC ID is used already */
190	for (i = 0; i < APIC_ID_COUNT; i++) {	191	for (i = 0; i < APIC_ID_COUNT; i++) {
191	if (!((1 << i) & apic_id_mask)) {	192	if (!((1 << i) & apic_id_mask)) {
192	idreg.apic_id = i;	193	idreg.apic_id = i;
193	io_apic_write(IOAPICID, idreg.value);	194	io_apic_write(IOAPICID, idreg.value);
194	break;	195	break;
195	}	196	}
196	}	197	}
197	}	198	}
198		199
199	/*	200	/*
200	* Configure the BSP's lapic.	201	* Configure the BSP's lapic.
201	*/	202	*/
202	l_apic_init();	203	l_apic_init();
203		204
204	l_apic_debug();	205	l_apic_debug();
205	}	206	}
206		207
207	/** Poll for APIC errors.	208	/** Poll for APIC errors.
208	*	209	*
209	* Examine Error Status Register and report all errors found.	210	* Examine Error Status Register and report all errors found.
210	*	211	*
211	* @return 0 on error, 1 on success.	212	* @return 0 on error, 1 on success.
212	*/	213	*/
213	int apic_poll_errors(void)	214	int apic_poll_errors(void)
214	{	215	{
215	esr_t esr;	216	esr_t esr;
216		217
217	esr.value = l_apic[ESR];	218	esr.value = l_apic[ESR];
218		219
219	if (esr.send_checksum_error)	220	if (esr.send_checksum_error)
220	printf("Send Checksum Error\n");	221	printf("Send Checksum Error\n");
221	if (esr.receive_checksum_error)	222	if (esr.receive_checksum_error)
222	printf("Receive Checksum Error\n");	223	printf("Receive Checksum Error\n");
223	if (esr.send_accept_error)	224	if (esr.send_accept_error)
224	printf("Send Accept Error\n");	225	printf("Send Accept Error\n");
225	if (esr.receive_accept_error)	226	if (esr.receive_accept_error)
226	printf("Receive Accept Error\n");	227	printf("Receive Accept Error\n");
227	if (esr.send_illegal_vector)	228	if (esr.send_illegal_vector)
228	printf("Send Illegal Vector\n");	229	printf("Send Illegal Vector\n");
229	if (esr.received_illegal_vector)	230	if (esr.received_illegal_vector)
230	printf("Received Illegal Vector\n");	231	printf("Received Illegal Vector\n");
231	if (esr.illegal_register_address)	232	if (esr.illegal_register_address)
232	printf("Illegal Register Address\n");	233	printf("Illegal Register Address\n");
233		234
234	return !esr.err_bitmap;	235	return !esr.err_bitmap;
235	}	236	}
236		237
237	/** Send all CPUs excluding CPU IPI vector.	238	/** Send all CPUs excluding CPU IPI vector.
238	*	239	*
239	* @param vector Interrupt vector to be sent.	240	* @param vector Interrupt vector to be sent.
240	*	241	*
241	* @return 0 on failure, 1 on success.	242	* @return 0 on failure, 1 on success.
242	*/	243	*/
243	int l_apic_broadcast_custom_ipi(uint8_t vector)	244	int l_apic_broadcast_custom_ipi(uint8_t vector)
244	{	245	{
245	icr_t icr;	246	icr_t icr;
246		247
247	icr.lo = l_apic[ICRlo];	248	icr.lo = l_apic[ICRlo];
248	icr.delmod = DELMOD_FIXED;	249	icr.delmod = DELMOD_FIXED;
249	icr.destmod = DESTMOD_LOGIC;	250	icr.destmod = DESTMOD_LOGIC;
250	icr.level = LEVEL_ASSERT;	251	icr.level = LEVEL_ASSERT;
251	icr.shorthand = SHORTHAND_ALL_EXCL;	252	icr.shorthand = SHORTHAND_ALL_EXCL;
252	icr.trigger_mode = TRIGMOD_LEVEL;	253	icr.trigger_mode = TRIGMOD_LEVEL;
253	icr.vector = vector;	254	icr.vector = vector;
254		255
255	l_apic[ICRlo] = icr.lo;	256	l_apic[ICRlo] = icr.lo;
256		257
257	icr.lo = l_apic[ICRlo];	258	icr.lo = l_apic[ICRlo];
258	if (icr.delivs == DELIVS_PENDING) {	259	if (icr.delivs == DELIVS_PENDING) {
259	#ifdef CONFIG_DEBUG	260	#ifdef CONFIG_DEBUG
260	printf("IPI is pending.\n");	261	printf("IPI is pending.\n");
261	#endif	262	#endif
262	}	263	}
263		264
264	return apic_poll_errors();	265	return apic_poll_errors();
265	}	266	}
266		267
267	/** Universal Start-up Algorithm for bringing up the AP processors.	268	/** Universal Start-up Algorithm for bringing up the AP processors.
268	*	269	*
269	* @param apicid APIC ID of the processor to be brought up.	270	* @param apicid APIC ID of the processor to be brought up.
270	*	271	*
271	* @return 0 on failure, 1 on success.	272	* @return 0 on failure, 1 on success.
272	*/	273	*/
273	int l_apic_send_init_ipi(uint8_t apicid)	274	int l_apic_send_init_ipi(uint8_t apicid)
274	{	275	{
275	icr_t icr;	276	icr_t icr;
276	int i;	277	int i;
277		278
278	/*	279	/*
279	* Read the ICR register in and zero all non-reserved fields.	280	* Read the ICR register in and zero all non-reserved fields.
280	*/	281	*/
281	icr.lo = l_apic[ICRlo];	282	icr.lo = l_apic[ICRlo];
282	icr.hi = l_apic[ICRhi];	283	icr.hi = l_apic[ICRhi];
283		284
284	icr.delmod = DELMOD_INIT;	285	icr.delmod = DELMOD_INIT;
285	icr.destmod = DESTMOD_PHYS;	286	icr.destmod = DESTMOD_PHYS;
286	icr.level = LEVEL_ASSERT;	287	icr.level = LEVEL_ASSERT;
287	icr.trigger_mode = TRIGMOD_LEVEL;	288	icr.trigger_mode = TRIGMOD_LEVEL;
288	icr.shorthand = SHORTHAND_NONE;	289	icr.shorthand = SHORTHAND_NONE;
289	icr.vector = 0;	290	icr.vector = 0;
290	icr.dest = apicid;	291	icr.dest = apicid;
291		292
292	l_apic[ICRhi] = icr.hi;	293	l_apic[ICRhi] = icr.hi;
293	l_apic[ICRlo] = icr.lo;	294	l_apic[ICRlo] = icr.lo;
294		295
295	/*	296	/*
296	* According to MP Specification, 20us should be enough to	297	* According to MP Specification, 20us should be enough to
297	* deliver the IPI.	298	* deliver the IPI.
298	*/	299	*/
299	delay(20);	300	delay(20);
300		301
301	if (!apic_poll_errors())	302	if (!apic_poll_errors())
302	return 0;	303	return 0;
303		304
304	icr.lo = l_apic[ICRlo];	305	icr.lo = l_apic[ICRlo];
305	if (icr.delivs == DELIVS_PENDING) {	306	if (icr.delivs == DELIVS_PENDING) {
306	#ifdef CONFIG_DEBUG	307	#ifdef CONFIG_DEBUG
307	printf("IPI is pending.\n");	308	printf("IPI is pending.\n");
308	#endif	309	#endif
309	}	310	}
310		311
311	icr.delmod = DELMOD_INIT;	312	icr.delmod = DELMOD_INIT;
312	icr.destmod = DESTMOD_PHYS;	313	icr.destmod = DESTMOD_PHYS;
313	icr.level = LEVEL_DEASSERT;	314	icr.level = LEVEL_DEASSERT;
314	icr.shorthand = SHORTHAND_NONE;	315	icr.shorthand = SHORTHAND_NONE;
315	icr.trigger_mode = TRIGMOD_LEVEL;	316	icr.trigger_mode = TRIGMOD_LEVEL;
316	icr.vector = 0;	317	icr.vector = 0;
317	l_apic[ICRlo] = icr.lo;	318	l_apic[ICRlo] = icr.lo;
318		319
319	/*	320	/*
320	* Wait 10ms as MP Specification specifies.	321	* Wait 10ms as MP Specification specifies.
321	*/	322	*/
322	delay(10000);	323	delay(10000);
323		324
324	if (!is_82489DX_apic(l_apic[LAVR])) {	325	if (!is_82489DX_apic(l_apic[LAVR])) {
325	/*	326	/*
326	* If this is not 82489DX-based l_apic we must send two STARTUP IPI's.	327	* If this is not 82489DX-based l_apic we must send two STARTUP IPI's.
327	*/	328	*/
328	for (i = 0; i<2; i++) {	329	for (i = 0; i<2; i++) {
329	icr.lo = l_apic[ICRlo];	330	icr.lo = l_apic[ICRlo];
330	icr.vector = ((uintptr_t) ap_boot) / 4096; /* calculate the reset vector */	331	icr.vector = ((uintptr_t) ap_boot) / 4096; /* calculate the reset vector */
331	icr.delmod = DELMOD_STARTUP;	332	icr.delmod = DELMOD_STARTUP;
332	icr.destmod = DESTMOD_PHYS;	333	icr.destmod = DESTMOD_PHYS;
333	icr.level = LEVEL_ASSERT;	334	icr.level = LEVEL_ASSERT;
334	icr.shorthand = SHORTHAND_NONE;	335	icr.shorthand = SHORTHAND_NONE;
335	icr.trigger_mode = TRIGMOD_LEVEL;	336	icr.trigger_mode = TRIGMOD_LEVEL;
336	l_apic[ICRlo] = icr.lo;	337	l_apic[ICRlo] = icr.lo;
337	delay(200);	338	delay(200);
338	}	339	}
339	}	340	}
340		341
341	return apic_poll_errors();	342	return apic_poll_errors();
342	}	343	}
343		344
344	/** Initialize Local APIC. */	345	/** Initialize Local APIC. */
345	void l_apic_init(void)	346	void l_apic_init(void)
346	{	347	{
347	lvt_error_t error;	348	lvt_error_t error;
348	lvt_lint_t lint;	349	lvt_lint_t lint;
349	tpr_t tpr;	350	tpr_t tpr;
350	svr_t svr;	351	svr_t svr;
351	icr_t icr;	352	icr_t icr;
352	tdcr_t tdcr;	353	tdcr_t tdcr;
353	lvt_tm_t tm;	354	lvt_tm_t tm;
354	ldr_t ldr;	355	ldr_t ldr;
355	dfr_t dfr;	356	dfr_t dfr;
356	uint32_t t1, t2;	357	uint32_t t1, t2;
357		358
358	/* Initialize LVT Error register. */	359	/* Initialize LVT Error register. */
359	error.value = l_apic[LVT_Err];	360	error.value = l_apic[LVT_Err];
360	error.masked = true;	361	error.masked = true;
361	l_apic[LVT_Err] = error.value;	362	l_apic[LVT_Err] = error.value;
362		363
363	/* Initialize LVT LINT0 register. */	364	/* Initialize LVT LINT0 register. */
364	lint.value = l_apic[LVT_LINT0];	365	lint.value = l_apic[LVT_LINT0];
365	lint.masked = true;	366	lint.masked = true;
366	l_apic[LVT_LINT0] = lint.value;	367	l_apic[LVT_LINT0] = lint.value;
367		368
368	/* Initialize LVT LINT1 register. */	369	/* Initialize LVT LINT1 register. */
369	lint.value = l_apic[LVT_LINT1];	370	lint.value = l_apic[LVT_LINT1];
370	lint.masked = true;	371	lint.masked = true;
371	l_apic[LVT_LINT1] = lint.value;	372	l_apic[LVT_LINT1] = lint.value;
372		373
373	/* Task Priority Register initialization. */	374	/* Task Priority Register initialization. */
374	tpr.value = l_apic[TPR];	375	tpr.value = l_apic[TPR];
375	tpr.pri_sc = 0;	376	tpr.pri_sc = 0;
376	tpr.pri = 0;	377	tpr.pri = 0;
377	l_apic[TPR] = tpr.value;	378	l_apic[TPR] = tpr.value;
378		379
379	/* Spurious-Interrupt Vector Register initialization. */	380	/* Spurious-Interrupt Vector Register initialization. */
380	svr.value = l_apic[SVR];	381	svr.value = l_apic[SVR];
381	svr.vector = VECTOR_APIC_SPUR;	382	svr.vector = VECTOR_APIC_SPUR;
382	svr.lapic_enabled = true;	383	svr.lapic_enabled = true;
383	svr.focus_checking = true;	384	svr.focus_checking = true;
384	l_apic[SVR] = svr.value;	385	l_apic[SVR] = svr.value;
385		386
386	if (CPU->arch.family >= 6)	387	if (CPU->arch.family >= 6)
387	enable_l_apic_in_msr();	388	enable_l_apic_in_msr();
388		389
389	/* Interrupt Command Register initialization. */	390	/* Interrupt Command Register initialization. */
390	icr.lo = l_apic[ICRlo];	391	icr.lo = l_apic[ICRlo];
391	icr.delmod = DELMOD_INIT;	392	icr.delmod = DELMOD_INIT;
392	icr.destmod = DESTMOD_PHYS;	393	icr.destmod = DESTMOD_PHYS;
393	icr.level = LEVEL_DEASSERT;	394	icr.level = LEVEL_DEASSERT;
394	icr.shorthand = SHORTHAND_ALL_INCL;	395	icr.shorthand = SHORTHAND_ALL_INCL;
395	icr.trigger_mode = TRIGMOD_LEVEL;	396	icr.trigger_mode = TRIGMOD_LEVEL;
396	l_apic[ICRlo] = icr.lo;	397	l_apic[ICRlo] = icr.lo;
397		398
398	/* Timer Divide Configuration Register initialization. */	399	/* Timer Divide Configuration Register initialization. */
399	tdcr.value = l_apic[TDCR];	400	tdcr.value = l_apic[TDCR];
400	tdcr.div_value = DIVIDE_1;	401	tdcr.div_value = DIVIDE_1;
401	l_apic[TDCR] = tdcr.value;	402	l_apic[TDCR] = tdcr.value;
402		403
403	/* Program local timer. */	404	/* Program local timer. */
404	tm.value = l_apic[LVT_Tm];	405	tm.value = l_apic[LVT_Tm];
405	tm.vector = VECTOR_CLK;	406	tm.vector = VECTOR_CLK;
406	tm.mode = TIMER_PERIODIC;	407	tm.mode = TIMER_PERIODIC;
407	tm.masked = false;	408	tm.masked = false;
408	l_apic[LVT_Tm] = tm.value;	409	l_apic[LVT_Tm] = tm.value;
409		410
410	/*	411	/*
411	* Measure and configure the timer to generate timer	412	* Measure and configure the timer to generate timer
412	* interrupt with period 1s/HZ seconds.	413	* interrupt with period 1s/HZ seconds.
413	*/	414	*/
414	t1 = l_apic[CCRT];	415	t1 = l_apic[CCRT];
415	l_apic[ICRT] = 0xffffffff;	416	l_apic[ICRT] = 0xffffffff;
416		417
417	while (l_apic[CCRT] == t1)	418	while (l_apic[CCRT] == t1)
418	;	419	;
419		420
420	t1 = l_apic[CCRT];	421	t1 = l_apic[CCRT];
421	delay(1000000/HZ);	422	delay(1000000/HZ);
422	t2 = l_apic[CCRT];	423	t2 = l_apic[CCRT];
423		424
424	l_apic[ICRT] = t1-t2;	425	l_apic[ICRT] = t1-t2;
425		426
426	/* Program Logical Destination Register. */	427	/* Program Logical Destination Register. */
427	ldr.value = l_apic[LDR];	428	ldr.value = l_apic[LDR];
428	if (CPU->id < sizeof(CPU->id)8) / size in bits */	429	if (CPU->id < sizeof(CPU->id)8) / size in bits */
429	ldr.id = (1<<CPU->id);	430	ldr.id = (1<<CPU->id);
430	l_apic[LDR] = ldr.value;	431	l_apic[LDR] = ldr.value;
431		432
432	/* Program Destination Format Register for Flat mode. */	433	/* Program Destination Format Register for Flat mode. */
433	dfr.value = l_apic[DFR];	434	dfr.value = l_apic[DFR];
434	dfr.model = MODEL_FLAT;	435	dfr.model = MODEL_FLAT;
435	l_apic[DFR] = dfr.value;	436	l_apic[DFR] = dfr.value;
436	}	437	}
437		438
438	/** Local APIC End of Interrupt. */	439	/** Local APIC End of Interrupt. */
439	void l_apic_eoi(void)	440	void l_apic_eoi(void)
440	{	441	{
441	l_apic[EOI] = 0;	442	l_apic[EOI] = 0;
442	}	443	}
443		444
444	/** Dump content of Local APIC registers. */	445	/** Dump content of Local APIC registers. */
445	void l_apic_debug(void)	446	void l_apic_debug(void)
446	{	447	{
447	#ifdef LAPIC_VERBOSE	448	#ifdef LAPIC_VERBOSE
448	lvt_tm_t tm;	449	lvt_tm_t tm;
449	lvt_lint_t lint;	450	lvt_lint_t lint;
450	lvt_error_t error;	451	lvt_error_t error;
451		452
452	printf("LVT on cpu%d, LAPIC ID: %d\n", CPU->id, l_apic_id());	453	printf("LVT on cpu%d, LAPIC ID: %d\n", CPU->id, l_apic_id());
453		454
454	tm.value = l_apic[LVT_Tm];	455	tm.value = l_apic[LVT_Tm];
455	printf("LVT Tm: vector=%hhd, %s, %s, %s\n", tm.vector, delivs_str[tm.delivs], mask_str[tm.masked], tm_mode_str[tm.mode]);	456	printf("LVT Tm: vector=%hhd, %s, %s, %s\n", tm.vector, delivs_str[tm.delivs], mask_str[tm.masked], tm_mode_str[tm.mode]);
456	lint.value = l_apic[LVT_LINT0];	457	lint.value = l_apic[LVT_LINT0];
457	printf("LVT LINT0: vector=%hhd, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]);	458	printf("LVT LINT0: vector=%hhd, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]);
458	lint.value = l_apic[LVT_LINT1];	459	lint.value = l_apic[LVT_LINT1];
459	printf("LVT LINT1: vector=%hhd, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]);	460	printf("LVT LINT1: vector=%hhd, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]);
460	error.value = l_apic[LVT_Err];	461	error.value = l_apic[LVT_Err];
461	printf("LVT Err: vector=%hhd, %s, %s\n", error.vector, delivs_str[error.delivs], mask_str[error.masked]);	462	printf("LVT Err: vector=%hhd, %s, %s\n", error.vector, delivs_str[error.delivs], mask_str[error.masked]);
462	#endif	463	#endif
463	}	464	}
464		465
465	/** Get Local APIC ID.	466	/** Get Local APIC ID.
466	*	467	*
467	* @return Local APIC ID.	468	* @return Local APIC ID.
468	*/	469	*/
469	uint8_t l_apic_id(void)	470	uint8_t l_apic_id(void)
470	{	471	{
471	l_apic_id_t idreg;	472	l_apic_id_t idreg;
472		473
473	idreg.value = l_apic[L_APIC_ID];	474	idreg.value = l_apic[L_APIC_ID];
474	return idreg.apic_id;	475	return idreg.apic_id;
475	}	476	}
476		477
477	/** Read from IO APIC register.	478	/** Read from IO APIC register.
478	*	479	*
479	* @param address IO APIC register address.	480	* @param address IO APIC register address.
480	*	481	*
481	* @return Content of the addressed IO APIC register.	482	* @return Content of the addressed IO APIC register.
482	*/	483	*/
483	uint32_t io_apic_read(uint8_t address)	484	uint32_t io_apic_read(uint8_t address)
484	{	485	{
485	io_regsel_t regsel;	486	io_regsel_t regsel;
486		487
487	regsel.value = io_apic[IOREGSEL];	488	regsel.value = io_apic[IOREGSEL];
488	regsel.reg_addr = address;	489	regsel.reg_addr = address;
489	io_apic[IOREGSEL] = regsel.value;	490	io_apic[IOREGSEL] = regsel.value;
490	return io_apic[IOWIN];	491	return io_apic[IOWIN];
491	}	492	}
492		493
493	/** Write to IO APIC register.	494	/** Write to IO APIC register.
494	*	495	*
495	* @param address IO APIC register address.	496	* @param address IO APIC register address.
496	* @param x Content to be written to the addressed IO APIC register.	497	* @param x Content to be written to the addressed IO APIC register.
497	*/	498	*/
498	void io_apic_write(uint8_t address, uint32_t x)	499	void io_apic_write(uint8_t address, uint32_t x)
499	{	500	{

Subversion Repositories HelenOS

(root)/trunk/kernel/arch/ia32/src/smp/apic.c – Rev 2217 → 2218