WebSVN – HelenOS – Diff – /trunk/kernel/arch/ia32/src/asm.S


#
# Copyright (c) 2001-2004 Jakub Jermar
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# - Redistributions of source code must retain the above copyright
#   notice, this list of conditions and the following disclaimer.
# - Redistributions in binary form must reproduce the above copyright
#   notice, this list of conditions and the following disclaimer in the
#   documentation and/or other materials provided with the distribution.
# - The name of the author may not be used to endorse or promote products
#   derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
 
## very low and hardware-level functions
 
# Mask for interrupts 0 - 31 (bits 0 - 31) where 0 means that int has no error
# word and 1 means interrupt with error word
#define ERROR_WORD_INTERRUPT_LIST 0x00027d00
 
.text
 
.global paging_on
.global enable_l_apic_in_msr
.global interrupt_handlers
.global memsetb
.global memsetw
.global memcpy
.global memcpy_from_uspace
.global memcpy_from_uspace_failover_address
.global memcpy_to_uspace
.global memcpy_to_uspace_failover_address
 
 
# Wrapper for generic memsetb
memsetb:
	jmp _memsetb
 
# Wrapper for generic memsetw
memsetw:
	jmp _memsetw
 
 
#define MEMCPY_DST	4
#define MEMCPY_SRC	8
#define MEMCPY_SIZE	12
 
/** Copy memory to/from userspace.
 *
 * This is almost conventional memcpy().
 * The difference is that there is a failover part
 * to where control is returned from a page fault
 * if the page fault occurs during copy_from_uspace()
 * or copy_to_uspace().
 *
 * @param MEMCPY_DST(%esp)	Destination address.
 * @param MEMCPY_SRC(%esp)	Source address.
 * @param MEMCPY_SIZE(%esp)	Size.
 *
 * @return MEMCPY_DST(%esp) on success and 0 on failure.
 */
memcpy:
memcpy_from_uspace:
memcpy_to_uspace:
	movl %edi, %edx			/* save %edi */
	movl %esi, %eax			/* save %esi */
	
	movl MEMCPY_SIZE(%esp), %ecx
	shrl $2, %ecx			/* size / 4 */
	
	movl MEMCPY_DST(%esp), %edi
	movl MEMCPY_SRC(%esp), %esi
	
	rep movsl			/* copy whole words */
 
	movl MEMCPY_SIZE(%esp), %ecx
	andl $3, %ecx			/* size % 4 */
	jz 0f
	
	rep movsb			/* copy the rest byte by byte */
 
0:
	movl %edx, %edi
	movl %eax, %esi
	movl MEMCPY_DST(%esp), %eax	/* MEMCPY_DST(%esp), success */
	ret
	
/*
 * We got here from as_page_fault() after the memory operations
 * above had caused a page fault.
 */
memcpy_from_uspace_failover_address:
memcpy_to_uspace_failover_address:
	movl %edx, %edi
	movl %eax, %esi
	xorl %eax, %eax			/* return 0, failure */
	ret
 
## Turn paging on
#
# Enable paging and write-back caching in CR0.
#
paging_on:
	movl %cr0, %edx
	orl $(1 << 31), %edx		# paging on
	# clear Cache Disable and not Write Though
	andl $~((1 << 30) | (1 << 29)), %edx
	movl %edx,%cr0
	jmp 0f
0:
	ret
 
 
## Enable local APIC
#
# Enable local APIC in MSR.
#
enable_l_apic_in_msr:
	movl $0x1b, %ecx
	rdmsr
	orl $(1 << 11), %eax
	orl $(0xfee00000), %eax
	wrmsr
	ret
 
# Clear nested flag
# overwrites %ecx
.macro CLEAR_NT_FLAG
	pushfl
	pop %ecx
	and $0xffffbfff, %ecx
	push %ecx
	popfl
.endm	
 
## Declare interrupt handlers
#
# Declare interrupt handlers for n interrupt
# vectors starting at vector i.
#
# The handlers setup data segment registers
# and call exc_dispatch().
#
#define INTERRUPT_ALIGN 64
.macro handler i n
 
.ifeq \i - 0x30     # Syscall handler
	pushl %ds
	pushl %es
	pushl %fs
	pushl %gs
 
	#
	# Push syscall arguments onto the stack
	#
	# NOTE: The idea behind the order of arguments passed in registers is to
	#	use all scratch registers first and preserved registers next.
	#	An optimized libc syscall wrapper can make use of this setup.
	#
	pushl %eax
	pushl %ebp
	pushl %edi
	pushl %esi
	pushl %ebx
	pushl %ecx
	pushl %edx
	
	# we must fill the data segment registers
	movw $16, %ax
	movw %ax, %ds
	movw %ax, %es
	
	cld
	sti
	# syscall_handler(edx, ecx, ebx, esi, edi, ebp, eax)
	call syscall_handler   
	cli
	addl $28, %esp         # clean-up of parameters
	
	popl %gs
	popl %fs
	popl %es
	popl %ds
	
	CLEAR_NT_FLAG
	iret
.else	
	/*
	 * This macro distinguishes between two versions of ia32 exceptions.
	 * One version has error word and the other does not have it.
	 * The latter version fakes the error word on the stack so that the
	 * handlers and istate_t can be the same for both types.
	 */
	.iflt \i - 32
		.if (1 << \i) & ERROR_WORD_INTERRUPT_LIST
			/* 
			 * With error word, do nothing
			 */
                .else
                        /*
                         * Version without error word,
                         */
			subl $4, %esp
                .endif
        .else
                /*
                 * Version without error word,
                 */
		subl $4, %esp
	.endif
	
	pushl %ds
	pushl %es
	pushl %fs
	pushl %gs
 
#ifdef CONFIG_DEBUG_ALLREGS
	pushl %ebx
	pushl %ebp
	pushl %edi
	pushl %esi
#else
	subl $16, %esp
#endif
	pushl %edx
	pushl %ecx
	pushl %eax
	
	# we must fill the data segment registers
	movw $16, %ax
	movw %ax, %ds
	movw %ax, %es
 
	cld
 
	pushl %esp          # *istate
	pushl $(\i)         # intnum
	call exc_dispatch   # excdispatch(intnum, *istate)
	addl $8, %esp       # Clear arguments from stack
 
	CLEAR_NT_FLAG # Modifies %ecx
	
	popl %eax
	popl %ecx
	popl %edx
#ifdef CONFIG_DEBUG_ALLREGS
	popl %esi
	popl %edi
	popl %ebp
	popl %ebx
#else
	addl $16, %esp
#endif	
	
	popl %gs
	popl %fs
	popl %es
	popl %ds
 
	addl $4, %esp	# Skip error word, no matter whether real or fake.
	iret
.endif
 
	.align INTERRUPT_ALIGN
	.if (\n- \i) - 1
	handler "(\i + 1)", \n
	.endif
.endm
 
# keep in sync with pm.h !!!
IDT_ITEMS = 64
.align INTERRUPT_ALIGN
interrupt_handlers:
h_start:
	handler 0 IDT_ITEMS
h_end:
 
.data
.global interrupt_handler_size
 
interrupt_handler_size: .long (h_end - h_start) / IDT_ITEMS
 

Rev 3043	Rev 3274
1	#	1	#
2	# Copyright (c) 2001-2004 Jakub Jermar	2	# Copyright (c) 2001-2004 Jakub Jermar
3	# All rights reserved.	3	# All rights reserved.
4	#	4	#
5	# Redistribution and use in source and binary forms, with or without	5	# Redistribution and use in source and binary forms, with or without
6	# modification, are permitted provided that the following conditions	6	# modification, are permitted provided that the following conditions
7	# are met:	7	# are met:
8	#	8	#
9	# - Redistributions of source code must retain the above copyright	9	# - Redistributions of source code must retain the above copyright
10	# notice, this list of conditions and the following disclaimer.	10	# notice, this list of conditions and the following disclaimer.
11	# - Redistributions in binary form must reproduce the above copyright	11	# - Redistributions in binary form must reproduce the above copyright
12	# notice, this list of conditions and the following disclaimer in the	12	# notice, this list of conditions and the following disclaimer in the
13	# documentation and/or other materials provided with the distribution.	13	# documentation and/or other materials provided with the distribution.
14	# - The name of the author may not be used to endorse or promote products	14	# - The name of the author may not be used to endorse or promote products
15	# derived from this software without specific prior written permission.	15	# derived from this software without specific prior written permission.
16	#	16	#
17	# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	#	27	#
28		28
29	## very low and hardware-level functions	29	## very low and hardware-level functions
30		30
31	# Mask for interrupts 0 - 31 (bits 0 - 31) where 0 means that int has no error	31	# Mask for interrupts 0 - 31 (bits 0 - 31) where 0 means that int has no error
32	# word and 1 means interrupt with error word	32	# word and 1 means interrupt with error word
33	#define ERROR_WORD_INTERRUPT_LIST 0x00027d00	33	#define ERROR_WORD_INTERRUPT_LIST 0x00027d00
34		34
35	.text	35	.text
36		36
37	.global paging_on	37	.global paging_on
38	.global enable_l_apic_in_msr	38	.global enable_l_apic_in_msr
39	.global interrupt_handlers	39	.global interrupt_handlers
40	.global memsetb	40	.global memsetb
41	.global memsetw	41	.global memsetw
42	.global memcpy	42	.global memcpy
43	.global memcpy_from_uspace	43	.global memcpy_from_uspace
44	.global memcpy_from_uspace_failover_address	44	.global memcpy_from_uspace_failover_address
45	.global memcpy_to_uspace	45	.global memcpy_to_uspace
46	.global memcpy_to_uspace_failover_address	46	.global memcpy_to_uspace_failover_address
47		47
48		48
49	# Wrapper for generic memsetb	49	# Wrapper for generic memsetb
50	memsetb:	50	memsetb:
51	jmp _memsetb	51	jmp _memsetb
52		52
53	# Wrapper for generic memsetw	53	# Wrapper for generic memsetw
54	memsetw:	54	memsetw:
55	jmp _memsetw	55	jmp _memsetw
56		56
57		57
58	#define MEMCPY_DST 4	58	#define MEMCPY_DST 4
59	#define MEMCPY_SRC 8	59	#define MEMCPY_SRC 8
60	#define MEMCPY_SIZE 12	60	#define MEMCPY_SIZE 12
61		61
62	/** Copy memory to/from userspace.	62	/** Copy memory to/from userspace.
63	*	63	*
64	* This is almost conventional memcpy().	64	* This is almost conventional memcpy().
65	* The difference is that there is a failover part	65	* The difference is that there is a failover part
66	* to where control is returned from a page fault	66	* to where control is returned from a page fault
67	* if the page fault occurs during copy_from_uspace()	67	* if the page fault occurs during copy_from_uspace()
68	* or copy_to_uspace().	68	* or copy_to_uspace().
69	*	69	*
70	* @param MEMCPY_DST(%esp) Destination address.	70	* @param MEMCPY_DST(%esp) Destination address.
71	* @param MEMCPY_SRC(%esp) Source address.	71	* @param MEMCPY_SRC(%esp) Source address.
72	* @param MEMCPY_SIZE(%esp) Size.	72	* @param MEMCPY_SIZE(%esp) Size.
73	*	73	*
74	* @return MEMCPY_SRC(%esp) on success and 0 on failure.	74	* @return MEMCPY_DST(%esp) on success and 0 on failure.
75	*/	75	*/
76	memcpy:	76	memcpy:
77	memcpy_from_uspace:	77	memcpy_from_uspace:
78	memcpy_to_uspace:	78	memcpy_to_uspace:
79	movl %edi, %edx /* save %edi */	79	movl %edi, %edx /* save %edi */
80	movl %esi, %eax /* save %esi */	80	movl %esi, %eax /* save %esi */
81		81
82	movl MEMCPY_SIZE(%esp), %ecx	82	movl MEMCPY_SIZE(%esp), %ecx
83	shrl $2, %ecx /* size / 4 */	83	shrl $2, %ecx /* size / 4 */
84		84
85	movl MEMCPY_DST(%esp), %edi	85	movl MEMCPY_DST(%esp), %edi
86	movl MEMCPY_SRC(%esp), %esi	86	movl MEMCPY_SRC(%esp), %esi
87		87
88	rep movsl /* copy whole words */	88	rep movsl /* copy whole words */
89		89
90	movl MEMCPY_SIZE(%esp), %ecx	90	movl MEMCPY_SIZE(%esp), %ecx
91	andl $3, %ecx /* size % 4 */	91	andl $3, %ecx /* size % 4 */
92	jz 0f	92	jz 0f
93		93
94	rep movsb /* copy the rest byte by byte */	94	rep movsb /* copy the rest byte by byte */
95		95
96	0:	96	0:
97	movl %edx, %edi	97	movl %edx, %edi
98	movl %eax, %esi	98	movl %eax, %esi
99	movl MEMCPY_SRC(%esp), %eax /* MEMCPY_SRC(%esp), success */	99	movl MEMCPY_DST(%esp), %eax /* MEMCPY_DST(%esp), success */
100	ret	100	ret
101		101
102	/*	102	/*
103	* We got here from as_page_fault() after the memory operations	103	* We got here from as_page_fault() after the memory operations
104	* above had caused a page fault.	104	* above had caused a page fault.
105	*/	105	*/
106	memcpy_from_uspace_failover_address:	106	memcpy_from_uspace_failover_address:
107	memcpy_to_uspace_failover_address:	107	memcpy_to_uspace_failover_address:
108	movl %edx, %edi	108	movl %edx, %edi
109	movl %eax, %esi	109	movl %eax, %esi
110	xorl %eax, %eax /* return 0, failure */	110	xorl %eax, %eax /* return 0, failure */
111	ret	111	ret
112		112
113	## Turn paging on	113	## Turn paging on
114	#	114	#
115	# Enable paging and write-back caching in CR0.	115	# Enable paging and write-back caching in CR0.
116	#	116	#
117	paging_on:	117	paging_on:
118	movl %cr0, %edx	118	movl %cr0, %edx
119	orl $(1 << 31), %edx # paging on	119	orl $(1 << 31), %edx # paging on
120	# clear Cache Disable and not Write Though	120	# clear Cache Disable and not Write Though
121	andl $~((1 << 30) \| (1 << 29)), %edx	121	andl $~((1 << 30) \| (1 << 29)), %edx
122	movl %edx,%cr0	122	movl %edx,%cr0
123	jmp 0f	123	jmp 0f
124	0:	124	0:
125	ret	125	ret
126		126
127		127
128	## Enable local APIC	128	## Enable local APIC
129	#	129	#
130	# Enable local APIC in MSR.	130	# Enable local APIC in MSR.
131	#	131	#
132	enable_l_apic_in_msr:	132	enable_l_apic_in_msr:
133	movl $0x1b, %ecx	133	movl $0x1b, %ecx
134	rdmsr	134	rdmsr
135	orl $(1 << 11), %eax	135	orl $(1 << 11), %eax
136	orl $(0xfee00000), %eax	136	orl $(0xfee00000), %eax
137	wrmsr	137	wrmsr
138	ret	138	ret
139		139
140	# Clear nested flag	140	# Clear nested flag
141	# overwrites %ecx	141	# overwrites %ecx
142	.macro CLEAR_NT_FLAG	142	.macro CLEAR_NT_FLAG
143	pushfl	143	pushfl
144	pop %ecx	144	pop %ecx
145	and $0xffffbfff, %ecx	145	and $0xffffbfff, %ecx
146	push %ecx	146	push %ecx
147	popfl	147	popfl
148	.endm	148	.endm
149		149
150	## Declare interrupt handlers	150	## Declare interrupt handlers
151	#	151	#
152	# Declare interrupt handlers for n interrupt	152	# Declare interrupt handlers for n interrupt
153	# vectors starting at vector i.	153	# vectors starting at vector i.
154	#	154	#
155	# The handlers setup data segment registers	155	# The handlers setup data segment registers
156	# and call exc_dispatch().	156	# and call exc_dispatch().
157	#	157	#
158	#define INTERRUPT_ALIGN 64	158	#define INTERRUPT_ALIGN 64
159	.macro handler i n	159	.macro handler i n
160		160
161	.ifeq \i - 0x30 # Syscall handler	161	.ifeq \i - 0x30 # Syscall handler
162	pushl %ds	162	pushl %ds
163	pushl %es	163	pushl %es
164	pushl %fs	164	pushl %fs
165	pushl %gs	165	pushl %gs
166		166
167	#	167	#
168	# Push syscall arguments onto the stack	168	# Push syscall arguments onto the stack
169	#	169	#
170	# NOTE: The idea behind the order of arguments passed in registers is to	170	# NOTE: The idea behind the order of arguments passed in registers is to
171	# use all scratch registers first and preserved registers next.	171	# use all scratch registers first and preserved registers next.
172	# An optimized libc syscall wrapper can make use of this setup.	172	# An optimized libc syscall wrapper can make use of this setup.
173	#	173	#
174	pushl %eax	174	pushl %eax
175	pushl %ebp	175	pushl %ebp
176	pushl %edi	176	pushl %edi
177	pushl %esi	177	pushl %esi
178	pushl %ebx	178	pushl %ebx
179	pushl %ecx	179	pushl %ecx
180	pushl %edx	180	pushl %edx
181		181
182	# we must fill the data segment registers	182	# we must fill the data segment registers
183	movw $16, %ax	183	movw $16, %ax
184	movw %ax, %ds	184	movw %ax, %ds
185	movw %ax, %es	185	movw %ax, %es
186		186
187	cld	187	cld
188	sti	188	sti
189	# syscall_handler(edx, ecx, ebx, esi, edi, ebp, eax)	189	# syscall_handler(edx, ecx, ebx, esi, edi, ebp, eax)
190	call syscall_handler	190	call syscall_handler
191	cli	191	cli
192	addl $28, %esp # clean-up of parameters	192	addl $28, %esp # clean-up of parameters
193		193
194	popl %gs	194	popl %gs
195	popl %fs	195	popl %fs
196	popl %es	196	popl %es
197	popl %ds	197	popl %ds
198		198
199	CLEAR_NT_FLAG	199	CLEAR_NT_FLAG
200	iret	200	iret
201	.else	201	.else
202	/*	202	/*
203	* This macro distinguishes between two versions of ia32 exceptions.	203	* This macro distinguishes between two versions of ia32 exceptions.
204	* One version has error word and the other does not have it.	204	* One version has error word and the other does not have it.
205	* The latter version fakes the error word on the stack so that the	205	* The latter version fakes the error word on the stack so that the
206	* handlers and istate_t can be the same for both types.	206	* handlers and istate_t can be the same for both types.
207	*/	207	*/
208	.iflt \i - 32	208	.iflt \i - 32
209	.if (1 << \i) & ERROR_WORD_INTERRUPT_LIST	209	.if (1 << \i) & ERROR_WORD_INTERRUPT_LIST
210	/*	210	/*
211	* With error word, do nothing	211	* With error word, do nothing
212	*/	212	*/
213	.else	213	.else
214	/*	214	/*
215	* Version without error word,	215	* Version without error word,
216	*/	216	*/
217	subl $4, %esp	217	subl $4, %esp
218	.endif	218	.endif
219	.else	219	.else
220	/*	220	/*
221	* Version without error word,	221	* Version without error word,
222	*/	222	*/
223	subl $4, %esp	223	subl $4, %esp
224	.endif	224	.endif
225		225
226	pushl %ds	226	pushl %ds
227	pushl %es	227	pushl %es
228	pushl %fs	228	pushl %fs
229	pushl %gs	229	pushl %gs
230		230
231	#ifdef CONFIG_DEBUG_ALLREGS	231	#ifdef CONFIG_DEBUG_ALLREGS
232	pushl %ebx	232	pushl %ebx
233	pushl %ebp	233	pushl %ebp
234	pushl %edi	234	pushl %edi
235	pushl %esi	235	pushl %esi
236	#else	236	#else
237	subl $16, %esp	237	subl $16, %esp
238	#endif	238	#endif
239	pushl %edx	239	pushl %edx
240	pushl %ecx	240	pushl %ecx
241	pushl %eax	241	pushl %eax
242		242
243	# we must fill the data segment registers	243	# we must fill the data segment registers
244	movw $16, %ax	244	movw $16, %ax
245	movw %ax, %ds	245	movw %ax, %ds
246	movw %ax, %es	246	movw %ax, %es
247		247
248	cld	248	cld
249		249
250	pushl %esp # *istate	250	pushl %esp # *istate
251	pushl $(\i) # intnum	251	pushl $(\i) # intnum
252	call exc_dispatch # excdispatch(intnum, *istate)	252	call exc_dispatch # excdispatch(intnum, *istate)
253	addl $8, %esp # Clear arguments from stack	253	addl $8, %esp # Clear arguments from stack
254		254
255	CLEAR_NT_FLAG # Modifies %ecx	255	CLEAR_NT_FLAG # Modifies %ecx
256		256
257	popl %eax	257	popl %eax
258	popl %ecx	258	popl %ecx
259	popl %edx	259	popl %edx
260	#ifdef CONFIG_DEBUG_ALLREGS	260	#ifdef CONFIG_DEBUG_ALLREGS
261	popl %esi	261	popl %esi
262	popl %edi	262	popl %edi
263	popl %ebp	263	popl %ebp
264	popl %ebx	264	popl %ebx
265	#else	265	#else
266	addl $16, %esp	266	addl $16, %esp
267	#endif	267	#endif
268		268
269	popl %gs	269	popl %gs
270	popl %fs	270	popl %fs
271	popl %es	271	popl %es
272	popl %ds	272	popl %ds
273		273
274	addl $4, %esp # Skip error word, no matter whether real or fake.	274	addl $4, %esp # Skip error word, no matter whether real or fake.
275	iret	275	iret
276	.endif	276	.endif
277		277
278	.align INTERRUPT_ALIGN	278	.align INTERRUPT_ALIGN
279	.if (\n- \i) - 1	279	.if (\n- \i) - 1
280	handler "(\i + 1)", \n	280	handler "(\i + 1)", \n
281	.endif	281	.endif
282	.endm	282	.endm
283		283
284	# keep in sync with pm.h !!!	284	# keep in sync with pm.h !!!
285	IDT_ITEMS = 64	285	IDT_ITEMS = 64
286	.align INTERRUPT_ALIGN	286	.align INTERRUPT_ALIGN
287	interrupt_handlers:	287	interrupt_handlers:
288	h_start:	288	h_start:
289	handler 0 IDT_ITEMS	289	handler 0 IDT_ITEMS
290	h_end:	290	h_end:
291		291
292	.data	292	.data
293	.global interrupt_handler_size	293	.global interrupt_handler_size
294		294
295	interrupt_handler_size: .long (h_end - h_start) / IDT_ITEMS	295	interrupt_handler_size: .long (h_end - h_start) / IDT_ITEMS
296		296

Subversion Repositories HelenOS

(root)/trunk/kernel/arch/ia32/src/asm.S – Rev 3043 → 3274