WebSVN – HelenOS – Diff – /trunk/kernel/arch/ia32/src/asm.S


#
# Copyright (c) 2001-2004 Jakub Jermar
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# - Redistributions of source code must retain the above copyright
#   notice, this list of conditions and the following disclaimer.
# - Redistributions in binary form must reproduce the above copyright
#   notice, this list of conditions and the following disclaimer in the
#   documentation and/or other materials provided with the distribution.
# - The name of the author may not be used to endorse or promote products
#   derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
 
## very low and hardware-level functions
 
# Mask for interrupts 0 - 31 (bits 0 - 31) where 0 means that int has no error word
# and 1 means interrupt with error word
#define ERROR_WORD_INTERRUPT_LIST 0x00027D00
 
.text
 
.global paging_on
.global enable_l_apic_in_msr
.global interrupt_handlers
.global memcpy
.global memcpy_from_uspace
.global memcpy_from_uspace_failover_address
.global memcpy_to_uspace
.global memcpy_to_uspace_failover_address
 
 
#define MEMCPY_DST	4
#define MEMCPY_SRC	8
#define MEMCPY_SIZE	12
 
/** Copy memory to/from userspace.
 *
 * This is almost conventional memcpy().
 * The difference is that there is a failover part
 * to where control is returned from a page fault
 * if the page fault occurs during copy_from_uspace()
 * or copy_to_uspace().
 *
 * @param MEMCPY_DST(%esp)	Destination address.
 * @param MEMCPY_SRC(%esp)	Source address.
 * @param MEMCPY_SIZE(%esp)	Size.
 *
 * @return MEMCPY_SRC(%esp) on success and 0 on failure.
 */
memcpy:
memcpy_from_uspace:
memcpy_to_uspace:
	movl %edi, %edx				/* save %edi */
	movl %esi, %eax				/* save %esi */
	
	movl MEMCPY_SIZE(%esp), %ecx
	shrl $2, %ecx				/* size / 4 */
	
	movl MEMCPY_DST(%esp), %edi
	movl MEMCPY_SRC(%esp), %esi
	
	rep movsl				/* copy as much as possible word by word */
 
	movl MEMCPY_SIZE(%esp), %ecx
	andl $3, %ecx				/* size % 4 */
	jz 0f
	
	rep movsb				/* copy the rest byte by byte */
 
0:
	movl %edx, %edi
	movl %eax, %esi
	movl MEMCPY_SRC(%esp), %eax		/* MEMCPY_SRC(%esp), success */
	ret
	
/*
 * We got here from as_page_fault() after the memory operations
 * above had caused a page fault.
 */
memcpy_from_uspace_failover_address:
memcpy_to_uspace_failover_address:
	movl %edx, %edi
	movl %eax, %esi
	xorl %eax, %eax				/* return 0, failure */
	ret
 
## Turn paging on
#
# Enable paging and write-back caching in CR0.
#
paging_on:
	movl %cr0,%edx
	orl $(1<<31),%edx		# paging on
	andl $~((1<<30)|(1<<29)),%edx	# clear Cache Disable and not Write Though
	movl %edx,%cr0
	jmp 0f
0:
	ret
 
 
## Enable local APIC
#
# Enable local APIC in MSR.
#
enable_l_apic_in_msr:
	push %eax
 
	movl $0x1b, %ecx
	rdmsr
	orl $(1<<11),%eax
	orl $(0xfee00000),%eax
	wrmsr
 
	pop %eax
	ret
 
# Clear nested flag
# overwrites %ecx
.macro CLEAR_NT_FLAG
	pushfl
	pop %ecx
	and $0xffffbfff,%ecx
	push %ecx
	popfl
.endm	
 
## Declare interrupt handlers
#
# Declare interrupt handlers for n interrupt
# vectors starting at vector i.
#
# The handlers setup data segment registers
# and call exc_dispatch().
#
#define INTERRUPT_ALIGN 64
.macro handler i n
 
.ifeq \i-0x30     # Syscall handler
	push %ds
	push %es
	push %fs
	push %gs
 
	# Push arguments on stack
	push %edi
	push %esi
	push %edx
	push %ecx
	push %eax
	
	# we must fill the data segment registers
	movw $16,%ax
	movw %ax,%ds
	movw %ax,%es
	
	sti
	
	call syscall_handler   # syscall_handler(ax,cx,dx,si,di)
	cli
	addl $20, %esp         # clean-up of parameters
	
	pop %gs
	pop %fs
	pop %es
	pop %ds
	
	CLEAR_NT_FLAG
	iret
.else	
	/*
	 * This macro distinguishes between two versions of ia32 exceptions.
	 * One version has error word and the other does not have it.
	 * The latter version fakes the error word on the stack so that the
	 * handlers and istate_t can be the same for both types.
	 */
	.iflt \i-32
		.if (1 << \i) & ERROR_WORD_INTERRUPT_LIST
			/* 
			 * With error word, do nothing
			 */
                .else
                        /*
                         * Version without error word,
                         */
			subl $4, %esp
                .endif
        .else
                /*
                 * Version without error word,
                 */
		subl $4, %esp
	.endif
	
	push %ds
	push %es
	push %fs
	push %gs
 
#ifdef CONFIG_DEBUG_ALLREGS
	push %ebx
	push %ebp
	push %edi
	push %esi
#else
	sub $16, %esp
#endif
	push %edx
	push %ecx
	push %eax
	
	# we must fill the data segment registers
	movw $16,%ax
	movw %ax,%ds
	movw %ax,%es
 
	pushl %esp          # *istate
	pushl $(\i)         # intnum
	call exc_dispatch   # excdispatch(intnum, *istate)
	addl $8,%esp        # Clear arguments from stack
 
	CLEAR_NT_FLAG # Modifies %ecx
	
	pop %eax
	pop %ecx
	pop %edx
#ifdef CONFIG_DEBUG_ALLREGS
	pop %esi
	pop %edi
	pop %ebp
	pop %ebx
#else
	add $16, %esp
#endif	
	
	pop %gs
	pop %fs
	pop %es
	pop %ds
 
	addl $4,%esp	# Skip error word, no matter whether real or fake.
	iret
.endif
 
	.align INTERRUPT_ALIGN
	.if (\n-\i)-1
	handler "(\i+1)",\n
	.endif
.endm
 
# keep in sync with pm.h !!!
IDT_ITEMS=64
.align INTERRUPT_ALIGN
interrupt_handlers:
h_start:
	handler 0 IDT_ITEMS
h_end:
 
.data
.global interrupt_handler_size
 
interrupt_handler_size: .long (h_end-h_start)/IDT_ITEMS
 

Rev 1787	Rev 2071
1	#	1	#
2	# Copyright (C) 2001-2004 Jakub Jermar	2	# Copyright (c) 2001-2004 Jakub Jermar
3	# All rights reserved.	3	# All rights reserved.
4	#	4	#
5	# Redistribution and use in source and binary forms, with or without	5	# Redistribution and use in source and binary forms, with or without
6	# modification, are permitted provided that the following conditions	6	# modification, are permitted provided that the following conditions
7	# are met:	7	# are met:
8	#	8	#
9	# - Redistributions of source code must retain the above copyright	9	# - Redistributions of source code must retain the above copyright
10	# notice, this list of conditions and the following disclaimer.	10	# notice, this list of conditions and the following disclaimer.
11	# - Redistributions in binary form must reproduce the above copyright	11	# - Redistributions in binary form must reproduce the above copyright
12	# notice, this list of conditions and the following disclaimer in the	12	# notice, this list of conditions and the following disclaimer in the
13	# documentation and/or other materials provided with the distribution.	13	# documentation and/or other materials provided with the distribution.
14	# - The name of the author may not be used to endorse or promote products	14	# - The name of the author may not be used to endorse or promote products
15	# derived from this software without specific prior written permission.	15	# derived from this software without specific prior written permission.
16	#	16	#
17	# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	#	27	#
28		28
29	## very low and hardware-level functions	29	## very low and hardware-level functions
30		30
31	# Mask for interrupts 0 - 31 (bits 0 - 31) where 0 means that int has no error word	31	# Mask for interrupts 0 - 31 (bits 0 - 31) where 0 means that int has no error word
32	# and 1 means interrupt with error word	32	# and 1 means interrupt with error word
33	#define ERROR_WORD_INTERRUPT_LIST 0x00027D00	33	#define ERROR_WORD_INTERRUPT_LIST 0x00027D00
34		34
35	.text	35	.text
36		36
37	.global paging_on	37	.global paging_on
38	.global enable_l_apic_in_msr	38	.global enable_l_apic_in_msr
39	.global interrupt_handlers	39	.global interrupt_handlers
40	.global memcpy	40	.global memcpy
41	.global memcpy_from_uspace	41	.global memcpy_from_uspace
42	.global memcpy_from_uspace_failover_address	42	.global memcpy_from_uspace_failover_address
43	.global memcpy_to_uspace	43	.global memcpy_to_uspace
44	.global memcpy_to_uspace_failover_address	44	.global memcpy_to_uspace_failover_address
45		45
46		46
47	#define MEMCPY_DST 4	47	#define MEMCPY_DST 4
48	#define MEMCPY_SRC 8	48	#define MEMCPY_SRC 8
49	#define MEMCPY_SIZE 12	49	#define MEMCPY_SIZE 12
50		50
51	/** Copy memory to/from userspace.	51	/** Copy memory to/from userspace.
52	*	52	*
53	* This is almost conventional memcpy().	53	* This is almost conventional memcpy().
54	* The difference is that there is a failover part	54	* The difference is that there is a failover part
55	* to where control is returned from a page fault	55	* to where control is returned from a page fault
56	* if the page fault occurs during copy_from_uspace()	56	* if the page fault occurs during copy_from_uspace()
57	* or copy_to_uspace().	57	* or copy_to_uspace().
58	*	58	*
59	* @param MEMCPY_DST(%esp) Destination address.	59	* @param MEMCPY_DST(%esp) Destination address.
60	* @param MEMCPY_SRC(%esp) Source address.	60	* @param MEMCPY_SRC(%esp) Source address.
61	* @param MEMCPY_SIZE(%esp) Size.	61	* @param MEMCPY_SIZE(%esp) Size.
62	*	62	*
63	* @return MEMCPY_SRC(%esp) on success and 0 on failure.	63	* @return MEMCPY_SRC(%esp) on success and 0 on failure.
64	*/	64	*/
65	memcpy:	65	memcpy:
66	memcpy_from_uspace:	66	memcpy_from_uspace:
67	memcpy_to_uspace:	67	memcpy_to_uspace:
68	movl %edi, %edx /* save %edi */	68	movl %edi, %edx /* save %edi */
69	movl %esi, %eax /* save %esi */	69	movl %esi, %eax /* save %esi */
70		70
71	movl MEMCPY_SIZE(%esp), %ecx	71	movl MEMCPY_SIZE(%esp), %ecx
72	shrl $2, %ecx /* size / 4 */	72	shrl $2, %ecx /* size / 4 */
73		73
74	movl MEMCPY_DST(%esp), %edi	74	movl MEMCPY_DST(%esp), %edi
75	movl MEMCPY_SRC(%esp), %esi	75	movl MEMCPY_SRC(%esp), %esi
76		76
77	rep movsl /* copy as much as possible word by word */	77	rep movsl /* copy as much as possible word by word */
78		78
79	movl MEMCPY_SIZE(%esp), %ecx	79	movl MEMCPY_SIZE(%esp), %ecx
80	andl $3, %ecx /* size % 4 */	80	andl $3, %ecx /* size % 4 */
81	jz 0f	81	jz 0f
82		82
83	rep movsb /* copy the rest byte by byte */	83	rep movsb /* copy the rest byte by byte */
84		84
85	0:	85	0:
86	movl %edx, %edi	86	movl %edx, %edi
87	movl %eax, %esi	87	movl %eax, %esi
88	movl MEMCPY_SRC(%esp), %eax /* MEMCPY_SRC(%esp), success */	88	movl MEMCPY_SRC(%esp), %eax /* MEMCPY_SRC(%esp), success */
89	ret	89	ret
90		90
91	/*	91	/*
92	* We got here from as_page_fault() after the memory operations	92	* We got here from as_page_fault() after the memory operations
93	* above had caused a page fault.	93	* above had caused a page fault.
94	*/	94	*/
95	memcpy_from_uspace_failover_address:	95	memcpy_from_uspace_failover_address:
96	memcpy_to_uspace_failover_address:	96	memcpy_to_uspace_failover_address:
97	movl %edx, %edi	97	movl %edx, %edi
98	movl %eax, %esi	98	movl %eax, %esi
99	xorl %eax, %eax /* return 0, failure */	99	xorl %eax, %eax /* return 0, failure */
100	ret	100	ret
101		101
102	## Turn paging on	102	## Turn paging on
103	#	103	#
104	# Enable paging and write-back caching in CR0.	104	# Enable paging and write-back caching in CR0.
105	#	105	#
106	paging_on:	106	paging_on:
107	movl %cr0,%edx	107	movl %cr0,%edx
108	orl $(1<<31),%edx # paging on	108	orl $(1<<31),%edx # paging on
109	andl $~((1<<30)\|(1<<29)),%edx # clear Cache Disable and not Write Though	109	andl $~((1<<30)\|(1<<29)),%edx # clear Cache Disable and not Write Though
110	movl %edx,%cr0	110	movl %edx,%cr0
111	jmp 0f	111	jmp 0f
112	0:	112	0:
113	ret	113	ret
114		114
115		115
116	## Enable local APIC	116	## Enable local APIC
117	#	117	#
118	# Enable local APIC in MSR.	118	# Enable local APIC in MSR.
119	#	119	#
120	enable_l_apic_in_msr:	120	enable_l_apic_in_msr:
121	push %eax	121	push %eax
122		122
123	movl $0x1b, %ecx	123	movl $0x1b, %ecx
124	rdmsr	124	rdmsr
125	orl $(1<<11),%eax	125	orl $(1<<11),%eax
126	orl $(0xfee00000),%eax	126	orl $(0xfee00000),%eax
127	wrmsr	127	wrmsr
128		128
129	pop %eax	129	pop %eax
130	ret	130	ret
131		131
132	# Clear nested flag	132	# Clear nested flag
133	# overwrites %ecx	133	# overwrites %ecx
134	.macro CLEAR_NT_FLAG	134	.macro CLEAR_NT_FLAG
135	pushfl	135	pushfl
136	pop %ecx	136	pop %ecx
137	and $0xffffbfff,%ecx	137	and $0xffffbfff,%ecx
138	push %ecx	138	push %ecx
139	popfl	139	popfl
140	.endm	140	.endm
141		141
142	## Declare interrupt handlers	142	## Declare interrupt handlers
143	#	143	#
144	# Declare interrupt handlers for n interrupt	144	# Declare interrupt handlers for n interrupt
145	# vectors starting at vector i.	145	# vectors starting at vector i.
146	#	146	#
147	# The handlers setup data segment registers	147	# The handlers setup data segment registers
148	# and call exc_dispatch().	148	# and call exc_dispatch().
149	#	149	#
150	#define INTERRUPT_ALIGN 64	150	#define INTERRUPT_ALIGN 64
151	.macro handler i n	151	.macro handler i n
152		152
153	.ifeq \i-0x30 # Syscall handler	153	.ifeq \i-0x30 # Syscall handler
154	push %ds	154	push %ds
155	push %es	155	push %es
156	push %fs	156	push %fs
157	push %gs	157	push %gs
158		158
159	# Push arguments on stack	159	# Push arguments on stack
160	push %edi	160	push %edi
161	push %esi	161	push %esi
162	push %edx	162	push %edx
163	push %ecx	163	push %ecx
164	push %eax	164	push %eax
165		165
166	# we must fill the data segment registers	166	# we must fill the data segment registers
167	movw $16,%ax	167	movw $16,%ax
168	movw %ax,%ds	168	movw %ax,%ds
169	movw %ax,%es	169	movw %ax,%es
170		170
171	sti	171	sti
172		172
173	call syscall_handler # syscall_handler(ax,cx,dx,si,di)	173	call syscall_handler # syscall_handler(ax,cx,dx,si,di)
174	cli	174	cli
175	addl $20, %esp # clean-up of parameters	175	addl $20, %esp # clean-up of parameters
176		176
177	pop %gs	177	pop %gs
178	pop %fs	178	pop %fs
179	pop %es	179	pop %es
180	pop %ds	180	pop %ds
181		181
182	CLEAR_NT_FLAG	182	CLEAR_NT_FLAG
183	iret	183	iret
184	.else	184	.else
185	/*	185	/*
186	* This macro distinguishes between two versions of ia32 exceptions.	186	* This macro distinguishes between two versions of ia32 exceptions.
187	* One version has error word and the other does not have it.	187	* One version has error word and the other does not have it.
188	* The latter version fakes the error word on the stack so that the	188	* The latter version fakes the error word on the stack so that the
189	* handlers and istate_t can be the same for both types.	189	* handlers and istate_t can be the same for both types.
190	*/	190	*/
191	.iflt \i-32	191	.iflt \i-32
192	.if (1 << \i) & ERROR_WORD_INTERRUPT_LIST	192	.if (1 << \i) & ERROR_WORD_INTERRUPT_LIST
193	/*	193	/*
194	* With error word, do nothing	194	* With error word, do nothing
195	*/	195	*/
196	.else	196	.else
197	/*	197	/*
198	* Version without error word,	198	* Version without error word,
199	*/	199	*/
200	subl $4, %esp	200	subl $4, %esp
201	.endif	201	.endif
202	.else	202	.else
203	/*	203	/*
204	* Version without error word,	204	* Version without error word,
205	*/	205	*/
206	subl $4, %esp	206	subl $4, %esp
207	.endif	207	.endif
208		208
209	push %ds	209	push %ds
210	push %es	210	push %es
211	push %fs	211	push %fs
212	push %gs	212	push %gs
213		213
214	#ifdef CONFIG_DEBUG_ALLREGS	214	#ifdef CONFIG_DEBUG_ALLREGS
215	push %ebx	215	push %ebx
216	push %ebp	216	push %ebp
217	push %edi	217	push %edi
218	push %esi	218	push %esi
219	#else	219	#else
220	sub $16, %esp	220	sub $16, %esp
221	#endif	221	#endif
222	push %edx	222	push %edx
223	push %ecx	223	push %ecx
224	push %eax	224	push %eax
225		225
226	# we must fill the data segment registers	226	# we must fill the data segment registers
227	movw $16,%ax	227	movw $16,%ax
228	movw %ax,%ds	228	movw %ax,%ds
229	movw %ax,%es	229	movw %ax,%es
230		230
231	pushl %esp # *istate	231	pushl %esp # *istate
232	pushl $(\i) # intnum	232	pushl $(\i) # intnum
233	call exc_dispatch # excdispatch(intnum, *istate)	233	call exc_dispatch # excdispatch(intnum, *istate)
234	addl $8,%esp # Clear arguments from stack	234	addl $8,%esp # Clear arguments from stack
235		235
236	CLEAR_NT_FLAG # Modifies %ecx	236	CLEAR_NT_FLAG # Modifies %ecx
237		237
238	pop %eax	238	pop %eax
239	pop %ecx	239	pop %ecx
240	pop %edx	240	pop %edx
241	#ifdef CONFIG_DEBUG_ALLREGS	241	#ifdef CONFIG_DEBUG_ALLREGS
242	pop %esi	242	pop %esi
243	pop %edi	243	pop %edi
244	pop %ebp	244	pop %ebp
245	pop %ebx	245	pop %ebx
246	#else	246	#else
247	add $16, %esp	247	add $16, %esp
248	#endif	248	#endif
249		249
250	pop %gs	250	pop %gs
251	pop %fs	251	pop %fs
252	pop %es	252	pop %es
253	pop %ds	253	pop %ds
254		254
255	addl $4,%esp # Skip error word, no matter whether real or fake.	255	addl $4,%esp # Skip error word, no matter whether real or fake.
256	iret	256	iret
257	.endif	257	.endif
258		258
259	.align INTERRUPT_ALIGN	259	.align INTERRUPT_ALIGN
260	.if (\n-\i)-1	260	.if (\n-\i)-1
261	handler "(\i+1)",\n	261	handler "(\i+1)",\n
262	.endif	262	.endif
263	.endm	263	.endm
264		264
265	# keep in sync with pm.h !!!	265	# keep in sync with pm.h !!!
266	IDT_ITEMS=64	266	IDT_ITEMS=64
267	.align INTERRUPT_ALIGN	267	.align INTERRUPT_ALIGN
268	interrupt_handlers:	268	interrupt_handlers:
269	h_start:	269	h_start:
270	handler 0 IDT_ITEMS	270	handler 0 IDT_ITEMS
271	h_end:	271	h_end:
272		272
273	.data	273	.data
274	.global interrupt_handler_size	274	.global interrupt_handler_size
275		275
276	interrupt_handler_size: .long (h_end-h_start)/IDT_ITEMS	276	interrupt_handler_size: .long (h_end-h_start)/IDT_ITEMS
277		277

Subversion Repositories HelenOS

(root)/trunk/kernel/arch/ia32/src/asm.S – Rev 1787 → 2071