WebSVN – HelenOS – Diff – /trunk/kernel/arch/ia32/include/smp/apic.h


/*
 * Copyright (c) 2001-2004 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup ia32   
 * @{
 */
/** @file
 */
 
#ifndef KERN_ia32_APIC_H_
#define KERN_ia32_APIC_H_
 
#include <arch/types.h>
#include <cpu.h>
 
#define FIXED       (0<<0)
#define LOPRI       (1<<0)
 
#define APIC_ID_COUNT   16
 
/* local APIC macros */
#define IPI_INIT    0
#define IPI_STARTUP 0
 
/** Delivery modes. */
#define DELMOD_FIXED    0x0
#define DELMOD_LOWPRI   0x1
#define DELMOD_SMI  0x2
/* 0x3 reserved */
#define DELMOD_NMI  0x4
#define DELMOD_INIT 0x5
#define DELMOD_STARTUP  0x6
#define DELMOD_EXTINT   0x7
 
/** Destination modes. */
#define DESTMOD_PHYS    0x0
#define DESTMOD_LOGIC   0x1
 
/** Trigger Modes. */
#define TRIGMOD_EDGE    0x0
#define TRIGMOD_LEVEL   0x1
 
/** Levels. */
#define LEVEL_DEASSERT  0x0
#define LEVEL_ASSERT    0x1
 
/** Destination Shorthands. */
#define SHORTHAND_NONE      0x0
#define SHORTHAND_SELF      0x1
#define SHORTHAND_ALL_INCL  0x2
#define SHORTHAND_ALL_EXCL  0x3
 
/** Interrupt Input Pin Polarities. */
#define POLARITY_HIGH   0x0
#define POLARITY_LOW    0x1
 
/** Divide Values. (Bit 2 is always 0) */
#define DIVIDE_2    0x0
#define DIVIDE_4    0x1
#define DIVIDE_8    0x2
#define DIVIDE_16   0x3
#define DIVIDE_32   0x8
#define DIVIDE_64   0x9
#define DIVIDE_128  0xa
#define DIVIDE_1    0xb
 
/** Timer Modes. */
#define TIMER_ONESHOT   0x0
#define TIMER_PERIODIC  0x1
 
/** Delivery status. */
#define DELIVS_IDLE 0x0
#define DELIVS_PENDING  0x1
 
/** Destination masks. */
#define DEST_ALL    0xff
 
/** Dest format models. */
#define MODEL_FLAT  0xf
#define MODEL_CLUSTER   0x0
 
/** Interrupt Command Register. */
#define ICRlo       (0x300 / sizeof(uint32_t))
#define ICRhi       (0x310 / sizeof(uint32_t))
typedef struct {
    union {
        uint32_t lo;
        struct {
            uint8_t vector;         /**< Interrupt Vector. */
            unsigned delmod : 3;        /**< Delivery Mode. */
            unsigned destmod : 1;       /**< Destination Mode. */
            unsigned delivs : 1;        /**< Delivery status (RO). */
            unsigned : 1;           /**< Reserved. */
            unsigned level : 1;     /**< Level. */
            unsigned trigger_mode : 1;  /**< Trigger Mode. */
            unsigned : 2;           /**< Reserved. */
            unsigned shorthand : 2;     /**< Destination Shorthand. */
            unsigned : 12;          /**< Reserved. */
        } __attribute__ ((packed));
    };
    union {
        uint32_t hi;
        struct {
            unsigned : 24;          /**< Reserved. */
            uint8_t dest;           /**< Destination field. */
        } __attribute__ ((packed));
    };
} __attribute__ ((packed)) icr_t;
 
/* End Of Interrupt. */
#define EOI     (0x0b0 / sizeof(uint32_t))
 
/** Error Status Register. */
#define ESR     (0x280 / sizeof(uint32_t))
typedef union {
    uint32_t value;
    uint8_t err_bitmap;
    struct {
        unsigned send_checksum_error : 1;
        unsigned receive_checksum_error : 1;
        unsigned send_accept_error : 1;
        unsigned receive_accept_error : 1;
        unsigned : 1;
        unsigned send_illegal_vector : 1;
        unsigned received_illegal_vector : 1;
        unsigned illegal_register_address : 1;
        unsigned : 24;
    } __attribute__ ((packed));
} esr_t;
 
/* Task Priority Register */
#define TPR     (0x080 / sizeof(uint32_t))
typedef union {
    uint32_t value;
    struct {
        unsigned pri_sc : 4;        /**< Task Priority Sub-Class. */
        unsigned pri : 4;       /**< Task Priority. */
    } __attribute__ ((packed));
} tpr_t;
 
/** Spurious-Interrupt Vector Register. */
#define SVR     (0x0f0 / sizeof(uint32_t))
typedef union {
    uint32_t value;
    struct {
        uint8_t vector;         /**< Spurious Vector. */
        unsigned lapic_enabled : 1; /**< APIC Software Enable/Disable. */
        unsigned focus_checking : 1;    /**< Focus Processor Checking. */
        unsigned : 22;          /**< Reserved. */
    } __attribute__ ((packed));
} svr_t;
 
/** Time Divide Configuration Register. */
#define TDCR        (0x3e0 / sizeof(uint32_t))
typedef union {
    uint32_t value;
    struct {
        unsigned div_value : 4;     /**< Divide Value, bit 2 is always 0. */
        unsigned : 28;          /**< Reserved. */
    } __attribute__ ((packed));
} tdcr_t;
 
/* Initial Count Register for Timer */
#define ICRT        (0x380 / sizeof(uint32_t))
 
/* Current Count Register for Timer */
#define CCRT        (0x390 / sizeof(uint32_t))
 
/** LVT Timer register. */
#define LVT_Tm      (0x320 / sizeof(uint32_t))
typedef union {
    uint32_t value;
    struct {
        uint8_t vector;     /**< Local Timer Interrupt vector. */
        unsigned : 4;       /**< Reserved. */
        unsigned delivs : 1;    /**< Delivery status (RO). */
        unsigned : 3;       /**< Reserved. */
        unsigned masked : 1;    /**< Interrupt Mask. */
        unsigned mode : 1;  /**< Timer Mode. */
        unsigned : 14;      /**< Reserved. */
    } __attribute__ ((packed));
} lvt_tm_t;
 
/** LVT LINT registers. */
#define LVT_LINT0   (0x350 / sizeof(uint32_t))
#define LVT_LINT1   (0x360 / sizeof(uint32_t))
typedef union {
    uint32_t value;
    struct {
        uint8_t vector;         /**< LINT Interrupt vector. */
        unsigned delmod : 3;        /**< Delivery Mode. */
        unsigned : 1;           /**< Reserved. */
        unsigned delivs : 1;        /**< Delivery status (RO). */
        unsigned intpol : 1;        /**< Interrupt Input Pin Polarity. */
        unsigned irr : 1;       /**< Remote IRR (RO). */
        unsigned trigger_mode : 1;  /**< Trigger Mode. */
        unsigned masked : 1;        /**< Interrupt Mask. */
        unsigned : 15;          /**< Reserved. */
    } __attribute__ ((packed));
} lvt_lint_t;
 
/** LVT Error register. */
#define LVT_Err     (0x370 / sizeof(uint32_t))
typedef union {
    uint32_t value;
    struct {
        uint8_t vector;     /**< Local Timer Interrupt vector. */
        unsigned : 4;       /**< Reserved. */
        unsigned delivs : 1;    /**< Delivery status (RO). */
        unsigned : 3;       /**< Reserved. */
        unsigned masked : 1;    /**< Interrupt Mask. */
        unsigned : 15;      /**< Reserved. */
    } __attribute__ ((packed));
} lvt_error_t;
 
/** Local APIC ID Register. */
#define L_APIC_ID   (0x020 / sizeof(uint32_t))
typedef union {
    uint32_t value;
    struct {
        unsigned : 24;      /**< Reserved. */
        uint8_t apic_id;        /**< Local APIC ID. */
    } __attribute__ ((packed));
} l_apic_id_t;
 
/** Local APIC Version Register */
#define LAVR        (0x030 / sizeof(uint32_t))
#define LAVR_Mask   0xff
#define is_local_apic(x)    (((x) & LAVR_Mask & 0xf0) == 0x1)
#define is_82489DX_apic(x)  ((((x) & LAVR_Mask & 0xf0) == 0x0))
#define is_local_xapic(x)   (((x) & LAVR_Mask) == 0x14)
 
/** Logical Destination Register. */
#define  LDR        (0x0d0 / sizeof(uint32_t))
typedef union {
    uint32_t value;
    struct {
        unsigned : 24;      /**< Reserved. */
        uint8_t id;     /**< Logical APIC ID. */
    } __attribute__ ((packed));
} ldr_t;
 
/** Destination Format Register. */
#define DFR     (0x0e0 / sizeof(uint32_t))
typedef union {
    uint32_t value;
    struct {
        unsigned : 28;      /**< Reserved, all ones. */
        unsigned model : 4; /**< Model. */
    } __attribute__ ((packed));
} dfr_t;
 
/* IO APIC */
#define IOREGSEL    (0x00 / sizeof(uint32_t))
#define IOWIN       (0x10 / sizeof(uint32_t))
 
#define IOAPICID    0x00
#define IOAPICVER   0x01
#define IOAPICARB   0x02
#define IOREDTBL    0x10
 
/** I/O Register Select Register. */
typedef union {
    uint32_t value;
    struct {
        uint8_t reg_addr;       /**< APIC Register Address. */
        unsigned : 24;      /**< Reserved. */
    } __attribute__ ((packed));
} io_regsel_t;
 
/** I/O Redirection Register. */
typedef struct io_redirection_reg {
    union {
        uint32_t lo;
        struct {
            uint8_t intvec;         /**< Interrupt Vector. */
            unsigned delmod : 3;        /**< Delivery Mode. */
            unsigned destmod : 1;       /**< Destination mode. */
            unsigned delivs : 1;        /**< Delivery status (RO). */
            unsigned intpol : 1;        /**< Interrupt Input Pin Polarity. */
            unsigned irr : 1;       /**< Remote IRR (RO). */
            unsigned trigger_mode : 1;  /**< Trigger Mode. */
            unsigned masked : 1;        /**< Interrupt Mask. */
            unsigned : 15;          /**< Reserved. */
        } __attribute__ ((packed));
    };
    union {
        uint32_t hi;
        struct {
            unsigned : 24;          /**< Reserved. */
            uint8_t dest : 8;           /**< Destination Field. */
        } __attribute__ ((packed));
    };
   
} __attribute__ ((packed)) io_redirection_reg_t;
 
 
/** IO APIC Identification Register. */
typedef union {
    uint32_t value;
    struct {
        unsigned : 24;      /**< Reserved. */
        unsigned apic_id : 4;   /**< IO APIC ID. */
        unsigned : 4;       /**< Reserved. */
    } __attribute__ ((packed));
} io_apic_id_t;
 
extern volatile uint32_t *l_apic;
extern volatile uint32_t *io_apic;
 
extern uint32_t apic_id_mask;
 
extern void apic_init(void);
 
extern void l_apic_init(void);
extern void l_apic_eoi(void);
extern int l_apic_broadcast_custom_ipi(uint8_t vector);
extern int l_apic_send_init_ipi(uint8_t apicid);
extern void l_apic_debug(void);
extern uint8_t l_apic_id(void);
 
extern uint32_t io_apic_read(uint8_t address);
extern void io_apic_write(uint8_t address , uint32_t x);
extern void io_apic_change_ioredtbl(uint8_t pin, uint8_t dest, uint8_t v, int flags);
extern void io_apic_disable_irqs(uint16_t irqmask);
extern void io_apic_enable_irqs(uint16_t irqmask);
 
#endif
 
/** @}
 */
 

Rev 2441	Rev 3071
1	/*	1	/*
2	* Copyright (c) 2001-2004 Jakub Jermar	2	* Copyright (c) 2001-2004 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	/** @addtogroup ia32	29	/** @addtogroup ia32
30	* @{	30	* @{
31	*/	31	*/
32	/** @file	32	/** @file
33	*/	33	*/
34		34
35	#ifndef KERN_ia32_APIC_H_	35	#ifndef KERN_ia32_APIC_H_
36	#define KERN_ia32_APIC_H_	36	#define KERN_ia32_APIC_H_
37		37
38	#include <arch/types.h>	38	#include <arch/types.h>
39	#include <cpu.h>	39	#include <cpu.h>
40		40
41	#define FIXED (0<<0)	41	#define FIXED (0<<0)
42	#define LOPRI (1<<0)	42	#define LOPRI (1<<0)
43		43
44	#define APIC_ID_COUNT 16	44	#define APIC_ID_COUNT 16
45		45
46	/* local APIC macros */	46	/* local APIC macros */
47	#define IPI_INIT 0	47	#define IPI_INIT 0
48	#define IPI_STARTUP 0	48	#define IPI_STARTUP 0
49		49
50	/** Delivery modes. */	50	/** Delivery modes. */
51	#define DELMOD_FIXED 0x0	51	#define DELMOD_FIXED 0x0
52	#define DELMOD_LOWPRI 0x1	52	#define DELMOD_LOWPRI 0x1
53	#define DELMOD_SMI 0x2	53	#define DELMOD_SMI 0x2
54	/* 0x3 reserved */	54	/* 0x3 reserved */
55	#define DELMOD_NMI 0x4	55	#define DELMOD_NMI 0x4
56	#define DELMOD_INIT 0x5	56	#define DELMOD_INIT 0x5
57	#define DELMOD_STARTUP 0x6	57	#define DELMOD_STARTUP 0x6
58	#define DELMOD_EXTINT 0x7	58	#define DELMOD_EXTINT 0x7
59		59
60	/** Destination modes. */	60	/** Destination modes. */
61	#define DESTMOD_PHYS 0x0	61	#define DESTMOD_PHYS 0x0
62	#define DESTMOD_LOGIC 0x1	62	#define DESTMOD_LOGIC 0x1
63		63
64	/** Trigger Modes. */	64	/** Trigger Modes. */
65	#define TRIGMOD_EDGE 0x0	65	#define TRIGMOD_EDGE 0x0
66	#define TRIGMOD_LEVEL 0x1	66	#define TRIGMOD_LEVEL 0x1
67		67
68	/** Levels. */	68	/** Levels. */
69	#define LEVEL_DEASSERT 0x0	69	#define LEVEL_DEASSERT 0x0
70	#define LEVEL_ASSERT 0x1	70	#define LEVEL_ASSERT 0x1
71		71
72	/** Destination Shorthands. */	72	/** Destination Shorthands. */
73	#define SHORTHAND_NONE 0x0	73	#define SHORTHAND_NONE 0x0
74	#define SHORTHAND_SELF 0x1	74	#define SHORTHAND_SELF 0x1
75	#define SHORTHAND_ALL_INCL 0x2	75	#define SHORTHAND_ALL_INCL 0x2
76	#define SHORTHAND_ALL_EXCL 0x3	76	#define SHORTHAND_ALL_EXCL 0x3
77		77
78	/** Interrupt Input Pin Polarities. */	78	/** Interrupt Input Pin Polarities. */
79	#define POLARITY_HIGH 0x0	79	#define POLARITY_HIGH 0x0
80	#define POLARITY_LOW 0x1	80	#define POLARITY_LOW 0x1
81		81
82	/** Divide Values. (Bit 2 is always 0) */	82	/** Divide Values. (Bit 2 is always 0) */
83	#define DIVIDE_2 0x0	83	#define DIVIDE_2 0x0
84	#define DIVIDE_4 0x1	84	#define DIVIDE_4 0x1
85	#define DIVIDE_8 0x2	85	#define DIVIDE_8 0x2
86	#define DIVIDE_16 0x3	86	#define DIVIDE_16 0x3
87	#define DIVIDE_32 0x8	87	#define DIVIDE_32 0x8
88	#define DIVIDE_64 0x9	88	#define DIVIDE_64 0x9
89	#define DIVIDE_128 0xa	89	#define DIVIDE_128 0xa
90	#define DIVIDE_1 0xb	90	#define DIVIDE_1 0xb
91		91
92	/** Timer Modes. */	92	/** Timer Modes. */
93	#define TIMER_ONESHOT 0x0	93	#define TIMER_ONESHOT 0x0
94	#define TIMER_PERIODIC 0x1	94	#define TIMER_PERIODIC 0x1
95		95
96	/** Delivery status. */	96	/** Delivery status. */
97	#define DELIVS_IDLE 0x0	97	#define DELIVS_IDLE 0x0
98	#define DELIVS_PENDING 0x1	98	#define DELIVS_PENDING 0x1
99		99
100	/** Destination masks. */	100	/** Destination masks. */
101	#define DEST_ALL 0xff	101	#define DEST_ALL 0xff
102		102
103	/** Dest format models. */	103	/** Dest format models. */
104	#define MODEL_FLAT 0xf	104	#define MODEL_FLAT 0xf
105	#define MODEL_CLUSTER 0x0	105	#define MODEL_CLUSTER 0x0
106		106
107	/** Interrupt Command Register. */	107	/** Interrupt Command Register. */
108	#define ICRlo (0x300/sizeof(uint32_t))	108	#define ICRlo (0x300 / sizeof(uint32_t))
109	#define ICRhi (0x310/sizeof(uint32_t))	109	#define ICRhi (0x310 / sizeof(uint32_t))
110	typedef struct {	110	typedef struct {
111	union {	111	union {
112	uint32_t lo;	112	uint32_t lo;
113	struct {	113	struct {
114	uint8_t vector; /*< Interrupt Vector. /	114	uint8_t vector; /*< Interrupt Vector. /
115	unsigned delmod : 3; /*< Delivery Mode. /	115	unsigned delmod : 3; /*< Delivery Mode. /
116	unsigned destmod : 1; /*< Destination Mode. /	116	unsigned destmod : 1; /*< Destination Mode. /
117	unsigned delivs : 1; /*< Delivery status (RO). /	117	unsigned delivs : 1; /*< Delivery status (RO). /
118	unsigned : 1; /*< Reserved. /	118	unsigned : 1; /*< Reserved. /
119	unsigned level : 1; /*< Level. /	119	unsigned level : 1; /*< Level. /
120	unsigned trigger_mode : 1; /*< Trigger Mode. /	120	unsigned trigger_mode : 1; /*< Trigger Mode. /
121	unsigned : 2; /*< Reserved. /	121	unsigned : 2; /*< Reserved. /
122	unsigned shorthand : 2; /*< Destination Shorthand. /	122	unsigned shorthand : 2; /*< Destination Shorthand. /
123	unsigned : 12; /*< Reserved. /	123	unsigned : 12; /*< Reserved. /
124	} __attribute__ ((packed));	124	} __attribute__ ((packed));
125	};	125	};
126	union {	126	union {
127	uint32_t hi;	127	uint32_t hi;
128	struct {	128	struct {
129	unsigned : 24; /*< Reserved. /	129	unsigned : 24; /*< Reserved. /
130	uint8_t dest; /*< Destination field. /	130	uint8_t dest; /*< Destination field. /
131	} __attribute__ ((packed));	131	} __attribute__ ((packed));
132	};	132	};
133	} __attribute__ ((packed)) icr_t;	133	} __attribute__ ((packed)) icr_t;
134		134
135	/* End Of Interrupt. */	135	/* End Of Interrupt. */
136	#define EOI (0x0b0/sizeof(uint32_t))	136	#define EOI (0x0b0 / sizeof(uint32_t))
137		137
138	/** Error Status Register. */	138	/** Error Status Register. */
139	#define ESR (0x280/sizeof(uint32_t))	139	#define ESR (0x280 / sizeof(uint32_t))
140	typedef union {	140	typedef union {
141	uint32_t value;	141	uint32_t value;
142	uint8_t err_bitmap;	142	uint8_t err_bitmap;
143	struct {	143	struct {
144	unsigned send_checksum_error : 1;	144	unsigned send_checksum_error : 1;
145	unsigned receive_checksum_error : 1;	145	unsigned receive_checksum_error : 1;
146	unsigned send_accept_error : 1;	146	unsigned send_accept_error : 1;
147	unsigned receive_accept_error : 1;	147	unsigned receive_accept_error : 1;
148	unsigned : 1;	148	unsigned : 1;
149	unsigned send_illegal_vector : 1;	149	unsigned send_illegal_vector : 1;
150	unsigned received_illegal_vector : 1;	150	unsigned received_illegal_vector : 1;
151	unsigned illegal_register_address : 1;	151	unsigned illegal_register_address : 1;
152	unsigned : 24;	152	unsigned : 24;
153	} __attribute__ ((packed));	153	} __attribute__ ((packed));
154	} esr_t;	154	} esr_t;
155		155
156	/* Task Priority Register */	156	/* Task Priority Register */
157	#define TPR (0x080/sizeof(uint32_t))	157	#define TPR (0x080 / sizeof(uint32_t))
158	typedef union {	158	typedef union {
159	uint32_t value;	159	uint32_t value;
160	struct {	160	struct {
161	unsigned pri_sc : 4; /*< Task Priority Sub-Class. /	161	unsigned pri_sc : 4; /*< Task Priority Sub-Class. /
162	unsigned pri : 4; /*< Task Priority. /	162	unsigned pri : 4; /*< Task Priority. /
163	} __attribute__ ((packed));	163	} __attribute__ ((packed));
164	} tpr_t;	164	} tpr_t;
165		165
166	/** Spurious-Interrupt Vector Register. */	166	/** Spurious-Interrupt Vector Register. */
167	#define SVR (0x0f0/sizeof(uint32_t))	167	#define SVR (0x0f0 / sizeof(uint32_t))
168	typedef union {	168	typedef union {
169	uint32_t value;	169	uint32_t value;
170	struct {	170	struct {
171	uint8_t vector; /*< Spurious Vector. /	171	uint8_t vector; /*< Spurious Vector. /
172	unsigned lapic_enabled : 1; /*< APIC Software Enable/Disable. /	172	unsigned lapic_enabled : 1; /*< APIC Software Enable/Disable. /
173	unsigned focus_checking : 1; /*< Focus Processor Checking. /	173	unsigned focus_checking : 1; /*< Focus Processor Checking. /
174	unsigned : 22; /*< Reserved. /	174	unsigned : 22; /*< Reserved. /
175	} __attribute__ ((packed));	175	} __attribute__ ((packed));
176	} svr_t;	176	} svr_t;
177		177
178	/** Time Divide Configuration Register. */	178	/** Time Divide Configuration Register. */
179	#define TDCR (0x3e0/sizeof(uint32_t))	179	#define TDCR (0x3e0 / sizeof(uint32_t))
180	typedef union {	180	typedef union {
181	uint32_t value;	181	uint32_t value;
182	struct {	182	struct {
183	unsigned div_value : 4; /*< Divide Value, bit 2 is always 0. /	183	unsigned div_value : 4; /*< Divide Value, bit 2 is always 0. /
184	unsigned : 28; /*< Reserved. /	184	unsigned : 28; /*< Reserved. /
185	} __attribute__ ((packed));	185	} __attribute__ ((packed));
186	} tdcr_t;	186	} tdcr_t;
187		187
188	/* Initial Count Register for Timer */	188	/* Initial Count Register for Timer */
189	#define ICRT (0x380/sizeof(uint32_t))	189	#define ICRT (0x380 / sizeof(uint32_t))
190		190
191	/* Current Count Register for Timer */	191	/* Current Count Register for Timer */
192	#define CCRT (0x390/sizeof(uint32_t))	192	#define CCRT (0x390 / sizeof(uint32_t))
193		193
194	/** LVT Timer register. */	194	/** LVT Timer register. */
195	#define LVT_Tm (0x320/sizeof(uint32_t))	195	#define LVT_Tm (0x320 / sizeof(uint32_t))
196	typedef union {	196	typedef union {
197	uint32_t value;	197	uint32_t value;
198	struct {	198	struct {
199	uint8_t vector; /*< Local Timer Interrupt vector. /	199	uint8_t vector; /*< Local Timer Interrupt vector. /
200	unsigned : 4; /*< Reserved. /	200	unsigned : 4; /*< Reserved. /
201	unsigned delivs : 1; /*< Delivery status (RO). /	201	unsigned delivs : 1; /*< Delivery status (RO). /
202	unsigned : 3; /*< Reserved. /	202	unsigned : 3; /*< Reserved. /
203	unsigned masked : 1; /*< Interrupt Mask. /	203	unsigned masked : 1; /*< Interrupt Mask. /
204	unsigned mode : 1; /*< Timer Mode. /	204	unsigned mode : 1; /*< Timer Mode. /
205	unsigned : 14; /*< Reserved. /	205	unsigned : 14; /*< Reserved. /
206	} __attribute__ ((packed));	206	} __attribute__ ((packed));
207	} lvt_tm_t;	207	} lvt_tm_t;
208		208
209	/** LVT LINT registers. */	209	/** LVT LINT registers. */
210	#define LVT_LINT0 (0x350/sizeof(uint32_t))	210	#define LVT_LINT0 (0x350 / sizeof(uint32_t))
211	#define LVT_LINT1 (0x360/sizeof(uint32_t))	211	#define LVT_LINT1 (0x360 / sizeof(uint32_t))
212	typedef union {	212	typedef union {
213	uint32_t value;	213	uint32_t value;
214	struct {	214	struct {
215	uint8_t vector; /*< LINT Interrupt vector. /	215	uint8_t vector; /*< LINT Interrupt vector. /
216	unsigned delmod : 3; /*< Delivery Mode. /	216	unsigned delmod : 3; /*< Delivery Mode. /
217	unsigned : 1; /*< Reserved. /	217	unsigned : 1; /*< Reserved. /
218	unsigned delivs : 1; /*< Delivery status (RO). /	218	unsigned delivs : 1; /*< Delivery status (RO). /
219	unsigned intpol : 1; /*< Interrupt Input Pin Polarity. /	219	unsigned intpol : 1; /*< Interrupt Input Pin Polarity. /
220	unsigned irr : 1; /*< Remote IRR (RO). /	220	unsigned irr : 1; /*< Remote IRR (RO). /
221	unsigned trigger_mode : 1; /*< Trigger Mode. /	221	unsigned trigger_mode : 1; /*< Trigger Mode. /
222	unsigned masked : 1; /*< Interrupt Mask. /	222	unsigned masked : 1; /*< Interrupt Mask. /
223	unsigned : 15; /*< Reserved. /	223	unsigned : 15; /*< Reserved. /
224	} __attribute__ ((packed));	224	} __attribute__ ((packed));
225	} lvt_lint_t;	225	} lvt_lint_t;
226		226
227	/** LVT Error register. */	227	/** LVT Error register. */
228	#define LVT_Err (0x370/sizeof(uint32_t))	228	#define LVT_Err (0x370 / sizeof(uint32_t))
229	typedef union {	229	typedef union {
230	uint32_t value;	230	uint32_t value;
231	struct {	231	struct {
232	uint8_t vector; /*< Local Timer Interrupt vector. /	232	uint8_t vector; /*< Local Timer Interrupt vector. /
233	unsigned : 4; /*< Reserved. /	233	unsigned : 4; /*< Reserved. /
234	unsigned delivs : 1; /*< Delivery status (RO). /	234	unsigned delivs : 1; /*< Delivery status (RO). /
235	unsigned : 3; /*< Reserved. /	235	unsigned : 3; /*< Reserved. /
236	unsigned masked : 1; /*< Interrupt Mask. /	236	unsigned masked : 1; /*< Interrupt Mask. /
237	unsigned : 15; /*< Reserved. /	237	unsigned : 15; /*< Reserved. /
238	} __attribute__ ((packed));	238	} __attribute__ ((packed));
239	} lvt_error_t;	239	} lvt_error_t;
240		240
241	/** Local APIC ID Register. */	241	/** Local APIC ID Register. */
242	#define L_APIC_ID (0x020/sizeof(uint32_t))	242	#define L_APIC_ID (0x020 / sizeof(uint32_t))
243	typedef union {	243	typedef union {
244	uint32_t value;	244	uint32_t value;
245	struct {	245	struct {
246	unsigned : 24; /*< Reserved. /	246	unsigned : 24; /*< Reserved. /
247	uint8_t apic_id; /*< Local APIC ID. /	247	uint8_t apic_id; /*< Local APIC ID. /
248	} __attribute__ ((packed));	248	} __attribute__ ((packed));
249	} l_apic_id_t;	249	} l_apic_id_t;
250		250
251	/** Local APIC Version Register */	251	/** Local APIC Version Register */
252	#define LAVR (0x030/sizeof(uint32_t))	252	#define LAVR (0x030 / sizeof(uint32_t))
253	#define LAVR_Mask 0xff	253	#define LAVR_Mask 0xff
254	#define is_local_apic(x) (((x)&LAVR_Mask&0xf0)==0x1)	254	#define is_local_apic(x) (((x) & LAVR_Mask & 0xf0) == 0x1)
255	#define is_82489DX_apic(x) ((((x)&LAVR_Mask&0xf0)==0x0))	255	#define is_82489DX_apic(x) ((((x) & LAVR_Mask & 0xf0) == 0x0))
256	#define is_local_xapic(x) (((x)&LAVR_Mask)==0x14)	256	#define is_local_xapic(x) (((x) & LAVR_Mask) == 0x14)
257		257
258	/** Logical Destination Register. */	258	/** Logical Destination Register. */
259	#define LDR (0x0d0/sizeof(uint32_t))	259	#define LDR (0x0d0 / sizeof(uint32_t))
260	typedef union {	260	typedef union {
261	uint32_t value;	261	uint32_t value;
262	struct {	262	struct {
263	unsigned : 24; /*< Reserved. /	263	unsigned : 24; /*< Reserved. /
264	uint8_t id; /*< Logical APIC ID. /	264	uint8_t id; /*< Logical APIC ID. /
265	} __attribute__ ((packed));	265	} __attribute__ ((packed));
266	} ldr_t;	266	} ldr_t;
267		267
268	/** Destination Format Register. */	268	/** Destination Format Register. */
269	#define DFR (0x0e0/sizeof(uint32_t))	269	#define DFR (0x0e0 / sizeof(uint32_t))
270	typedef union {	270	typedef union {
271	uint32_t value;	271	uint32_t value;
272	struct {	272	struct {
273	unsigned : 28; /*< Reserved, all ones. /	273	unsigned : 28; /*< Reserved, all ones. /
274	unsigned model : 4; /*< Model. /	274	unsigned model : 4; /*< Model. /
275	} __attribute__ ((packed));	275	} __attribute__ ((packed));
276	} dfr_t;	276	} dfr_t;
277		277
278	/* IO APIC */	278	/* IO APIC */
279	#define IOREGSEL (0x00/sizeof(uint32_t))	279	#define IOREGSEL (0x00 / sizeof(uint32_t))
280	#define IOWIN (0x10/sizeof(uint32_t))	280	#define IOWIN (0x10 / sizeof(uint32_t))
281		281
282	#define IOAPICID 0x00	282	#define IOAPICID 0x00
283	#define IOAPICVER 0x01	283	#define IOAPICVER 0x01
284	#define IOAPICARB 0x02	284	#define IOAPICARB 0x02
285	#define IOREDTBL 0x10	285	#define IOREDTBL 0x10
286		286
287	/** I/O Register Select Register. */	287	/** I/O Register Select Register. */
288	typedef union {	288	typedef union {
289	uint32_t value;	289	uint32_t value;
290	struct {	290	struct {
291	uint8_t reg_addr; /*< APIC Register Address. /	291	uint8_t reg_addr; /*< APIC Register Address. /
292	unsigned : 24; /*< Reserved. /	292	unsigned : 24; /*< Reserved. /
293	} __attribute__ ((packed));	293	} __attribute__ ((packed));
294	} io_regsel_t;	294	} io_regsel_t;
295		295
296	/** I/O Redirection Register. */	296	/** I/O Redirection Register. */
297	typedef struct io_redirection_reg {	297	typedef struct io_redirection_reg {
298	union {	298	union {
299	uint32_t lo;	299	uint32_t lo;
300	struct {	300	struct {
301	uint8_t intvec; /*< Interrupt Vector. /	301	uint8_t intvec; /*< Interrupt Vector. /
302	unsigned delmod : 3; /*< Delivery Mode. /	302	unsigned delmod : 3; /*< Delivery Mode. /
303	unsigned destmod : 1; /*< Destination mode. /	303	unsigned destmod : 1; /*< Destination mode. /
304	unsigned delivs : 1; /*< Delivery status (RO). /	304	unsigned delivs : 1; /*< Delivery status (RO). /
305	unsigned intpol : 1; /*< Interrupt Input Pin Polarity. /	305	unsigned intpol : 1; /*< Interrupt Input Pin Polarity. /
306	unsigned irr : 1; /*< Remote IRR (RO). /	306	unsigned irr : 1; /*< Remote IRR (RO). /
307	unsigned trigger_mode : 1; /*< Trigger Mode. /	307	unsigned trigger_mode : 1; /*< Trigger Mode. /
308	unsigned masked : 1; /*< Interrupt Mask. /	308	unsigned masked : 1; /*< Interrupt Mask. /
309	unsigned : 15; /*< Reserved. /	309	unsigned : 15; /*< Reserved. /
310	} __attribute__ ((packed));	310	} __attribute__ ((packed));
311	};	311	};
312	union {	312	union {
313	uint32_t hi;	313	uint32_t hi;
314	struct {	314	struct {
315	unsigned : 24; /*< Reserved. /	315	unsigned : 24; /*< Reserved. /
316	uint8_t dest : 8; /*< Destination Field. /	316	uint8_t dest : 8; /*< Destination Field. /
317	} __attribute__ ((packed));	317	} __attribute__ ((packed));
318	};	318	};
319		319
320	} __attribute__ ((packed)) io_redirection_reg_t;	320	} __attribute__ ((packed)) io_redirection_reg_t;
321		321
322		322
323	/** IO APIC Identification Register. */	323	/** IO APIC Identification Register. */
324	typedef union {	324	typedef union {
325	uint32_t value;	325	uint32_t value;
326	struct {	326	struct {
327	unsigned : 24; /*< Reserved. /	327	unsigned : 24; /*< Reserved. /
328	unsigned apic_id : 4; /*< IO APIC ID. /	328	unsigned apic_id : 4; /*< IO APIC ID. /
329	unsigned : 4; /*< Reserved. /	329	unsigned : 4; /*< Reserved. /
330	} __attribute__ ((packed));	330	} __attribute__ ((packed));
331	} io_apic_id_t;	331	} io_apic_id_t;
332		332
333	extern volatile uint32_t *l_apic;	333	extern volatile uint32_t *l_apic;
334	extern volatile uint32_t *io_apic;	334	extern volatile uint32_t *io_apic;
335		335
336	extern uint32_t apic_id_mask;	336	extern uint32_t apic_id_mask;
337		337
338	extern void apic_init(void);	338	extern void apic_init(void);
339		339
340	extern void l_apic_init(void);	340	extern void l_apic_init(void);
341	extern void l_apic_eoi(void);	341	extern void l_apic_eoi(void);
342	extern int l_apic_broadcast_custom_ipi(uint8_t vector);	342	extern int l_apic_broadcast_custom_ipi(uint8_t vector);
343	extern int l_apic_send_init_ipi(uint8_t apicid);	343	extern int l_apic_send_init_ipi(uint8_t apicid);
344	extern void l_apic_debug(void);	344	extern void l_apic_debug(void);
345	extern uint8_t l_apic_id(void);	345	extern uint8_t l_apic_id(void);
346		346
347	extern uint32_t io_apic_read(uint8_t address);	347	extern uint32_t io_apic_read(uint8_t address);
348	extern void io_apic_write(uint8_t address , uint32_t x);	348	extern void io_apic_write(uint8_t address , uint32_t x);
349	extern void io_apic_change_ioredtbl(uint8_t pin, uint8_t dest, uint8_t v, int flags);	349	extern void io_apic_change_ioredtbl(uint8_t pin, uint8_t dest, uint8_t v, int flags);
350	extern void io_apic_disable_irqs(uint16_t irqmask);	350	extern void io_apic_disable_irqs(uint16_t irqmask);
351	extern void io_apic_enable_irqs(uint16_t irqmask);	351	extern void io_apic_enable_irqs(uint16_t irqmask);
352		352
353	#endif	353	#endif
354		354
355	/** @}	355	/** @}
356	*/	356	*/
357		357

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(root)/trunk/kernel/arch/ia32/include/smp/apic.h – Rev 2441 → 3071