WebSVN – HelenOS – Diff – /trunk/kernel/arch/ia32/include/smp/apic.h



/** Dest format models. */
#define MODEL_FLAT  0xf
#define MODEL_CLUSTER   0x0
 
/** Interrupt Command Register. */
#define ICRlo       (0x300 / sizeof(uint32_t))
#define ICRhi       (0x310 / sizeof(uint32_t))
typedef struct {
    union {
        uint32_t lo;
        struct {
            uint8_t vector;         /**< Interrupt Vector. */

        } __attribute__ ((packed));
    };
} __attribute__ ((packed)) icr_t;
 
/* End Of Interrupt. */
#define EOI     (0x0b0 / sizeof(uint32_t))
 
/** Error Status Register. */
#define ESR     (0x280 / sizeof(uint32_t))
typedef union {
    uint32_t value;
    uint8_t err_bitmap;
    struct {
        unsigned send_checksum_error : 1;

        unsigned : 24;
    } __attribute__ ((packed));
} esr_t;
 
/* Task Priority Register */
#define TPR     (0x080 / sizeof(uint32_t))
typedef union {
    uint32_t value;
    struct {
        unsigned pri_sc : 4;        /**< Task Priority Sub-Class. */
        unsigned pri : 4;       /**< Task Priority. */
    } __attribute__ ((packed));
} tpr_t;
 
/** Spurious-Interrupt Vector Register. */
#define SVR     (0x0f0 / sizeof(uint32_t))
typedef union {
    uint32_t value;
    struct {
        uint8_t vector;         /**< Spurious Vector. */
        unsigned lapic_enabled : 1; /**< APIC Software Enable/Disable. */

        unsigned : 22;          /**< Reserved. */
    } __attribute__ ((packed));
} svr_t;
 
/** Time Divide Configuration Register. */
#define TDCR        (0x3e0 / sizeof(uint32_t))
typedef union {
    uint32_t value;
    struct {
        unsigned div_value : 4;     /**< Divide Value, bit 2 is always 0. */
        unsigned : 28;          /**< Reserved. */
    } __attribute__ ((packed));
} tdcr_t;
 
/* Initial Count Register for Timer */
#define ICRT        (0x380 / sizeof(uint32_t))
 
/* Current Count Register for Timer */
#define CCRT        (0x390 / sizeof(uint32_t))
 
/** LVT Timer register. */
#define LVT_Tm      (0x320 / sizeof(uint32_t))
typedef union {
    uint32_t value;
    struct {
        uint8_t vector;     /**< Local Timer Interrupt vector. */
        unsigned : 4;       /**< Reserved. */

        unsigned : 14;      /**< Reserved. */
    } __attribute__ ((packed));
} lvt_tm_t;
 
/** LVT LINT registers. */
#define LVT_LINT0   (0x350 / sizeof(uint32_t))
#define LVT_LINT1   (0x360 / sizeof(uint32_t))
typedef union {
    uint32_t value;
    struct {
        uint8_t vector;         /**< LINT Interrupt vector. */
        unsigned delmod : 3;        /**< Delivery Mode. */

        unsigned : 15;          /**< Reserved. */
    } __attribute__ ((packed));
} lvt_lint_t;
 
/** LVT Error register. */
#define LVT_Err     (0x370 / sizeof(uint32_t))
typedef union {
    uint32_t value;
    struct {
        uint8_t vector;     /**< Local Timer Interrupt vector. */
        unsigned : 4;       /**< Reserved. */

        unsigned : 15;      /**< Reserved. */
    } __attribute__ ((packed));
} lvt_error_t;
 
/** Local APIC ID Register. */
#define L_APIC_ID   (0x020 / sizeof(uint32_t))
typedef union {
    uint32_t value;
    struct {
        unsigned : 24;      /**< Reserved. */
        uint8_t apic_id;        /**< Local APIC ID. */
    } __attribute__ ((packed));
} l_apic_id_t;
 
/** Local APIC Version Register */
#define LAVR        (0x030 / sizeof(uint32_t))
#define LAVR_Mask   0xff
#define is_local_apic(x)    (((x) & LAVR_Mask & 0xf0) == 0x1)
#define is_82489DX_apic(x)  ((((x) & LAVR_Mask & 0xf0) == 0x0))
#define is_local_xapic(x)   (((x) & LAVR_Mask) == 0x14)
 
/** Logical Destination Register. */
#define  LDR        (0x0d0 / sizeof(uint32_t))
typedef union {
    uint32_t value;
    struct {
        unsigned : 24;      /**< Reserved. */
        uint8_t id;     /**< Logical APIC ID. */
    } __attribute__ ((packed));
} ldr_t;
 
/** Destination Format Register. */
#define DFR     (0x0e0 / sizeof(uint32_t))
typedef union {
    uint32_t value;
    struct {
        unsigned : 28;      /**< Reserved, all ones. */
        unsigned model : 4; /**< Model. */
    } __attribute__ ((packed));
} dfr_t;
 
/* IO APIC */
#define IOREGSEL    (0x00 / sizeof(uint32_t))
#define IOWIN       (0x10 / sizeof(uint32_t))
 
#define IOAPICID    0x00
#define IOAPICVER   0x01
#define IOAPICARB   0x02
#define IOREDTBL    0x10

Rev 2441	Rev 3071
Line 103...	Line 103...
103	/** Dest format models. */	103	/** Dest format models. */
104	#define MODEL_FLAT 0xf	104	#define MODEL_FLAT 0xf
105	#define MODEL_CLUSTER 0x0	105	#define MODEL_CLUSTER 0x0
106		106
107	/** Interrupt Command Register. */	107	/** Interrupt Command Register. */
108	#define ICRlo (0x300/sizeof(uint32_t))	108	#define ICRlo (0x300 / sizeof(uint32_t))
109	#define ICRhi (0x310/sizeof(uint32_t))	109	#define ICRhi (0x310 / sizeof(uint32_t))
110	typedef struct {	110	typedef struct {
111	union {	111	union {
112	uint32_t lo;	112	uint32_t lo;
113	struct {	113	struct {
114	uint8_t vector; /*< Interrupt Vector. /	114	uint8_t vector; /*< Interrupt Vector. /
Line 131...	Line 131...
131	} __attribute__ ((packed));	131	} __attribute__ ((packed));
132	};	132	};
133	} __attribute__ ((packed)) icr_t;	133	} __attribute__ ((packed)) icr_t;
134		134
135	/* End Of Interrupt. */	135	/* End Of Interrupt. */
136	#define EOI (0x0b0/sizeof(uint32_t))	136	#define EOI (0x0b0 / sizeof(uint32_t))
137		137
138	/** Error Status Register. */	138	/** Error Status Register. */
139	#define ESR (0x280/sizeof(uint32_t))	139	#define ESR (0x280 / sizeof(uint32_t))
140	typedef union {	140	typedef union {
141	uint32_t value;	141	uint32_t value;
142	uint8_t err_bitmap;	142	uint8_t err_bitmap;
143	struct {	143	struct {
144	unsigned send_checksum_error : 1;	144	unsigned send_checksum_error : 1;
Line 152...	Line 152...
152	unsigned : 24;	152	unsigned : 24;
153	} __attribute__ ((packed));	153	} __attribute__ ((packed));
154	} esr_t;	154	} esr_t;
155		155
156	/* Task Priority Register */	156	/* Task Priority Register */
157	#define TPR (0x080/sizeof(uint32_t))	157	#define TPR (0x080 / sizeof(uint32_t))
158	typedef union {	158	typedef union {
159	uint32_t value;	159	uint32_t value;
160	struct {	160	struct {
161	unsigned pri_sc : 4; /*< Task Priority Sub-Class. /	161	unsigned pri_sc : 4; /*< Task Priority Sub-Class. /
162	unsigned pri : 4; /*< Task Priority. /	162	unsigned pri : 4; /*< Task Priority. /
163	} __attribute__ ((packed));	163	} __attribute__ ((packed));
164	} tpr_t;	164	} tpr_t;
165		165
166	/** Spurious-Interrupt Vector Register. */	166	/** Spurious-Interrupt Vector Register. */
167	#define SVR (0x0f0/sizeof(uint32_t))	167	#define SVR (0x0f0 / sizeof(uint32_t))
168	typedef union {	168	typedef union {
169	uint32_t value;	169	uint32_t value;
170	struct {	170	struct {
171	uint8_t vector; /*< Spurious Vector. /	171	uint8_t vector; /*< Spurious Vector. /
172	unsigned lapic_enabled : 1; /*< APIC Software Enable/Disable. /	172	unsigned lapic_enabled : 1; /*< APIC Software Enable/Disable. /
Line 174...	Line 174...
174	unsigned : 22; /*< Reserved. /	174	unsigned : 22; /*< Reserved. /
175	} __attribute__ ((packed));	175	} __attribute__ ((packed));
176	} svr_t;	176	} svr_t;
177		177
178	/** Time Divide Configuration Register. */	178	/** Time Divide Configuration Register. */
179	#define TDCR (0x3e0/sizeof(uint32_t))	179	#define TDCR (0x3e0 / sizeof(uint32_t))
180	typedef union {	180	typedef union {
181	uint32_t value;	181	uint32_t value;
182	struct {	182	struct {
183	unsigned div_value : 4; /*< Divide Value, bit 2 is always 0. /	183	unsigned div_value : 4; /*< Divide Value, bit 2 is always 0. /
184	unsigned : 28; /*< Reserved. /	184	unsigned : 28; /*< Reserved. /
185	} __attribute__ ((packed));	185	} __attribute__ ((packed));
186	} tdcr_t;	186	} tdcr_t;
187		187
188	/* Initial Count Register for Timer */	188	/* Initial Count Register for Timer */
189	#define ICRT (0x380/sizeof(uint32_t))	189	#define ICRT (0x380 / sizeof(uint32_t))
190		190
191	/* Current Count Register for Timer */	191	/* Current Count Register for Timer */
192	#define CCRT (0x390/sizeof(uint32_t))	192	#define CCRT (0x390 / sizeof(uint32_t))
193		193
194	/** LVT Timer register. */	194	/** LVT Timer register. */
195	#define LVT_Tm (0x320/sizeof(uint32_t))	195	#define LVT_Tm (0x320 / sizeof(uint32_t))
196	typedef union {	196	typedef union {
197	uint32_t value;	197	uint32_t value;
198	struct {	198	struct {
199	uint8_t vector; /*< Local Timer Interrupt vector. /	199	uint8_t vector; /*< Local Timer Interrupt vector. /
200	unsigned : 4; /*< Reserved. /	200	unsigned : 4; /*< Reserved. /
Line 205...	Line 205...
205	unsigned : 14; /*< Reserved. /	205	unsigned : 14; /*< Reserved. /
206	} __attribute__ ((packed));	206	} __attribute__ ((packed));
207	} lvt_tm_t;	207	} lvt_tm_t;
208		208
209	/** LVT LINT registers. */	209	/** LVT LINT registers. */
210	#define LVT_LINT0 (0x350/sizeof(uint32_t))	210	#define LVT_LINT0 (0x350 / sizeof(uint32_t))
211	#define LVT_LINT1 (0x360/sizeof(uint32_t))	211	#define LVT_LINT1 (0x360 / sizeof(uint32_t))
212	typedef union {	212	typedef union {
213	uint32_t value;	213	uint32_t value;
214	struct {	214	struct {
215	uint8_t vector; /*< LINT Interrupt vector. /	215	uint8_t vector; /*< LINT Interrupt vector. /
216	unsigned delmod : 3; /*< Delivery Mode. /	216	unsigned delmod : 3; /*< Delivery Mode. /
Line 223...	Line 223...
223	unsigned : 15; /*< Reserved. /	223	unsigned : 15; /*< Reserved. /
224	} __attribute__ ((packed));	224	} __attribute__ ((packed));
225	} lvt_lint_t;	225	} lvt_lint_t;
226		226
227	/** LVT Error register. */	227	/** LVT Error register. */
228	#define LVT_Err (0x370/sizeof(uint32_t))	228	#define LVT_Err (0x370 / sizeof(uint32_t))
229	typedef union {	229	typedef union {
230	uint32_t value;	230	uint32_t value;
231	struct {	231	struct {
232	uint8_t vector; /*< Local Timer Interrupt vector. /	232	uint8_t vector; /*< Local Timer Interrupt vector. /
233	unsigned : 4; /*< Reserved. /	233	unsigned : 4; /*< Reserved. /
Line 237...	Line 237...
237	unsigned : 15; /*< Reserved. /	237	unsigned : 15; /*< Reserved. /
238	} __attribute__ ((packed));	238	} __attribute__ ((packed));
239	} lvt_error_t;	239	} lvt_error_t;
240		240
241	/** Local APIC ID Register. */	241	/** Local APIC ID Register. */
242	#define L_APIC_ID (0x020/sizeof(uint32_t))	242	#define L_APIC_ID (0x020 / sizeof(uint32_t))
243	typedef union {	243	typedef union {
244	uint32_t value;	244	uint32_t value;
245	struct {	245	struct {
246	unsigned : 24; /*< Reserved. /	246	unsigned : 24; /*< Reserved. /
247	uint8_t apic_id; /*< Local APIC ID. /	247	uint8_t apic_id; /*< Local APIC ID. /
248	} __attribute__ ((packed));	248	} __attribute__ ((packed));
249	} l_apic_id_t;	249	} l_apic_id_t;
250		250
251	/** Local APIC Version Register */	251	/** Local APIC Version Register */
252	#define LAVR (0x030/sizeof(uint32_t))	252	#define LAVR (0x030 / sizeof(uint32_t))
253	#define LAVR_Mask 0xff	253	#define LAVR_Mask 0xff
254	#define is_local_apic(x) (((x)&LAVR_Mask&0xf0)==0x1)	254	#define is_local_apic(x) (((x) & LAVR_Mask & 0xf0) == 0x1)
255	#define is_82489DX_apic(x) ((((x)&LAVR_Mask&0xf0)==0x0))	255	#define is_82489DX_apic(x) ((((x) & LAVR_Mask & 0xf0) == 0x0))
256	#define is_local_xapic(x) (((x)&LAVR_Mask)==0x14)	256	#define is_local_xapic(x) (((x) & LAVR_Mask) == 0x14)
257		257
258	/** Logical Destination Register. */	258	/** Logical Destination Register. */
259	#define LDR (0x0d0/sizeof(uint32_t))	259	#define LDR (0x0d0 / sizeof(uint32_t))
260	typedef union {	260	typedef union {
261	uint32_t value;	261	uint32_t value;
262	struct {	262	struct {
263	unsigned : 24; /*< Reserved. /	263	unsigned : 24; /*< Reserved. /
264	uint8_t id; /*< Logical APIC ID. /	264	uint8_t id; /*< Logical APIC ID. /
265	} __attribute__ ((packed));	265	} __attribute__ ((packed));
266	} ldr_t;	266	} ldr_t;
267		267
268	/** Destination Format Register. */	268	/** Destination Format Register. */
269	#define DFR (0x0e0/sizeof(uint32_t))	269	#define DFR (0x0e0 / sizeof(uint32_t))
270	typedef union {	270	typedef union {
271	uint32_t value;	271	uint32_t value;
272	struct {	272	struct {
273	unsigned : 28; /*< Reserved, all ones. /	273	unsigned : 28; /*< Reserved, all ones. /
274	unsigned model : 4; /*< Model. /	274	unsigned model : 4; /*< Model. /
275	} __attribute__ ((packed));	275	} __attribute__ ((packed));
276	} dfr_t;	276	} dfr_t;
277		277
278	/* IO APIC */	278	/* IO APIC */
279	#define IOREGSEL (0x00/sizeof(uint32_t))	279	#define IOREGSEL (0x00 / sizeof(uint32_t))
280	#define IOWIN (0x10/sizeof(uint32_t))	280	#define IOWIN (0x10 / sizeof(uint32_t))
281		281
282	#define IOAPICID 0x00	282	#define IOAPICID 0x00
283	#define IOAPICVER 0x01	283	#define IOAPICVER 0x01
284	#define IOAPICARB 0x02	284	#define IOAPICARB 0x02
285	#define IOREDTBL 0x10	285	#define IOREDTBL 0x10

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(root)/trunk/kernel/arch/ia32/include/smp/apic.h – Rev 2441 → 3071