WebSVN – HelenOS – Diff – /trunk/kernel/arch/ia32/include/smp/apic.h



#define MODEL_CLUSTER   0x0
 
/** Interrupt Command Register. */
#define ICRlo       (0x300/sizeof(uint32_t))
#define ICRhi       (0x310/sizeof(uint32_t))
typedef struct {
    union {
        uint32_t lo;
        struct {
            uint8_t vector;         /**< Interrupt Vector. */
            unsigned delmod : 3;        /**< Delivery Mode. */

        struct {
            unsigned : 24;          /**< Reserved. */
            uint8_t dest;           /**< Destination field. */
        } __attribute__ ((packed));
    };
} __attribute__ ((packed)) icr_t;
 
 
/* End Of Interrupt. */
#define EOI     (0x0b0/sizeof(uint32_t))
 
/** Error Status Register. */
#define ESR     (0x280/sizeof(uint32_t))
typedef union {
    uint32_t value;
    uint8_t err_bitmap;
    struct {
        unsigned send_checksum_error : 1;
        unsigned receive_checksum_error : 1;

        unsigned send_illegal_vector : 1;
        unsigned received_illegal_vector : 1;
        unsigned illegal_register_address : 1;
        unsigned : 24;
    } __attribute__ ((packed));
} esr_t;
 
 
/* Task Priority Register */
#define TPR     (0x080/sizeof(uint32_t))
typedef union {
    uint32_t value;
    struct {
        unsigned pri_sc : 4;        /**< Task Priority Sub-Class. */
        unsigned pri : 4;       /**< Task Priority. */
    } __attribute__ ((packed));
} tpr_t;
 
 
/** Spurious-Interrupt Vector Register. */
#define SVR     (0x0f0/sizeof(uint32_t))
typedef union {
    uint32_t value;
    struct {
        uint8_t vector;         /**< Spurious Vector. */
        unsigned lapic_enabled : 1; /**< APIC Software Enable/Disable. */
        unsigned focus_checking : 1;    /**< Focus Processor Checking. */
        unsigned : 22;          /**< Reserved. */
    } __attribute__ ((packed));
} svr_t;
 
 
/** Time Divide Configuration Register. */
#define TDCR        (0x3e0/sizeof(uint32_t))
typedef union {
    uint32_t value;
    struct {
        unsigned div_value : 4;     /**< Divide Value, bit 2 is always 0. */
        unsigned : 28;          /**< Reserved. */
    } __attribute__ ((packed));
 
} tdcr_t;
 
/* Initial Count Register for Timer */
#define ICRT        (0x380/sizeof(uint32_t))
 
/* Current Count Register for Timer */
#define CCRT        (0x390/sizeof(uint32_t))
 
/** LVT Timer register. */
#define LVT_Tm      (0x320/sizeof(uint32_t))
typedef union {
    uint32_t value;
    struct {
        uint8_t vector;     /**< Local Timer Interrupt vector. */
        unsigned : 4;       /**< Reserved. */
        unsigned delivs : 1;    /**< Delivery status (RO). */
        unsigned : 3;       /**< Reserved. */
        unsigned masked : 1;    /**< Interrupt Mask. */
        unsigned mode : 1;  /**< Timer Mode. */
        unsigned : 14;      /**< Reserved. */
    } __attribute__ ((packed));
 
} lvt_tm_t;
 
/** LVT LINT registers. */
#define LVT_LINT0   (0x350/sizeof(uint32_t))
#define LVT_LINT1   (0x360/sizeof(uint32_t))
typedef union {
    uint32_t value;
    struct {
        uint8_t vector;         /**< LINT Interrupt vector. */
        unsigned delmod : 3;        /**< Delivery Mode. */
        unsigned : 1;           /**< Reserved. */

        unsigned irr : 1;       /**< Remote IRR (RO). */
        unsigned trigger_mode : 1;  /**< Trigger Mode. */
        unsigned masked : 1;        /**< Interrupt Mask. */
        unsigned : 15;          /**< Reserved. */
    } __attribute__ ((packed));
 
} lvt_lint_t;
 
/** LVT Error register. */
#define LVT_Err     (0x370/sizeof(uint32_t))
typedef union {
    uint32_t value;
    struct {
        uint8_t vector;     /**< Local Timer Interrupt vector. */
        unsigned : 4;       /**< Reserved. */
        unsigned delivs : 1;    /**< Delivery status (RO). */
        unsigned : 3;       /**< Reserved. */
        unsigned masked : 1;    /**< Interrupt Mask. */
        unsigned : 15;      /**< Reserved. */
    } __attribute__ ((packed));
 
} lvt_error_t;
 
/** Local APIC ID Register. */
#define L_APIC_ID   (0x020/sizeof(uint32_t))
typedef union {
    uint32_t value;
    struct {
        unsigned : 24;      /**< Reserved. */
        uint8_t apic_id;        /**< Local APIC ID. */
    } __attribute__ ((packed));
 
} l_apic_id_t;
 
/** Local APIC Version Register */
#define LAVR        (0x030/sizeof(uint32_t))
#define LAVR_Mask   0xff
#define is_local_apic(x)    (((x)&LAVR_Mask&0xf0)==0x1)
#define is_82489DX_apic(x)  ((((x)&LAVR_Mask&0xf0)==0x0))
#define is_local_xapic(x)   (((x)&LAVR_Mask)==0x14)
 
/** Logical Destination Register. */
#define  LDR        (0x0d0/sizeof(uint32_t))
typedef union {
    uint32_t value;
    struct {
        unsigned : 24;      /**< Reserved. */
        uint8_t id;     /**< Logical APIC ID. */
    } __attribute__ ((packed));
} ldr_t;
 
 
/** Destination Format Register. */
#define DFR     (0x0e0/sizeof(uint32_t))
typedef union {
    uint32_t value;
    struct {
        unsigned : 28;      /**< Reserved, all ones. */
        unsigned model : 4; /**< Model. */
    } __attribute__ ((packed));
} dfr_t;
 
 
/* IO APIC */
#define IOREGSEL    (0x00/sizeof(uint32_t))
#define IOWIN       (0x10/sizeof(uint32_t))
 

#define IOAPICVER   0x01
#define IOAPICARB   0x02
#define IOREDTBL    0x10
 
/** I/O Register Select Register. */
typedef union {
    uint32_t value;
    struct {
        uint8_t reg_addr;       /**< APIC Register Address. */
        unsigned : 24;      /**< Reserved. */
    } __attribute__ ((packed));
 
} io_regsel_t;
 
/** I/O Redirection Register. */
typedef struct io_redirection_reg {
    union {
        uint32_t lo;
        struct {
            uint8_t intvec;         /**< Interrupt Vector. */
            unsigned delmod : 3;        /**< Delivery Mode. */

            unsigned : 24;          /**< Reserved. */
            uint8_t dest : 8;           /**< Destination Field. */
        } __attribute__ ((packed));
    };
   
} __attribute__ ((packed)) io_redirection_reg_t;
 
 
 
/** IO APIC Identification Register. */
typedef union {
    uint32_t value;
    struct {
        unsigned : 24;      /**< Reserved. */
        unsigned apic_id : 4;   /**< IO APIC ID. */
        unsigned : 4;       /**< Reserved. */
    } __attribute__ ((packed));
 
} io_apic_id_t;
 
extern volatile uint32_t *l_apic;
extern volatile uint32_t *io_apic;
 
extern uint32_t apic_id_mask;

Rev 2071	Rev 2089
Line 105...	Line 105...
105	#define MODEL_CLUSTER 0x0	105	#define MODEL_CLUSTER 0x0
106		106
107	/** Interrupt Command Register. */	107	/** Interrupt Command Register. */
108	#define ICRlo (0x300/sizeof(uint32_t))	108	#define ICRlo (0x300/sizeof(uint32_t))
109	#define ICRhi (0x310/sizeof(uint32_t))	109	#define ICRhi (0x310/sizeof(uint32_t))
110	struct icr {	110	typedef struct {
111	union {	111	union {
112	uint32_t lo;	112	uint32_t lo;
113	struct {	113	struct {
114	uint8_t vector; /*< Interrupt Vector. /	114	uint8_t vector; /*< Interrupt Vector. /
115	unsigned delmod : 3; /*< Delivery Mode. /	115	unsigned delmod : 3; /*< Delivery Mode. /
Line 128...	Line 128...
128	struct {	128	struct {
129	unsigned : 24; /*< Reserved. /	129	unsigned : 24; /*< Reserved. /
130	uint8_t dest; /*< Destination field. /	130	uint8_t dest; /*< Destination field. /
131	} __attribute__ ((packed));	131	} __attribute__ ((packed));
132	};	132	};
133	} __attribute__ ((packed));	133	} __attribute__ ((packed)) icr_t;
134	typedef struct icr icr_t;	-
135		134
136	/* End Of Interrupt. */	135	/* End Of Interrupt. */
137	#define EOI (0x0b0/sizeof(uint32_t))	136	#define EOI (0x0b0/sizeof(uint32_t))
138		137
139	/** Error Status Register. */	138	/** Error Status Register. */
140	#define ESR (0x280/sizeof(uint32_t))	139	#define ESR (0x280/sizeof(uint32_t))
141	union esr {	140	typedef union {
142	uint32_t value;	141	uint32_t value;
143	uint8_t err_bitmap;	142	uint8_t err_bitmap;
144	struct {	143	struct {
145	unsigned send_checksum_error : 1;	144	unsigned send_checksum_error : 1;
146	unsigned receive_checksum_error : 1;	145	unsigned receive_checksum_error : 1;
Line 150...	Line 149...
150	unsigned send_illegal_vector : 1;	149	unsigned send_illegal_vector : 1;
151	unsigned received_illegal_vector : 1;	150	unsigned received_illegal_vector : 1;
152	unsigned illegal_register_address : 1;	151	unsigned illegal_register_address : 1;
153	unsigned : 24;	152	unsigned : 24;
154	} __attribute__ ((packed));	153	} __attribute__ ((packed));
155	};	154	} esr_t;
156	typedef union esr esr_t;	-
157		155
158	/* Task Priority Register */	156	/* Task Priority Register */
159	#define TPR (0x080/sizeof(uint32_t))	157	#define TPR (0x080/sizeof(uint32_t))
160	union tpr {	158	typedef union {
161	uint32_t value;	159	uint32_t value;
162	struct {	160	struct {
163	unsigned pri_sc : 4; /*< Task Priority Sub-Class. /	161	unsigned pri_sc : 4; /*< Task Priority Sub-Class. /
164	unsigned pri : 4; /*< Task Priority. /	162	unsigned pri : 4; /*< Task Priority. /
165	} __attribute__ ((packed));	163	} __attribute__ ((packed));
166	};	164	} tpr_t;
167	typedef union tpr tpr_t;	-
168		165
169	/** Spurious-Interrupt Vector Register. */	166	/** Spurious-Interrupt Vector Register. */
170	#define SVR (0x0f0/sizeof(uint32_t))	167	#define SVR (0x0f0/sizeof(uint32_t))
171	union svr {	168	typedef union {
172	uint32_t value;	169	uint32_t value;
173	struct {	170	struct {
174	uint8_t vector; /*< Spurious Vector. /	171	uint8_t vector; /*< Spurious Vector. /
175	unsigned lapic_enabled : 1; /*< APIC Software Enable/Disable. /	172	unsigned lapic_enabled : 1; /*< APIC Software Enable/Disable. /
176	unsigned focus_checking : 1; /*< Focus Processor Checking. /	173	unsigned focus_checking : 1; /*< Focus Processor Checking. /
177	unsigned : 22; /*< Reserved. /	174	unsigned : 22; /*< Reserved. /
178	} __attribute__ ((packed));	175	} __attribute__ ((packed));
179	};	176	} svr_t;
180	typedef union svr svr_t;	-
181		177
182	/** Time Divide Configuration Register. */	178	/** Time Divide Configuration Register. */
183	#define TDCR (0x3e0/sizeof(uint32_t))	179	#define TDCR (0x3e0/sizeof(uint32_t))
184	union tdcr {	180	typedef union {
185	uint32_t value;	181	uint32_t value;
186	struct {	182	struct {
187	unsigned div_value : 4; /*< Divide Value, bit 2 is always 0. /	183	unsigned div_value : 4; /*< Divide Value, bit 2 is always 0. /
188	unsigned : 28; /*< Reserved. /	184	unsigned : 28; /*< Reserved. /
189	} __attribute__ ((packed));	185	} __attribute__ ((packed));
190	};	-
191	typedef union tdcr tdcr_t;	186	} tdcr_t;
192		187
193	/* Initial Count Register for Timer */	188	/* Initial Count Register for Timer */
194	#define ICRT (0x380/sizeof(uint32_t))	189	#define ICRT (0x380/sizeof(uint32_t))
195		190
196	/* Current Count Register for Timer */	191	/* Current Count Register for Timer */
197	#define CCRT (0x390/sizeof(uint32_t))	192	#define CCRT (0x390/sizeof(uint32_t))
198		193
199	/** LVT Timer register. */	194	/** LVT Timer register. */
200	#define LVT_Tm (0x320/sizeof(uint32_t))	195	#define LVT_Tm (0x320/sizeof(uint32_t))
201	union lvt_tm {	196	typedef union {
202	uint32_t value;	197	uint32_t value;
203	struct {	198	struct {
204	uint8_t vector; /*< Local Timer Interrupt vector. /	199	uint8_t vector; /*< Local Timer Interrupt vector. /
205	unsigned : 4; /*< Reserved. /	200	unsigned : 4; /*< Reserved. /
206	unsigned delivs : 1; /*< Delivery status (RO). /	201	unsigned delivs : 1; /*< Delivery status (RO). /
207	unsigned : 3; /*< Reserved. /	202	unsigned : 3; /*< Reserved. /
208	unsigned masked : 1; /*< Interrupt Mask. /	203	unsigned masked : 1; /*< Interrupt Mask. /
209	unsigned mode : 1; /*< Timer Mode. /	204	unsigned mode : 1; /*< Timer Mode. /
210	unsigned : 14; /*< Reserved. /	205	unsigned : 14; /*< Reserved. /
211	} __attribute__ ((packed));	206	} __attribute__ ((packed));
212	};	-
213	typedef union lvt_tm lvt_tm_t;	207	} lvt_tm_t;
214		208
215	/** LVT LINT registers. */	209	/** LVT LINT registers. */
216	#define LVT_LINT0 (0x350/sizeof(uint32_t))	210	#define LVT_LINT0 (0x350/sizeof(uint32_t))
217	#define LVT_LINT1 (0x360/sizeof(uint32_t))	211	#define LVT_LINT1 (0x360/sizeof(uint32_t))
218	union lvt_lint {	212	typedef union {
219	uint32_t value;	213	uint32_t value;
220	struct {	214	struct {
221	uint8_t vector; /*< LINT Interrupt vector. /	215	uint8_t vector; /*< LINT Interrupt vector. /
222	unsigned delmod : 3; /*< Delivery Mode. /	216	unsigned delmod : 3; /*< Delivery Mode. /
223	unsigned : 1; /*< Reserved. /	217	unsigned : 1; /*< Reserved. /
Line 226...	Line 220...
226	unsigned irr : 1; /*< Remote IRR (RO). /	220	unsigned irr : 1; /*< Remote IRR (RO). /
227	unsigned trigger_mode : 1; /*< Trigger Mode. /	221	unsigned trigger_mode : 1; /*< Trigger Mode. /
228	unsigned masked : 1; /*< Interrupt Mask. /	222	unsigned masked : 1; /*< Interrupt Mask. /
229	unsigned : 15; /*< Reserved. /	223	unsigned : 15; /*< Reserved. /
230	} __attribute__ ((packed));	224	} __attribute__ ((packed));
231	};	-
232	typedef union lvt_lint lvt_lint_t;	225	} lvt_lint_t;
233		226
234	/** LVT Error register. */	227	/** LVT Error register. */
235	#define LVT_Err (0x370/sizeof(uint32_t))	228	#define LVT_Err (0x370/sizeof(uint32_t))
236	union lvt_error {	229	typedef union {
237	uint32_t value;	230	uint32_t value;
238	struct {	231	struct {
239	uint8_t vector; /*< Local Timer Interrupt vector. /	232	uint8_t vector; /*< Local Timer Interrupt vector. /
240	unsigned : 4; /*< Reserved. /	233	unsigned : 4; /*< Reserved. /
241	unsigned delivs : 1; /*< Delivery status (RO). /	234	unsigned delivs : 1; /*< Delivery status (RO). /
242	unsigned : 3; /*< Reserved. /	235	unsigned : 3; /*< Reserved. /
243	unsigned masked : 1; /*< Interrupt Mask. /	236	unsigned masked : 1; /*< Interrupt Mask. /
244	unsigned : 15; /*< Reserved. /	237	unsigned : 15; /*< Reserved. /
245	} __attribute__ ((packed));	238	} __attribute__ ((packed));
246	};	-
247	typedef union lvt_error lvt_error_t;	239	} lvt_error_t;
248		240
249	/** Local APIC ID Register. */	241	/** Local APIC ID Register. */
250	#define L_APIC_ID (0x020/sizeof(uint32_t))	242	#define L_APIC_ID (0x020/sizeof(uint32_t))
251	union l_apic_id {	243	typedef union {
252	uint32_t value;	244	uint32_t value;
253	struct {	245	struct {
254	unsigned : 24; /*< Reserved. /	246	unsigned : 24; /*< Reserved. /
255	uint8_t apic_id; /*< Local APIC ID. /	247	uint8_t apic_id; /*< Local APIC ID. /
256	} __attribute__ ((packed));	248	} __attribute__ ((packed));
257	};	-
258	typedef union l_apic_id l_apic_id_t;	249	} l_apic_id_t;
259		250
260	/** Local APIC Version Register */	251	/** Local APIC Version Register */
261	#define LAVR (0x030/sizeof(uint32_t))	252	#define LAVR (0x030/sizeof(uint32_t))
262	#define LAVR_Mask 0xff	253	#define LAVR_Mask 0xff
263	#define is_local_apic(x) (((x)&LAVR_Mask&0xf0)==0x1)	254	#define is_local_apic(x) (((x)&LAVR_Mask&0xf0)==0x1)
264	#define is_82489DX_apic(x) ((((x)&LAVR_Mask&0xf0)==0x0))	255	#define is_82489DX_apic(x) ((((x)&LAVR_Mask&0xf0)==0x0))
265	#define is_local_xapic(x) (((x)&LAVR_Mask)==0x14)	256	#define is_local_xapic(x) (((x)&LAVR_Mask)==0x14)
266		257
267	/** Logical Destination Register. */	258	/** Logical Destination Register. */
268	#define LDR (0x0d0/sizeof(uint32_t))	259	#define LDR (0x0d0/sizeof(uint32_t))
269	union ldr {	260	typedef union {
270	uint32_t value;	261	uint32_t value;
271	struct {	262	struct {
272	unsigned : 24; /*< Reserved. /	263	unsigned : 24; /*< Reserved. /
273	uint8_t id; /*< Logical APIC ID. /	264	uint8_t id; /*< Logical APIC ID. /
274	} __attribute__ ((packed));	265	} __attribute__ ((packed));
275	};	266	} ldr_t;
276	typedef union ldr ldr_t;	-
277		267
278	/** Destination Format Register. */	268	/** Destination Format Register. */
279	#define DFR (0x0e0/sizeof(uint32_t))	269	#define DFR (0x0e0/sizeof(uint32_t))
280	union dfr {	270	typedef union {
281	uint32_t value;	271	uint32_t value;
282	struct {	272	struct {
283	unsigned : 28; /*< Reserved, all ones. /	273	unsigned : 28; /*< Reserved, all ones. /
284	unsigned model : 4; /*< Model. /	274	unsigned model : 4; /*< Model. /
285	} __attribute__ ((packed));	275	} __attribute__ ((packed));
286	};	276	} dfr_t;
287	typedef union dfr dfr_t;	-
288		277
289	/* IO APIC */	278	/* IO APIC */
290	#define IOREGSEL (0x00/sizeof(uint32_t))	279	#define IOREGSEL (0x00/sizeof(uint32_t))
291	#define IOWIN (0x10/sizeof(uint32_t))	280	#define IOWIN (0x10/sizeof(uint32_t))
292		281
Line 294...	Line 283...
294	#define IOAPICVER 0x01	283	#define IOAPICVER 0x01
295	#define IOAPICARB 0x02	284	#define IOAPICARB 0x02
296	#define IOREDTBL 0x10	285	#define IOREDTBL 0x10
297		286
298	/** I/O Register Select Register. */	287	/** I/O Register Select Register. */
299	union io_regsel {	288	typedef union {
300	uint32_t value;	289	uint32_t value;
301	struct {	290	struct {
302	uint8_t reg_addr; /*< APIC Register Address. /	291	uint8_t reg_addr; /*< APIC Register Address. /
303	unsigned : 24; /*< Reserved. /	292	unsigned : 24; /*< Reserved. /
304	} __attribute__ ((packed));	293	} __attribute__ ((packed));
305	};	-
306	typedef union io_regsel io_regsel_t;	294	} io_regsel_t;
307		295
308	/** I/O Redirection Register. */	296	/** I/O Redirection Register. */
309	struct io_redirection_reg {	297	typedef struct io_redirection_reg {
310	union {	298	union {
311	uint32_t lo;	299	uint32_t lo;
312	struct {	300	struct {
313	uint8_t intvec; /*< Interrupt Vector. /	301	uint8_t intvec; /*< Interrupt Vector. /
314	unsigned delmod : 3; /*< Delivery Mode. /	302	unsigned delmod : 3; /*< Delivery Mode. /
Line 327...	Line 315...
327	unsigned : 24; /*< Reserved. /	315	unsigned : 24; /*< Reserved. /
328	uint8_t dest : 8; /*< Destination Field. /	316	uint8_t dest : 8; /*< Destination Field. /
329	} __attribute__ ((packed));	317	} __attribute__ ((packed));
330	};	318	};
331		319
332	} __attribute__ ((packed));	320	} __attribute__ ((packed)) io_redirection_reg_t;
333	typedef struct io_redirection_reg io_redirection_reg_t;	-
334		321
335		322
336	/** IO APIC Identification Register. */	323	/** IO APIC Identification Register. */
337	union io_apic_id {	324	typedef union {
338	uint32_t value;	325	uint32_t value;
339	struct {	326	struct {
340	unsigned : 24; /*< Reserved. /	327	unsigned : 24; /*< Reserved. /
341	unsigned apic_id : 4; /*< IO APIC ID. /	328	unsigned apic_id : 4; /*< IO APIC ID. /
342	unsigned : 4; /*< Reserved. /	329	unsigned : 4; /*< Reserved. /
343	} __attribute__ ((packed));	330	} __attribute__ ((packed));
344	};	-
345	typedef union io_apic_id io_apic_id_t;	331	} io_apic_id_t;
346		332
347	extern volatile uint32_t *l_apic;	333	extern volatile uint32_t *l_apic;
348	extern volatile uint32_t *io_apic;	334	extern volatile uint32_t *io_apic;
349		335
350	extern uint32_t apic_id_mask;	336	extern uint32_t apic_id_mask;

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(root)/trunk/kernel/arch/ia32/include/smp/apic.h – Rev 2071 → 2089