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| 89 | * even on SMP systems. We issue a write barrier to be sure that writes |
89 | * even on SMP systems. We issue a write barrier to be sure that writes |
| 90 | * queueing in the store buffer drain to the memory (even though it would be |
90 | * queueing in the store buffer drain to the memory (even though it would be |
| 91 | * sufficient for them to drain to the D-cache). |
91 | * sufficient for them to drain to the D-cache). |
| 92 | */ |
92 | */ |
| 93 | #define smc_coherence(a) write_barrier() |
93 | #define smc_coherence(a) write_barrier() |
| - | 94 | #define smc_coherence_block(a, l) write_barrier() |
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| 94 | 95 | ||
| 95 | #endif |
96 | #endif |
| 96 | 97 | ||
| 97 | /** @} |
98 | /** @} |
| 98 | */ |
99 | */ |