WebSVN – HelenOS – Diff – /trunk/kernel/arch/ia32/include/asm.h


/*
 * Copyright (c) 2001-2004 Jakub Jermar
 * Copyright (c) 2005 Sergey Bondari
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup ia32   
 * @{
 */
/** @file
 */
 
#ifndef KERN_ia32_ASM_H_
#define KERN_ia32_ASM_H_
 
#include <arch/pm.h>
#include <arch/types.h>
#include <config.h>
 
extern uint32_t interrupt_handler_size;
 
extern void paging_on(void);
 
extern void interrupt_handlers(void);
 
extern void enable_l_apic_in_msr(void);
 
 
extern void asm_delay_loop(uint32_t t);
extern void asm_fake_loop(uint32_t t);
 
 
/** Halt CPU
 *
 * Halt the current CPU until interrupt event.
 */
static inline void cpu_halt(void)
{
    asm volatile ("hlt\n");
}
 
static inline void cpu_sleep(void)
{
    asm volatile ("hlt\n");
}
 
#define GEN_READ_REG(reg) static inline unative_t read_ ##reg (void) \
    { \
    unative_t res; \
    asm volatile ("movl %%" #reg ", %0" : "=r" (res) ); \
    return res; \
    }
 
#define GEN_WRITE_REG(reg) static inline void write_ ##reg (unative_t regn) \
    { \
    asm volatile ("movl %0, %%" #reg : : "r" (regn)); \
    }
 
GEN_READ_REG(cr0)
GEN_READ_REG(cr2)
GEN_READ_REG(cr3)
GEN_WRITE_REG(cr3)
 
GEN_READ_REG(dr0)
GEN_READ_REG(dr1)
GEN_READ_REG(dr2)
GEN_READ_REG(dr3)
GEN_READ_REG(dr6)
GEN_READ_REG(dr7)
 
GEN_WRITE_REG(dr0)
GEN_WRITE_REG(dr1)
GEN_WRITE_REG(dr2)
GEN_WRITE_REG(dr3)
GEN_WRITE_REG(dr6)
GEN_WRITE_REG(dr7)
 
/** Byte to port
 *
 * Output byte to port
 *
 * @param port Port to write to
 * @param val Value to write
 */
static inline void outb(uint16_t port, uint8_t val)
{
    asm volatile ("outb %b0, %w1\n" : : "a" (val), "d" (port) );
}
 
/** Word to port
 *
 * Output word to port
 *
 * @param port Port to write to
 * @param val Value to write
 */
static inline void outw(uint16_t port, uint16_t val)
{
    asm volatile ("outw %w0, %w1\n" : : "a" (val), "d" (port) );
}
 
/** Double word to port
 *
 * Output double word to port
 *
 * @param port Port to write to
 * @param val Value to write
 */
static inline void outl(uint16_t port, uint32_t val)
{
    asm volatile ("outl %l0, %w1\n" : : "a" (val), "d" (port) );
}
 
/** Byte from port
 *
 * Get byte from port
 *
 * @param port Port to read from
 * @return Value read
 */
static inline uint8_t inb(uint16_t port)
{
    uint8_t val;
   
    asm volatile ("inb %w1, %b0 \n" : "=a" (val) : "d" (port) );
    return val;
}
 
/** Word from port
 *
 * Get word from port
 *
 * @param port Port to read from
 * @return Value read
 */
static inline uint16_t inw(uint16_t port)
{
    uint16_t val;
   
    asm volatile ("inw %w1, %w0 \n" : "=a" (val) : "d" (port) );
    return val;
}
 
/** Double word from port
 *
 * Get double word from port
 *
 * @param port Port to read from
 * @return Value read
 */
static inline uint32_t inl(uint16_t port)
{
    uint32_t val;
   
    asm volatile ("inl %w1, %l0 \n" : "=a" (val) : "d" (port) );
    return val;
}
 
/** Enable interrupts.
 *
 * Enable interrupts and return previous
 * value of EFLAGS.
 *
 * @return Old interrupt priority level.
 */
static inline ipl_t interrupts_enable(void)
{
    ipl_t v;
    asm volatile (
        "pushf\n\t"
        "popl %0\n\t"
        "sti\n"
        : "=r" (v)
    );
    return v;
}
 
/** Disable interrupts.
 *
 * Disable interrupts and return previous
 * value of EFLAGS.
 *
 * @return Old interrupt priority level.
 */
static inline ipl_t interrupts_disable(void)
{
    ipl_t v;
    asm volatile (
        "pushf\n\t"
        "popl %0\n\t"
        "cli\n"
        : "=r" (v)
    );
    return v;
}
 
/** Restore interrupt priority level.
 *
 * Restore EFLAGS.
 *
 * @param ipl Saved interrupt priority level.
 */
static inline void interrupts_restore(ipl_t ipl)
{
    asm volatile (
        "pushl %0\n\t"
        "popf\n"
        : : "r" (ipl)
    );
}
 
/** Return interrupt priority level.
 *
 * @return EFLAFS.
 */
static inline ipl_t interrupts_read(void)
{
    ipl_t v;
    asm volatile (
        "pushf\n\t"
        "popl %0\n"
        : "=r" (v)
    );
    return v;
}
 
/** Write to MSR */
static inline void write_msr(uint32_t msr, uint64_t value)
{
    asm volatile ("wrmsr" : : "c" (msr), "a" ((uint32_t)(value)),
        "d" ((uint32_t)(value >> 32)));
}
 
static inline uint64_t read_msr(uint32_t msr)
{
    uint32_t ax, dx;
 
    asm volatile ("rdmsr" : "=a"(ax), "=d"(dx) : "c" (msr));
    return ((uint64_t)dx << 32) | ax;
}
 
 
/** Return base address of current stack
 *
 * Return the base address of the current stack.
 * The stack is assumed to be STACK_SIZE bytes long.
 * The stack must start on page boundary.
 */
static inline uintptr_t get_stack_base(void)
{
    uintptr_t v;
   
    asm volatile (
        "andl %%esp, %0\n"
        : "=r" (v)
        : "0" (~(STACK_SIZE - 1))
    );
   
    return v;
}
 
/** Return current IP address */
static inline uintptr_t * get_ip()
{
    uintptr_t *ip;
 
    asm volatile (
        "mov %%eip, %0"
        : "=r" (ip)
        );
    return ip;
}
 
/** Invalidate TLB Entry.
 *
 * @param addr Address on a page whose TLB entry is to be invalidated.
 */
static inline void invlpg(uintptr_t addr)
{
    asm volatile ("invlpg %0\n" :: "m" (*(unative_t *)addr));
}
 
/** Load GDTR register from memory.
 *
 * @param gdtr_reg Address of memory from where to load GDTR.
 */
static inline void gdtr_load(ptr_16_32_t *gdtr_reg)
{
    asm volatile ("lgdtl %0\n" : : "m" (*gdtr_reg));
}
 
/** Store GDTR register to memory.
 *
 * @param gdtr_reg Address of memory to where to load GDTR.
 */
static inline void gdtr_store(ptr_16_32_t *gdtr_reg)
{
    asm volatile ("sgdtl %0\n" : : "m" (*gdtr_reg));
}
 
/** Load IDTR register from memory.
 *
 * @param idtr_reg Address of memory from where to load IDTR.
 */
static inline void idtr_load(ptr_16_32_t *idtr_reg)
{
    asm volatile ("lidtl %0\n" : : "m" (*idtr_reg));
}
 
/** Load TR from descriptor table.
 *
 * @param sel Selector specifying descriptor of TSS segment.
 */
static inline void tr_load(uint16_t sel)
{
    asm volatile ("ltr %0" : : "r" (sel));
}
 
#endif
 
/** @}
 */
 

Rev 2444	Rev 3485
1	/*	1	/*
2	* Copyright (c) 2001-2004 Jakub Jermar	2	* Copyright (c) 2001-2004 Jakub Jermar
3	* Copyright (c) 2005 Sergey Bondari	3	* Copyright (c) 2005 Sergey Bondari
4	* All rights reserved.	4	* All rights reserved.
5	*	5	*
6	* Redistribution and use in source and binary forms, with or without	6	* Redistribution and use in source and binary forms, with or without
7	* modification, are permitted provided that the following conditions	7	* modification, are permitted provided that the following conditions
8	* are met:	8	* are met:
9	*	9	*
10	* - Redistributions of source code must retain the above copyright	10	* - Redistributions of source code must retain the above copyright
11	* notice, this list of conditions and the following disclaimer.	11	* notice, this list of conditions and the following disclaimer.
12	* - Redistributions in binary form must reproduce the above copyright	12	* - Redistributions in binary form must reproduce the above copyright
13	* notice, this list of conditions and the following disclaimer in the	13	* notice, this list of conditions and the following disclaimer in the
14	* documentation and/or other materials provided with the distribution.	14	* documentation and/or other materials provided with the distribution.
15	* - The name of the author may not be used to endorse or promote products	15	* - The name of the author may not be used to endorse or promote products
16	* derived from this software without specific prior written permission.	16	* derived from this software without specific prior written permission.
17	*	17	*
18	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	18	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	19	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	20	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	21	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	22	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	23	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	24	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	25	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	26	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	27	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28	*/	28	*/
29		29
30	/** @addtogroup ia32	30	/** @addtogroup ia32
31	* @{	31	* @{
32	*/	32	*/
33	/** @file	33	/** @file
34	*/	34	*/
35		35
36	#ifndef KERN_ia32_ASM_H_	36	#ifndef KERN_ia32_ASM_H_
37	#define KERN_ia32_ASM_H_	37	#define KERN_ia32_ASM_H_
38		38
39	#include <arch/pm.h>	39	#include <arch/pm.h>
40	#include <arch/types.h>	40	#include <arch/types.h>
41	#include <config.h>	41	#include <config.h>
42		42
43	extern uint32_t interrupt_handler_size;	43	extern uint32_t interrupt_handler_size;
44		44
45	extern void paging_on(void);	45	extern void paging_on(void);
46		46
47	extern void interrupt_handlers(void);	47	extern void interrupt_handlers(void);
48		48
49	extern void enable_l_apic_in_msr(void);	49	extern void enable_l_apic_in_msr(void);
50		50
51		51
52	extern void asm_delay_loop(uint32_t t);	52	extern void asm_delay_loop(uint32_t t);
53	extern void asm_fake_loop(uint32_t t);	53	extern void asm_fake_loop(uint32_t t);
54		54
55		55
56	/** Halt CPU	56	/** Halt CPU
57	*	57	*
58	* Halt the current CPU until interrupt event.	58	* Halt the current CPU until interrupt event.
59	*/	59	*/
60	static inline void cpu_halt(void)	60	static inline void cpu_halt(void)
61	{	61	{
62	asm volatile ("hlt\n");	62	asm volatile ("hlt\n");
63	}	63	}
64		64
65	static inline void cpu_sleep(void)	65	static inline void cpu_sleep(void)
66	{	66	{
67	asm volatile ("hlt\n");	67	asm volatile ("hlt\n");
68	}	68	}
69		69
70	#define GEN_READ_REG(reg) static inline unative_t read_ ##reg (void) \	70	#define GEN_READ_REG(reg) static inline unative_t read_ ##reg (void) \
71	{ \	71	{ \
72	unative_t res; \	72	unative_t res; \
73	asm volatile ("movl %%" #reg ", %0" : "=r" (res) ); \	73	asm volatile ("movl %%" #reg ", %0" : "=r" (res) ); \
74	return res; \	74	return res; \
75	}	75	}
76		76
77	#define GEN_WRITE_REG(reg) static inline void write_ ##reg (unative_t regn) \	77	#define GEN_WRITE_REG(reg) static inline void write_ ##reg (unative_t regn) \
78	{ \	78	{ \
79	asm volatile ("movl %0, %%" #reg : : "r" (regn)); \	79	asm volatile ("movl %0, %%" #reg : : "r" (regn)); \
80	}	80	}
81		81
82	GEN_READ_REG(cr0)	82	GEN_READ_REG(cr0)
83	GEN_READ_REG(cr2)	83	GEN_READ_REG(cr2)
84	GEN_READ_REG(cr3)	84	GEN_READ_REG(cr3)
85	GEN_WRITE_REG(cr3)	85	GEN_WRITE_REG(cr3)
86		86
87	GEN_READ_REG(dr0)	87	GEN_READ_REG(dr0)
88	GEN_READ_REG(dr1)	88	GEN_READ_REG(dr1)
89	GEN_READ_REG(dr2)	89	GEN_READ_REG(dr2)
90	GEN_READ_REG(dr3)	90	GEN_READ_REG(dr3)
91	GEN_READ_REG(dr6)	91	GEN_READ_REG(dr6)
92	GEN_READ_REG(dr7)	92	GEN_READ_REG(dr7)
93		93
94	GEN_WRITE_REG(dr0)	94	GEN_WRITE_REG(dr0)
95	GEN_WRITE_REG(dr1)	95	GEN_WRITE_REG(dr1)
96	GEN_WRITE_REG(dr2)	96	GEN_WRITE_REG(dr2)
97	GEN_WRITE_REG(dr3)	97	GEN_WRITE_REG(dr3)
98	GEN_WRITE_REG(dr6)	98	GEN_WRITE_REG(dr6)
99	GEN_WRITE_REG(dr7)	99	GEN_WRITE_REG(dr7)
100		100
101	/** Byte to port	101	/** Byte to port
102	*	102	*
103	* Output byte to port	103	* Output byte to port
104	*	104	*
105	* @param port Port to write to	105	* @param port Port to write to
106	* @param val Value to write	106	* @param val Value to write
107	*/	107	*/
108	static inline void outb(uint16_t port, uint8_t val)	108	static inline void outb(uint16_t port, uint8_t val)
109	{	109	{
110	asm volatile ("outb %b0, %w1\n" : : "a" (val), "d" (port) );	110	asm volatile ("outb %b0, %w1\n" : : "a" (val), "d" (port) );
111	}	111	}
112		112
113	/** Word to port	113	/** Word to port
114	*	114	*
115	* Output word to port	115	* Output word to port
116	*	116	*
117	* @param port Port to write to	117	* @param port Port to write to
118	* @param val Value to write	118	* @param val Value to write
119	*/	119	*/
120	static inline void outw(uint16_t port, uint16_t val)	120	static inline void outw(uint16_t port, uint16_t val)
121	{	121	{
122	asm volatile ("outw %w0, %w1\n" : : "a" (val), "d" (port) );	122	asm volatile ("outw %w0, %w1\n" : : "a" (val), "d" (port) );
123	}	123	}
124		124
125	/** Double word to port	125	/** Double word to port
126	*	126	*
127	* Output double word to port	127	* Output double word to port
128	*	128	*
129	* @param port Port to write to	129	* @param port Port to write to
130	* @param val Value to write	130	* @param val Value to write
131	*/	131	*/
132	static inline void outl(uint16_t port, uint32_t val)	132	static inline void outl(uint16_t port, uint32_t val)
133	{	133	{
134	asm volatile ("outl %l0, %w1\n" : : "a" (val), "d" (port) );	134	asm volatile ("outl %l0, %w1\n" : : "a" (val), "d" (port) );
135	}	135	}
136		136
137	/** Byte from port	137	/** Byte from port
138	*	138	*
139	* Get byte from port	139	* Get byte from port
140	*	140	*
141	* @param port Port to read from	141	* @param port Port to read from
142	* @return Value read	142	* @return Value read
143	*/	143	*/
144	static inline uint8_t inb(uint16_t port)	144	static inline uint8_t inb(uint16_t port)
145	{	145	{
146	uint8_t val;	146	uint8_t val;
147		147
148	asm volatile ("inb %w1, %b0 \n" : "=a" (val) : "d" (port) );	148	asm volatile ("inb %w1, %b0 \n" : "=a" (val) : "d" (port) );
149	return val;	149	return val;
150	}	150	}
151		151
152	/** Word from port	152	/** Word from port
153	*	153	*
154	* Get word from port	154	* Get word from port
155	*	155	*
156	* @param port Port to read from	156	* @param port Port to read from
157	* @return Value read	157	* @return Value read
158	*/	158	*/
159	static inline uint16_t inw(uint16_t port)	159	static inline uint16_t inw(uint16_t port)
160	{	160	{
161	uint16_t val;	161	uint16_t val;
162		162
163	asm volatile ("inw %w1, %w0 \n" : "=a" (val) : "d" (port) );	163	asm volatile ("inw %w1, %w0 \n" : "=a" (val) : "d" (port) );
164	return val;	164	return val;
165	}	165	}
166		166
167	/** Double word from port	167	/** Double word from port
168	*	168	*
169	* Get double word from port	169	* Get double word from port
170	*	170	*
171	* @param port Port to read from	171	* @param port Port to read from
172	* @return Value read	172	* @return Value read
173	*/	173	*/
174	static inline uint32_t inl(uint16_t port)	174	static inline uint32_t inl(uint16_t port)
175	{	175	{
176	uint32_t val;	176	uint32_t val;
177		177
178	asm volatile ("inl %w1, %l0 \n" : "=a" (val) : "d" (port) );	178	asm volatile ("inl %w1, %l0 \n" : "=a" (val) : "d" (port) );
179	return val;	179	return val;
180	}	180	}
181		181
182	/** Enable interrupts.	182	/** Enable interrupts.
183	*	183	*
184	* Enable interrupts and return previous	184	* Enable interrupts and return previous
185	* value of EFLAGS.	185	* value of EFLAGS.
186	*	186	*
187	* @return Old interrupt priority level.	187	* @return Old interrupt priority level.
188	*/	188	*/
189	static inline ipl_t interrupts_enable(void)	189	static inline ipl_t interrupts_enable(void)
190	{	190	{
191	ipl_t v;	191	ipl_t v;
192	asm volatile (	192	asm volatile (
193	"pushf\n\t"	193	"pushf\n\t"
194	"popl %0\n\t"	194	"popl %0\n\t"
195	"sti\n"	195	"sti\n"
196	: "=r" (v)	196	: "=r" (v)
197	);	197	);
198	return v;	198	return v;
199	}	199	}
200		200
201	/** Disable interrupts.	201	/** Disable interrupts.
202	*	202	*
203	* Disable interrupts and return previous	203	* Disable interrupts and return previous
204	* value of EFLAGS.	204	* value of EFLAGS.
205	*	205	*
206	* @return Old interrupt priority level.	206	* @return Old interrupt priority level.
207	*/	207	*/
208	static inline ipl_t interrupts_disable(void)	208	static inline ipl_t interrupts_disable(void)
209	{	209	{
210	ipl_t v;	210	ipl_t v;
211	asm volatile (	211	asm volatile (
212	"pushf\n\t"	212	"pushf\n\t"
213	"popl %0\n\t"	213	"popl %0\n\t"
214	"cli\n"	214	"cli\n"
215	: "=r" (v)	215	: "=r" (v)
216	);	216	);
217	return v;	217	return v;
218	}	218	}
219		219
220	/** Restore interrupt priority level.	220	/** Restore interrupt priority level.
221	*	221	*
222	* Restore EFLAGS.	222	* Restore EFLAGS.
223	*	223	*
224	* @param ipl Saved interrupt priority level.	224	* @param ipl Saved interrupt priority level.
225	*/	225	*/
226	static inline void interrupts_restore(ipl_t ipl)	226	static inline void interrupts_restore(ipl_t ipl)
227	{	227	{
228	asm volatile (	228	asm volatile (
229	"pushl %0\n\t"	229	"pushl %0\n\t"
230	"popf\n"	230	"popf\n"
231	: : "r" (ipl)	231	: : "r" (ipl)
232	);	232	);
233	}	233	}
234		234
235	/** Return interrupt priority level.	235	/** Return interrupt priority level.
236	*	236	*
237	* @return EFLAFS.	237	* @return EFLAFS.
238	*/	238	*/
239	static inline ipl_t interrupts_read(void)	239	static inline ipl_t interrupts_read(void)
240	{	240	{
241	ipl_t v;	241	ipl_t v;
242	asm volatile (	242	asm volatile (
243	"pushf\n\t"	243	"pushf\n\t"
244	"popl %0\n"	244	"popl %0\n"
245	: "=r" (v)	245	: "=r" (v)
246	);	246	);
247	return v;	247	return v;
248	}	248	}
249		249
-		250	/** Write to MSR */
-		251	static inline void write_msr(uint32_t msr, uint64_t value)
-		252	{
-		253	asm volatile ("wrmsr" : : "c" (msr), "a" ((uint32_t)(value)),
-		254	"d" ((uint32_t)(value >> 32)));
-		255	}
-		256
-		257	static inline uint64_t read_msr(uint32_t msr)
-		258	{
-		259	uint32_t ax, dx;
-		260
-		261	asm volatile ("rdmsr" : "=a"(ax), "=d"(dx) : "c" (msr));
-		262	return ((uint64_t)dx << 32) \| ax;
-		263	}
-		264
-		265
250	/** Return base address of current stack	266	/** Return base address of current stack
251	*	267	*
252	* Return the base address of the current stack.	268	* Return the base address of the current stack.
253	* The stack is assumed to be STACK_SIZE bytes long.	269	* The stack is assumed to be STACK_SIZE bytes long.
254	* The stack must start on page boundary.	270	* The stack must start on page boundary.
255	*/	271	*/
256	static inline uintptr_t get_stack_base(void)	272	static inline uintptr_t get_stack_base(void)
257	{	273	{
258	uintptr_t v;	274	uintptr_t v;
259		275
260	asm volatile (	276	asm volatile (
261	"andl %%esp, %0\n"	277	"andl %%esp, %0\n"
262	: "=r" (v)	278	: "=r" (v)
263	: "0" (~(STACK_SIZE - 1))	279	: "0" (~(STACK_SIZE - 1))
264	);	280	);
265		281
266	return v;	282	return v;
267	}	283	}
268		284
269	/** Return current IP address */	285	/** Return current IP address */
270	static inline uintptr_t * get_ip()	286	static inline uintptr_t * get_ip()
271	{	287	{
272	uintptr_t *ip;	288	uintptr_t *ip;
273		289
274	asm volatile (	290	asm volatile (
275	"mov %%eip, %0"	291	"mov %%eip, %0"
276	: "=r" (ip)	292	: "=r" (ip)
277	);	293	);
278	return ip;	294	return ip;
279	}	295	}
280		296
281	/** Invalidate TLB Entry.	297	/** Invalidate TLB Entry.
282	*	298	*
283	* @param addr Address on a page whose TLB entry is to be invalidated.	299	* @param addr Address on a page whose TLB entry is to be invalidated.
284	*/	300	*/
285	static inline void invlpg(uintptr_t addr)	301	static inline void invlpg(uintptr_t addr)
286	{	302	{
287	asm volatile ("invlpg %0\n" :: "m" ((unative_t )addr));	303	asm volatile ("invlpg %0\n" :: "m" ((unative_t )addr));
288	}	304	}
289		305
290	/** Load GDTR register from memory.	306	/** Load GDTR register from memory.
291	*	307	*
292	* @param gdtr_reg Address of memory from where to load GDTR.	308	* @param gdtr_reg Address of memory from where to load GDTR.
293	*/	309	*/
294	static inline void gdtr_load(ptr_16_32_t *gdtr_reg)	310	static inline void gdtr_load(ptr_16_32_t *gdtr_reg)
295	{	311	{
296	asm volatile ("lgdtl %0\n" : : "m" (*gdtr_reg));	312	asm volatile ("lgdtl %0\n" : : "m" (*gdtr_reg));
297	}	313	}
298		314
299	/** Store GDTR register to memory.	315	/** Store GDTR register to memory.
300	*	316	*
301	* @param gdtr_reg Address of memory to where to load GDTR.	317	* @param gdtr_reg Address of memory to where to load GDTR.
302	*/	318	*/
303	static inline void gdtr_store(ptr_16_32_t *gdtr_reg)	319	static inline void gdtr_store(ptr_16_32_t *gdtr_reg)
304	{	320	{
305	asm volatile ("sgdtl %0\n" : : "m" (*gdtr_reg));	321	asm volatile ("sgdtl %0\n" : : "m" (*gdtr_reg));
306	}	322	}
307		323
308	/** Load IDTR register from memory.	324	/** Load IDTR register from memory.
309	*	325	*
310	* @param idtr_reg Address of memory from where to load IDTR.	326	* @param idtr_reg Address of memory from where to load IDTR.
311	*/	327	*/
312	static inline void idtr_load(ptr_16_32_t *idtr_reg)	328	static inline void idtr_load(ptr_16_32_t *idtr_reg)
313	{	329	{
314	asm volatile ("lidtl %0\n" : : "m" (*idtr_reg));	330	asm volatile ("lidtl %0\n" : : "m" (*idtr_reg));
315	}	331	}
316		332
317	/** Load TR from descriptor table.	333	/** Load TR from descriptor table.
318	*	334	*
319	* @param sel Selector specifying descriptor of TSS segment.	335	* @param sel Selector specifying descriptor of TSS segment.
320	*/	336	*/
321	static inline void tr_load(uint16_t sel)	337	static inline void tr_load(uint16_t sel)
322	{	338	{
323	asm volatile ("ltr %0" : : "r" (sel));	339	asm volatile ("ltr %0" : : "r" (sel));
324	}	340	}
325		341
326	#endif	342	#endif
327		343
328	/** @}	344	/** @}
329	*/	345	*/
330		346

Subversion Repositories HelenOS

(root)/trunk/kernel/arch/ia32/include/asm.h – Rev 2444 → 3485