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 * Halt the current CPU until interrupt event.
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 * Halt the current CPU until interrupt event.
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 */
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 */
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static inline void cpu_halt(void)
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static inline void cpu_halt(void)
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{
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{
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    asm volatile ("hlt\n");
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    asm volatile ("hlt\n");
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};
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}
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static inline void cpu_sleep(void)
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static inline void cpu_sleep(void)
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{
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{
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    asm volatile ("hlt\n");
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    asm volatile ("hlt\n");
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};
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}
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#define GEN_READ_REG(reg) static inline unative_t read_ ##reg (void) \
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#define GEN_READ_REG(reg) static inline unative_t read_ ##reg (void) \
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    { \
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    { \
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    unative_t res; \
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    unative_t res; \
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    asm volatile ("movl %%" #reg ", %0" : "=r" (res) ); \
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    asm volatile ("movl %%" #reg ", %0" : "=r" (res) ); \
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#define GEN_WRITE_REG(reg) static inline void write_ ##reg (unative_t regn) \
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#define GEN_WRITE_REG(reg) static inline void write_ ##reg (unative_t regn) \
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    { \
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    { \
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    asm volatile ("movl %0, %%" #reg : : "r" (regn)); \
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    asm volatile ("movl %0, %%" #reg : : "r" (regn)); \
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    }
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    }
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GEN_READ_REG(cr0);
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GEN_READ_REG(cr0)
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GEN_READ_REG(cr2);
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GEN_READ_REG(cr2)
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GEN_READ_REG(cr3);
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GEN_READ_REG(cr3)
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GEN_WRITE_REG(cr3);
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GEN_WRITE_REG(cr3)
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GEN_READ_REG(dr0);
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GEN_READ_REG(dr0)
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GEN_READ_REG(dr1);
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GEN_READ_REG(dr1)
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GEN_READ_REG(dr2);
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GEN_READ_REG(dr2)
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GEN_READ_REG(dr3);
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GEN_READ_REG(dr3)
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GEN_READ_REG(dr6);
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GEN_READ_REG(dr6)
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GEN_READ_REG(dr7);
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GEN_READ_REG(dr7)
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GEN_WRITE_REG(dr0);
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GEN_WRITE_REG(dr0)
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GEN_WRITE_REG(dr1);
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GEN_WRITE_REG(dr1)
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GEN_WRITE_REG(dr2);
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GEN_WRITE_REG(dr2)
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GEN_WRITE_REG(dr3);
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GEN_WRITE_REG(dr3)
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GEN_WRITE_REG(dr6);
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GEN_WRITE_REG(dr6)
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GEN_WRITE_REG(dr7);
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GEN_WRITE_REG(dr7)
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/** Byte to port
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/** Byte to port
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 *
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 *
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 * Output byte to port
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 * Output byte to port
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 *
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 *