WebSVN – HelenOS – Diff – /trunk/kernel/arch/ia32/include/asm.h

 /** Halt CPU
+ *
  * Halt the current CPU until interrupt event.
  */
-static inline void cpu_halt(void) { __asm__("hlt\n"); };
+static inline void cpu_halt(void)
+{
+    asm("hlt\n");
+};
-static inline void cpu_sleep(void) { __asm__("hlt\n"); };
+static inline void cpu_sleep(void)
+{
+    asm("hlt\n");
+};
 #define GEN_READ_REG(reg) static inline unative_t read_ ##reg (void) \
     { \
     unative_t res; \
-    __asm__ volatile ("movl %%" #reg ", %0" : "=r" (res) ); \
+    asm volatile ("movl %%" #reg ", %0" : "=r" (res) ); \
     return res; \
+    }
 #define GEN_WRITE_REG(reg) static inline void write_ ##reg (unative_t regn) \
     { \
-    __asm__ volatile ("movl %0, %%" #reg : : "r" (regn)); \
+    asm volatile ("movl %0, %%" #reg : : "r" (regn)); \
+    }
 GEN_READ_REG(cr0);
 GEN_READ_REG(cr2);
 GEN_READ_REG(cr3);
  * Output byte to port
+ *
  * @param port Port to write to
  * @param val Value to write
  */
+static inline void outb(uint16_t port, uint8_t val)
+{
-static inline void outb(uint16_t port, uint8_t val) { __asm__ volatile ("outb %b0, %w1\n" : : "a" (val), "d" (port) ); }
+    asm volatile ("outb %b0, %w1\n" : : "a" (val), "d" (port) );
+}
 /** Word to port
+ *
  * Output word to port
+ *
  * @param port Port to write to
  * @param val Value to write
  */
+static inline void outw(uint16_t port, uint16_t val)
+{
-static inline void outw(uint16_t port, uint16_t val) { __asm__ volatile ("outw %w0, %w1\n" : : "a" (val), "d" (port) ); }
+    asm volatile ("outw %w0, %w1\n" : : "a" (val), "d" (port) );
+}
 /** Double word to port
+ *
  * Output double word to port
+ *
  * @param port Port to write to
  * @param val Value to write
  */
+static inline void outl(uint16_t port, uint32_t val)
+{
-static inline void outl(uint16_t port, uint32_t val) { __asm__ volatile ("outl %l0, %w1\n" : : "a" (val), "d" (port) ); }
+    asm volatile ("outl %l0, %w1\n" : : "a" (val), "d" (port) );
+}
 /** Byte from port
+ *
  * Get byte from port
+ *
  * @param port Port to read from
  * @return Value read
  */
+static inline uint8_t inb(uint16_t port)
+{
+    uint8_t val;
-static inline uint8_t inb(uint16_t port) { uint8_t val; __asm__ volatile ("inb %w1, %b0 \n" : "=a" (val) : "d" (port) ); return val; }
+    asm volatile ("inb %w1, %b0 \n" : "=a" (val) : "d" (port) );
+    return val;
+}
 /** Word from port
+ *
  * Get word from port
+ *
  * @param port Port to read from
  * @return Value read
  */
+static inline uint16_t inw(uint16_t port)
+{
+    uint16_t val;
-static inline uint16_t inw(uint16_t port) { uint16_t val; __asm__ volatile ("inw %w1, %w0 \n" : "=a" (val) : "d" (port) ); return val; }
+    asm volatile ("inw %w1, %w0 \n" : "=a" (val) : "d" (port) );
+    return val;
+}
 /** Double word from port
+ *
  * Get double word from port
+ *
  * @param port Port to read from
  * @return Value read
  */
+static inline uint32_t inl(uint16_t port)
+{
+    uint32_t val;
-static inline uint32_t inl(uint16_t port) { uint32_t val; __asm__ volatile ("inl %w1, %l0 \n" : "=a" (val) : "d" (port) ); return val; }
+    asm volatile ("inl %w1, %l0 \n" : "=a" (val) : "d" (port) );
+    return val;
+}
 /** Enable interrupts.
+ *
  * Enable interrupts and return previous
  * value of EFLAGS.
  * @return Old interrupt priority level.
  */
 static inline ipl_t interrupts_enable(void)
+{
     ipl_t v;
-    __asm__ volatile (
+    asm volatile (
         "pushf\n\t"
         "popl %0\n\t"
         "sti\n"
         : "=r" (v)
     );
  * @return Old interrupt priority level.
  */
 static inline ipl_t interrupts_disable(void)
+{
     ipl_t v;
-    __asm__ volatile (
+    asm volatile (
         "pushf\n\t"
         "popl %0\n\t"
         "cli\n"
         : "=r" (v)
     );
+ *
  * @param ipl Saved interrupt priority level.
  */
 static inline void interrupts_restore(ipl_t ipl)
+{
-    __asm__ volatile (
+    asm volatile (
         "pushl %0\n\t"
         "popf\n"
         : : "r" (ipl)
     );
+}
  * @return EFLAFS.
  */
 static inline ipl_t interrupts_read(void)
+{
     ipl_t v;
-    __asm__ volatile (
+    asm volatile (
         "pushf\n\t"
         "popl %0\n"
         : "=r" (v)
     );
     return v;
  */
 static inline uintptr_t get_stack_base(void)
+{
     uintptr_t v;
-    __asm__ volatile ("andl %%esp, %0\n" : "=r" (v) : "0" (~(STACK_SIZE-1)));
+    asm volatile ("andl %%esp, %0\n" : "=r" (v) : "0" (~(STACK_SIZE-1)));
     return v;
+}
 /** Return current IP address */
 static inline uintptr_t * get_ip()
+{
     uintptr_t *ip;
-    __asm__ volatile (
+    asm volatile (
         "mov %%eip, %0"
         : "=r" (ip)
         );
     return ip;
+}
+ *
  * @param addr Address on a page whose TLB entry is to be invalidated.
  */
 static inline void invlpg(uintptr_t addr)
+{
-    __asm__ volatile ("invlpg %0\n" :: "m" (*(unative_t *)addr));
+    asm volatile ("invlpg %0\n" :: "m" (*(unative_t *)addr));
+}
 /** Load GDTR register from memory.
+ *
  * @param gdtr_reg Address of memory from where to load GDTR.
  */
 static inline void gdtr_load(ptr_16_32_t *gdtr_reg)
+{
-    __asm__ volatile ("lgdtl %0\n" : : "m" (*gdtr_reg));
+    asm volatile ("lgdtl %0\n" : : "m" (*gdtr_reg));
+}
 /** Store GDTR register to memory.
+ *
  * @param gdtr_reg Address of memory to where to load GDTR.
  */
 static inline void gdtr_store(ptr_16_32_t *gdtr_reg)
+{
-    __asm__ volatile ("sgdtl %0\n" : : "m" (*gdtr_reg));
+    asm volatile ("sgdtl %0\n" : : "m" (*gdtr_reg));
+}
 /** Load IDTR register from memory.
+ *
  * @param idtr_reg Address of memory from where to load IDTR.
  */
 static inline void idtr_load(ptr_16_32_t *idtr_reg)
+{
-    __asm__ volatile ("lidtl %0\n" : : "m" (*idtr_reg));
+    asm volatile ("lidtl %0\n" : : "m" (*idtr_reg));
+}
 /** Load TR from descriptor table.
+ *
  * @param sel Selector specifying descriptor of TSS segment.
  */
 static inline void tr_load(uint16_t sel)
+{
-    __asm__ volatile ("ltr %0" : : "r" (sel));
+    asm volatile ("ltr %0" : : "r" (sel));
+}
 #endif
 /** @}

Subversion Repositories HelenOS

(root)/trunk/kernel/arch/ia32/include/asm.h – Rev 2071 → 2082