WebSVN – HelenOS – Diff – /trunk/kernel/arch/arm32/src/exception.c


/*
 * Copyright (c) 2007 Petr Stepan
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup arm32
 * @{
 */
/** @file
 *  @brief Exception handlers and exception initialization routines.
 */
 
#include <arch/exception.h>
#include <arch/memstr.h>
#include <arch/regutils.h>
#include <interrupt.h>
#include <arch/mm/page_fault.h>
#include <arch/barrier.h>
 
#include <print.h>
#include <syscall/syscall.h>
 
#ifdef MACHINE_testarm
    #include <arch/mach/testarm/testarm.h>
#endif
 
#ifdef MACHINE_integratorcp
    #include <arch/mach/integratorcp/integratorcp.h>
#endif
 
/** Offset used in calculation of exception handler's relative address.
 *
 * @see install_handler()
 */
#define PREFETCH_OFFSET      0x8
 
/** LDR instruction's code */
#define LDR_OPCODE           0xe59ff000
 
/** Number of exception vectors. */
#define EXC_VECTORS          8
 
/** Size of memory block occupied by exception vectors. */
#define EXC_VECTORS_SIZE     (EXC_VECTORS * 4)
 
/** Updates specified exception vector to jump to given handler.
 *
 *  Addresses of handlers are stored in memory following exception vectors.
 */
static void install_handler(unsigned handler_addr, unsigned *vector)
{
    /* relative address (related to exc. vector) of the word
     * where handler's address is stored
    */
    volatile uint32_t handler_address_ptr = EXC_VECTORS_SIZE -
        PREFETCH_OFFSET;
   
    /* make it LDR instruction and store at exception vector */
    *vector = handler_address_ptr | LDR_OPCODE;
    smc_coherence(*vector);
   
    /* store handler's address */
    *(vector + EXC_VECTORS) = handler_addr;
 
}
 
/** Software Interrupt handler.
 *
 * Dispatches the syscall.
 */
static void swi_exception(int exc_no, istate_t *istate)
{
    istate->r0 = syscall_handler(istate->r0, istate->r1, istate->r2,
        istate->r3, istate->r4, istate->r5, istate->r6);
}
 
/** Fills exception vectors with appropriate exception handlers. */
void install_exception_handlers(void)
{
    install_handler((unsigned) reset_exception_entry,
        (unsigned *) EXC_RESET_VEC);
   
    install_handler((unsigned) undef_instr_exception_entry,
        (unsigned *) EXC_UNDEF_INSTR_VEC);
   
    install_handler((unsigned) swi_exception_entry,
        (unsigned *) EXC_SWI_VEC);
   
    install_handler((unsigned) prefetch_abort_exception_entry,
        (unsigned *) EXC_PREFETCH_ABORT_VEC);
   
    install_handler((unsigned) data_abort_exception_entry,
        (unsigned *) EXC_DATA_ABORT_VEC);
   
    install_handler((unsigned) irq_exception_entry,
        (unsigned *) EXC_IRQ_VEC);
   
    install_handler((unsigned) fiq_exception_entry,
        (unsigned *) EXC_FIQ_VEC);
}
 
#ifdef HIGH_EXCEPTION_VECTORS
/** Activates use of high exception vectors addresses. */
static void high_vectors(void)
{
    uint32_t control_reg;
   
    asm volatile (
        "mrc p15, 0, %[control_reg], c1, c1"
        : [control_reg] "=r" (control_reg)
    );
   
    /* switch on the high vectors bit */
    control_reg |= CP15_R1_HIGH_VECTORS_BIT;
   
    asm volatile (
        "mcr p15, 0, %[control_reg], c1, c1"
        :: [control_reg] "r" (control_reg)
    );
}
#endif
 
/** Interrupt Exception handler.
 *
 * Determines the sources of interrupt and calls their handlers.
 */
static void irq_exception(int exc_no, istate_t *istate)
{
    machine_irq_exception(exc_no, istate);
}
 
/** Initializes exception handling.
 *
 * Installs low-level exception handlers and then registers
 * exceptions and their handlers to kernel exception dispatcher.
 */
void exception_init(void)
{
#ifdef HIGH_EXCEPTION_VECTORS
    high_vectors();
#endif
    install_exception_handlers();
   
    exc_register(EXC_IRQ, "interrupt", (iroutine) irq_exception);
    exc_register(EXC_PREFETCH_ABORT, "prefetch abort",
        (iroutine) prefetch_abort);
    exc_register(EXC_DATA_ABORT, "data abort", (iroutine) data_abort);
    exc_register(EXC_SWI, "software interrupt", (iroutine) swi_exception);
}
 
/** Prints #istate_t structure content.
 *
 * @param istate Structure to be printed.
 */
void print_istate(istate_t *istate)
{
    printf("istate dump:\n");
   
    printf(" r0: %x    r1: %x    r2: %x    r3: %x\n",
        istate->r0, istate->r1, istate->r2, istate->r3);
    printf(" r4: %x    r5: %x    r6: %x    r7: %x\n",
        istate->r4, istate->r5, istate->r6, istate->r7);
    printf(" r8: %x    r8: %x   r10: %x   r11: %x\n",
        istate->r8, istate->r9, istate->r10, istate->r11);
    printf(" r12: %x    sp: %x    lr: %x  spsr: %x\n",
        istate->r12, istate->sp, istate->lr, istate->spsr);
   
    printf(" pc: %x\n", istate->pc);
}
 
/** @}
 */
 

Subversion Repositories HelenOS

(root)/trunk/kernel/arch/arm32/src/exception.c – Rev 4669 → 4675

Rev 4669		Rev 4675
1	/*	1	/*
2	* Copyright (c) 2007 Petr Stepan	2	* Copyright (c) 2007 Petr Stepan
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	/** @addtogroup arm32	29	/** @addtogroup arm32
30	* @{	30	* @{
31	*/	31	*/
32	/** @file	32	/** @file
33	* @brief Exception handlers and exception initialization routines.	33	* @brief Exception handlers and exception initialization routines.
34	*/	34	*/
35		35
36	#include <arch/exception.h>	36	#include <arch/exception.h>
37	#include <arch/memstr.h>	37	#include <arch/memstr.h>
38	#include <arch/regutils.h>	38	#include <arch/regutils.h>
39	#include <interrupt.h>	39	#include <interrupt.h>
40	#include <arch/mm/page_fault.h>	40	#include <arch/mm/page_fault.h>
41	#include <arch/barrier.h>	41	#include <arch/barrier.h>
42	#include <arch/machine.h>	-
43	#include <print.h>	42	#include <print.h>
44	#include <syscall/syscall.h>	43	#include <syscall/syscall.h>
45		44
-		45	#ifdef MACHINE_testarm
-		46	#include <arch/mach/testarm/testarm.h>
-		47	#endif
-		48
-		49	#ifdef MACHINE_integratorcp
-		50	#include <arch/mach/integratorcp/integratorcp.h>
-		51	#endif
-		52
46	/** Offset used in calculation of exception handler's relative address.	53	/** Offset used in calculation of exception handler's relative address.
47	*	54	*
48	* @see install_handler()	55	* @see install_handler()
49	*/	56	*/
50	#define PREFETCH_OFFSET 0x8	57	#define PREFETCH_OFFSET 0x8
51		58
52	/** LDR instruction's code */	59	/** LDR instruction's code */
53	#define LDR_OPCODE 0xe59ff000	60	#define LDR_OPCODE 0xe59ff000
54		61
55	/** Number of exception vectors. */	62	/** Number of exception vectors. */
56	#define EXC_VECTORS 8	63	#define EXC_VECTORS 8
57		64
58	/** Size of memory block occupied by exception vectors. */	65	/** Size of memory block occupied by exception vectors. */
59	#define EXC_VECTORS_SIZE (EXC_VECTORS * 4)	66	#define EXC_VECTORS_SIZE (EXC_VECTORS * 4)
60		67
61	/** Updates specified exception vector to jump to given handler.	68	/** Updates specified exception vector to jump to given handler.
62	*	69	*
63	* Addresses of handlers are stored in memory following exception vectors.	70	* Addresses of handlers are stored in memory following exception vectors.
64	*/	71	*/
65	static void install_handler(unsigned handler_addr, unsigned *vector)	72	static void install_handler(unsigned handler_addr, unsigned *vector)
66	{	73	{
67	/* relative address (related to exc. vector) of the word	74	/* relative address (related to exc. vector) of the word
68	* where handler's address is stored	75	* where handler's address is stored
69	*/	76	*/
70	volatile uint32_t handler_address_ptr = EXC_VECTORS_SIZE -	77	volatile uint32_t handler_address_ptr = EXC_VECTORS_SIZE -
71	PREFETCH_OFFSET;	78	PREFETCH_OFFSET;
72		79
73	/* make it LDR instruction and store at exception vector */	80	/* make it LDR instruction and store at exception vector */
74	*vector = handler_address_ptr \| LDR_OPCODE;	81	*vector = handler_address_ptr \| LDR_OPCODE;
75	smc_coherence(*vector);	82	smc_coherence(*vector);
76		83
77	/* store handler's address */	84	/* store handler's address */
78	*(vector + EXC_VECTORS) = handler_addr;	85	*(vector + EXC_VECTORS) = handler_addr;
79		86
80	}	87	}
81		88
82	/** Software Interrupt handler.	89	/** Software Interrupt handler.
83	*	90	*
84	* Dispatches the syscall.	91	* Dispatches the syscall.
85	*/	92	*/
86	static void swi_exception(int exc_no, istate_t *istate)	93	static void swi_exception(int exc_no, istate_t *istate)
87	{	94	{
88	istate->r0 = syscall_handler(istate->r0, istate->r1, istate->r2,	95	istate->r0 = syscall_handler(istate->r0, istate->r1, istate->r2,
89	istate->r3, istate->r4, istate->r5, istate->r6);	96	istate->r3, istate->r4, istate->r5, istate->r6);
90	}	97	}
91		98
92	/** Fills exception vectors with appropriate exception handlers. */	99	/** Fills exception vectors with appropriate exception handlers. */
93	void install_exception_handlers(void)	100	void install_exception_handlers(void)
94	{	101	{
95	install_handler((unsigned) reset_exception_entry,	102	install_handler((unsigned) reset_exception_entry,
96	(unsigned *) EXC_RESET_VEC);	103	(unsigned *) EXC_RESET_VEC);
97		104
98	install_handler((unsigned) undef_instr_exception_entry,	105	install_handler((unsigned) undef_instr_exception_entry,
99	(unsigned *) EXC_UNDEF_INSTR_VEC);	106	(unsigned *) EXC_UNDEF_INSTR_VEC);
100		107
101	install_handler((unsigned) swi_exception_entry,	108	install_handler((unsigned) swi_exception_entry,
102	(unsigned *) EXC_SWI_VEC);	109	(unsigned *) EXC_SWI_VEC);
103		110
104	install_handler((unsigned) prefetch_abort_exception_entry,	111	install_handler((unsigned) prefetch_abort_exception_entry,
105	(unsigned *) EXC_PREFETCH_ABORT_VEC);	112	(unsigned *) EXC_PREFETCH_ABORT_VEC);
106		113
107	install_handler((unsigned) data_abort_exception_entry,	114	install_handler((unsigned) data_abort_exception_entry,
108	(unsigned *) EXC_DATA_ABORT_VEC);	115	(unsigned *) EXC_DATA_ABORT_VEC);
109		116
110	install_handler((unsigned) irq_exception_entry,	117	install_handler((unsigned) irq_exception_entry,
111	(unsigned *) EXC_IRQ_VEC);	118	(unsigned *) EXC_IRQ_VEC);
112		119
113	install_handler((unsigned) fiq_exception_entry,	120	install_handler((unsigned) fiq_exception_entry,
114	(unsigned *) EXC_FIQ_VEC);	121	(unsigned *) EXC_FIQ_VEC);
115	}	122	}
116		123
117	#ifdef HIGH_EXCEPTION_VECTORS	124	#ifdef HIGH_EXCEPTION_VECTORS
118	/** Activates use of high exception vectors addresses. */	125	/** Activates use of high exception vectors addresses. */
119	static void high_vectors(void)	126	static void high_vectors(void)
120	{	127	{
121	uint32_t control_reg;	128	uint32_t control_reg;
122		129
123	asm volatile (	130	asm volatile (
124	"mrc p15, 0, %[control_reg], c1, c1"	131	"mrc p15, 0, %[control_reg], c1, c1"
125	: [control_reg] "=r" (control_reg)	132	: [control_reg] "=r" (control_reg)
126	);	133	);
127		134
128	/* switch on the high vectors bit */	135	/* switch on the high vectors bit */
129	control_reg \|= CP15_R1_HIGH_VECTORS_BIT;	136	control_reg \|= CP15_R1_HIGH_VECTORS_BIT;
130		137
131	asm volatile (	138	asm volatile (
132	"mcr p15, 0, %[control_reg], c1, c1"	139	"mcr p15, 0, %[control_reg], c1, c1"
133	:: [control_reg] "r" (control_reg)	140	:: [control_reg] "r" (control_reg)
134	);	141	);
135	}	142	}
136	#endif	143	#endif
137		144
138	/** Interrupt Exception handler.	145	/** Interrupt Exception handler.
139	*	146	*
140	* Determines the sources of interrupt and calls their handlers.	147	* Determines the sources of interrupt and calls their handlers.
141	*/	148	*/
142	static void irq_exception(int exc_no, istate_t *istate)	149	static void irq_exception(int exc_no, istate_t *istate)
143	{	150	{
144	machine_irq_exception(exc_no, istate);	151	machine_irq_exception(exc_no, istate);
145	}	152	}
146		153
147	/** Initializes exception handling.	154	/** Initializes exception handling.
148	*	155	*
149	* Installs low-level exception handlers and then registers	156	* Installs low-level exception handlers and then registers
150	* exceptions and their handlers to kernel exception dispatcher.	157	* exceptions and their handlers to kernel exception dispatcher.
151	*/	158	*/
152	void exception_init(void)	159	void exception_init(void)
153	{	160	{
154	#ifdef HIGH_EXCEPTION_VECTORS	161	#ifdef HIGH_EXCEPTION_VECTORS
155	high_vectors();	162	high_vectors();
156	#endif	163	#endif
157	install_exception_handlers();	164	install_exception_handlers();
158		165
159	exc_register(EXC_IRQ, "interrupt", (iroutine) irq_exception);	166	exc_register(EXC_IRQ, "interrupt", (iroutine) irq_exception);
160	exc_register(EXC_PREFETCH_ABORT, "prefetch abort",	167	exc_register(EXC_PREFETCH_ABORT, "prefetch abort",
161	(iroutine) prefetch_abort);	168	(iroutine) prefetch_abort);
162	exc_register(EXC_DATA_ABORT, "data abort", (iroutine) data_abort);	169	exc_register(EXC_DATA_ABORT, "data abort", (iroutine) data_abort);
163	exc_register(EXC_SWI, "software interrupt", (iroutine) swi_exception);	170	exc_register(EXC_SWI, "software interrupt", (iroutine) swi_exception);
164	}	171	}
165		172
166	/** Prints #istate_t structure content.	173	/** Prints #istate_t structure content.
167	*	174	*
168	* @param istate Structure to be printed.	175	* @param istate Structure to be printed.
169	*/	176	*/
170	void print_istate(istate_t *istate)	177	void print_istate(istate_t *istate)
171	{	178	{
172	printf("istate dump:\n");	179	printf("istate dump:\n");
173		180
174	printf(" r0: %x r1: %x r2: %x r3: %x\n",	181	printf(" r0: %x r1: %x r2: %x r3: %x\n",
175	istate->r0, istate->r1, istate->r2, istate->r3);	182	istate->r0, istate->r1, istate->r2, istate->r3);
176	printf(" r4: %x r5: %x r6: %x r7: %x\n",	183	printf(" r4: %x r5: %x r6: %x r7: %x\n",
177	istate->r4, istate->r5, istate->r6, istate->r7);	184	istate->r4, istate->r5, istate->r6, istate->r7);
178	printf(" r8: %x r8: %x r10: %x r11: %x\n",	185	printf(" r8: %x r8: %x r10: %x r11: %x\n",
179	istate->r8, istate->r9, istate->r10, istate->r11);	186	istate->r8, istate->r9, istate->r10, istate->r11);
180	printf(" r12: %x sp: %x lr: %x spsr: %x\n",	187	printf(" r12: %x sp: %x lr: %x spsr: %x\n",
181	istate->r12, istate->sp, istate->lr, istate->spsr);	188	istate->r12, istate->sp, istate->lr, istate->spsr);
182		189
183	printf(" pc: %x\n", istate->pc);	190	printf(" pc: %x\n", istate->pc);
184	}	191	}
185		192
186	/** @}	193	/** @}
187	*/	194	*/
188		195