WebSVN – HelenOS – Diff – /trunk/kernel/arch/arm32/include/regutils.h


/*
 * Copyright (c) 2007 Petr Stepan
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup arm32  
 * @{
 */
/**
 * @file
 * @brief Utilities for convenient manipulation with ARM registers.
 */
 
#ifndef KERN_arm32_REGUTILS_H_
#define KERN_arm32_REGUTILS_H_
 
#define STATUS_REG_IRQ_DISABLED_BIT (1 << 7)
#define STATUS_REG_MODE_MASK        0x1f
 
#define CP15_R1_HIGH_VECTORS_BIT    (1 << 13)
 
 
/* ARM Processor Operation Modes */
#define USER_MODE         0x10
#define FIQ_MODE          0x11
#define IRQ_MODE          0x12
#define SUPERVISOR_MODE   0x13
#define ABORT_MODE        0x17
#define UNDEFINED_MODE    0x1b
#define SYSTEM_MODE       0x1f
 
/* [CS]PRS manipulation macros */
#define GEN_STATUS_READ(nm,reg) \
static inline uint32_t nm## _status_reg_read(void) \
{ \
    uint32_t retval; \
    asm volatile("mrs %0, " #reg : "=r" (retval)); \
    return retval; \
}
 
#define GEN_STATUS_WRITE(nm,reg,fieldname, field) \
static inline void nm## _status_reg_ ##fieldname## _write(uint32_t value) \
{ \
    asm volatile("msr " #reg "_" #field ", %0" : : "r" (value)); \
}
 
 
/** Returns the value of CPSR (Current Program Status Register). */
GEN_STATUS_READ(current, cpsr)
 
 
/** Sets control bits of CPSR. */
GEN_STATUS_WRITE(current, cpsr, control, c);
 
 
/** Returns the value of SPSR (Saved Program Status Register). */
GEN_STATUS_READ(saved, spsr)
 
 
#endif
 
/** @}
 */
 

Subversion Repositories HelenOS

(root)/trunk/kernel/arch/arm32/include/regutils.h – Rev 2464 → 2465

Rev 2464		Rev 2465
1	/*	1	/*
2	* Copyright (c) 2007 Petr Stepan	2	* Copyright (c) 2007 Petr Stepan
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	/** @addtogroup arm32	29	/** @addtogroup arm32
30	* @{	30	* @{
31	*/	31	*/
32	/**	32	/**
33	* @file	33	* @file
34	* @brief Utilities for convenient manipulation with ARM registers.	34	* @brief Utilities for convenient manipulation with ARM registers.
35	*/	35	*/
36		36
37	#ifndef KERN_arm32_REGUTILS_H_	37	#ifndef KERN_arm32_REGUTILS_H_
38	#define KERN_arm32_REGUTILS_H_	38	#define KERN_arm32_REGUTILS_H_
39		39
40	#define STATUS_REG_IRQ_DISABLED_BIT (1 << 7)	40	#define STATUS_REG_IRQ_DISABLED_BIT (1 << 7)
41	#define STATUS_REG_MODE_MASK 0x1f	41	#define STATUS_REG_MODE_MASK 0x1f
42		42
43	#define CP15_R1_HIGH_VECTORS_BIT (1 << 13)	43	#define CP15_R1_HIGH_VECTORS_BIT (1 << 13)
44		44
45		45
46	/* ARM Processor Operation Modes */	46	/* ARM Processor Operation Modes */
47	#define USER_MODE 0x10	47	#define USER_MODE 0x10
48	#define FIQ_MODE 0x11	48	#define FIQ_MODE 0x11
49	#define IRQ_MODE 0x12	49	#define IRQ_MODE 0x12
50	#define SUPERVISOR_MODE 0x13	50	#define SUPERVISOR_MODE 0x13
51	#define ABORT_MODE 0x17	51	#define ABORT_MODE 0x17
52	#define UNDEFINED_MODE 0x1b	52	#define UNDEFINED_MODE 0x1b
53	#define SYSTEM_MODE 0x1f	53	#define SYSTEM_MODE 0x1f
54		54
55	/* [CS]PRS manipulation macros */	55	/* [CS]PRS manipulation macros */
56	#define GEN_STATUS_READ(nm,reg) \	56	#define GEN_STATUS_READ(nm,reg) \
57	static inline uint32_t nm## _status_reg_read(void) \	57	static inline uint32_t nm## _status_reg_read(void) \
58	{ \	58	{ \
59	uint32_t retval; \	59	uint32_t retval; \
60	asm volatile("mrs %0, " #reg : "=r" (retval)); \	60	asm volatile("mrs %0, " #reg : "=r" (retval)); \
61	return retval; \	61	return retval; \
62	}	62	}
63		63
64	#define GEN_STATUS_WRITE(nm,reg,fieldname, field) \	64	#define GEN_STATUS_WRITE(nm,reg,fieldname, field) \
65	static inline void nm## _status_reg_ ##fieldname## _write(uint32_t value) \	65	static inline void nm## _status_reg_ ##fieldname## _write(uint32_t value) \
66	{ \	66	{ \
67	asm volatile("msr " #reg "_" #field ", %0" : : "r" (value)); \	67	asm volatile("msr " #reg "_" #field ", %0" : : "r" (value)); \
68	}	68	}
69		69
70		70
71	/** Returns the value of CPSR (Current Program Status Register). */	71	/** Returns the value of CPSR (Current Program Status Register). */
72	GEN_STATUS_READ(current, cpsr)	72	GEN_STATUS_READ(current, cpsr)
73		73
74		74
75	/** Sets control bits of CPSR. */	75	/** Sets control bits of CPSR. */
76	GEN_STATUS_WRITE(current, cpsr, control, c);	76	GEN_STATUS_WRITE(current, cpsr, control, c);
77		77
78		78
79	/** Returns the value of SPSR (Saved Program Status Register). */	79	/** Returns the value of SPSR (Saved Program Status Register). */
80	GEN_STATUS_READ(saved, spsr)	80	GEN_STATUS_READ(saved, spsr)
81		81
82		82
83	#endif	83	#endif
84		84
85	/** @}	85	/** @}
86	*/	86	*/
87		87