WebSVN – HelenOS – Diff – /trunk/kernel/arch/amd64/include/interrupt.h


/*
 * Copyright (c) 2001-2004 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup amd64interrupt
 * @{
 */
/** @file
 */
 
#ifndef KERN_amd64_INTERRUPT_H_
#define KERN_amd64_INTERRUPT_H_
 
#include <arch/types.h>
#include <arch/pm.h>
 
#define IVT_ITEMS       IDT_ITEMS
#define IVT_FIRST       0
 
#define EXC_COUNT   32
#define IRQ_COUNT   16
 
#define IVT_EXCBASE     0
#define IVT_IRQBASE     (IVT_EXCBASE + EXC_COUNT)
#define IVT_FREEBASE    (IVT_IRQBASE + IRQ_COUNT)
 
#define IRQ_CLK         0
#define IRQ_KBD         1
#define IRQ_PIC1        2
#define IRQ_PIC_SPUR    7
#define IRQ_MOUSE       12
 
/* this one must have four least significant bits set to ones */
#define VECTOR_APIC_SPUR    (IVT_ITEMS - 1)
 
#if (((VECTOR_APIC_SPUR + 1) % 16) || VECTOR_APIC_SPUR >= IVT_ITEMS)
#error Wrong definition of VECTOR_APIC_SPUR
#endif
 
#define VECTOR_DEBUG                1
#define VECTOR_CLK                  (IVT_IRQBASE + IRQ_CLK)
#define VECTOR_PIC_SPUR             (IVT_IRQBASE + IRQ_PIC_SPUR)
#define VECTOR_SYSCALL              IVT_FREEBASE
#define VECTOR_TLB_SHOOTDOWN_IPI    (IVT_FREEBASE + 1)
#define VECTOR_DEBUG_IPI            (IVT_FREEBASE + 2)
 
/** This is passed to interrupt handlers */
struct istate {
    uint64_t rax;
    uint64_t rbx;
    uint64_t rcx;
    uint64_t rdx;
    uint64_t rsi;
    uint64_t rdi;
    uint64_t r8;
    uint64_t r9;
    uint64_t r10;
    uint64_t r11;
    uint64_t r12;
    uint64_t r13;
    uint64_t r14;
    uint64_t r15;
    uint64_t rbp;
    uint64_t error_word;
    uint64_t rip;
    uint64_t cs;
    uint64_t rflags;
    uint64_t stack[]; /* Additional data on stack */
};
 
/** Return true if exception happened while in userspace */
static inline int istate_from_uspace(istate_t *istate)
{
    return !(istate->rip & 0x8000000000000000);
}
 
static inline void istate_set_retaddr(istate_t *istate, uintptr_t retaddr)
{
    istate->rip = retaddr;
}
static inline unative_t istate_get_pc(istate_t *istate)
{
    return istate->rip;
}
 
extern void (* disable_irqs_function)(uint16_t irqmask);
extern void (* enable_irqs_function)(uint16_t irqmask);
extern void (* eoi_function)(void);
 
extern void decode_istate(int n, istate_t *istate);
extern void interrupt_init(void);
extern void trap_virtual_enable_irqs(uint16_t irqmask);
extern void trap_virtual_disable_irqs(uint16_t irqmask);
/* AMD64 - specific page handler */
extern void ident_page_fault(int n, istate_t *istate);
 
#endif
 
/** @}
 */
 

Rev 1958	Rev 2071
1	/*	1	/*
2	* Copyright (C) 2001-2004 Jakub Jermar	2	* Copyright (c) 2001-2004 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	/** @addtogroup amd64interrupt	29	/** @addtogroup amd64interrupt
30	* @{	30	* @{
31	*/	31	*/
32	/** @file	32	/** @file
33	*/	33	*/
34		34
35	#ifndef KERN_amd64_INTERRUPT_H_	35	#ifndef KERN_amd64_INTERRUPT_H_
36	#define KERN_amd64_INTERRUPT_H_	36	#define KERN_amd64_INTERRUPT_H_
37		37
38	#include <arch/types.h>	38	#include <arch/types.h>
39	#include <arch/pm.h>	39	#include <arch/pm.h>
40		40
41	#define IVT_ITEMS IDT_ITEMS	41	#define IVT_ITEMS IDT_ITEMS
42	#define IVT_FIRST 0	42	#define IVT_FIRST 0
43		43
44	#define EXC_COUNT 32	44	#define EXC_COUNT 32
45	#define IRQ_COUNT 16	45	#define IRQ_COUNT 16
46		46
47	#define IVT_EXCBASE 0	47	#define IVT_EXCBASE 0
48	#define IVT_IRQBASE (IVT_EXCBASE + EXC_COUNT)	48	#define IVT_IRQBASE (IVT_EXCBASE + EXC_COUNT)
49	#define IVT_FREEBASE (IVT_IRQBASE + IRQ_COUNT)	49	#define IVT_FREEBASE (IVT_IRQBASE + IRQ_COUNT)
50		50
51	#define IRQ_CLK 0	51	#define IRQ_CLK 0
52	#define IRQ_KBD 1	52	#define IRQ_KBD 1
53	#define IRQ_PIC1 2	53	#define IRQ_PIC1 2
54	#define IRQ_PIC_SPUR 7	54	#define IRQ_PIC_SPUR 7
55	#define IRQ_MOUSE 12	55	#define IRQ_MOUSE 12
56		56
57	/* this one must have four least significant bits set to ones */	57	/* this one must have four least significant bits set to ones */
58	#define VECTOR_APIC_SPUR (IVT_ITEMS - 1)	58	#define VECTOR_APIC_SPUR (IVT_ITEMS - 1)
59		59
60	#if (((VECTOR_APIC_SPUR + 1) % 16) \|\| VECTOR_APIC_SPUR >= IVT_ITEMS)	60	#if (((VECTOR_APIC_SPUR + 1) % 16) \|\| VECTOR_APIC_SPUR >= IVT_ITEMS)
61	#error Wrong definition of VECTOR_APIC_SPUR	61	#error Wrong definition of VECTOR_APIC_SPUR
62	#endif	62	#endif
63		63
64	#define VECTOR_DEBUG 1	64	#define VECTOR_DEBUG 1
65	#define VECTOR_CLK (IVT_IRQBASE + IRQ_CLK)	65	#define VECTOR_CLK (IVT_IRQBASE + IRQ_CLK)
66	#define VECTOR_PIC_SPUR (IVT_IRQBASE + IRQ_PIC_SPUR)	66	#define VECTOR_PIC_SPUR (IVT_IRQBASE + IRQ_PIC_SPUR)
67	#define VECTOR_SYSCALL IVT_FREEBASE	67	#define VECTOR_SYSCALL IVT_FREEBASE
68	#define VECTOR_TLB_SHOOTDOWN_IPI (IVT_FREEBASE + 1)	68	#define VECTOR_TLB_SHOOTDOWN_IPI (IVT_FREEBASE + 1)
69	#define VECTOR_DEBUG_IPI (IVT_FREEBASE + 2)	69	#define VECTOR_DEBUG_IPI (IVT_FREEBASE + 2)
70		70
71	/** This is passed to interrupt handlers */	71	/** This is passed to interrupt handlers */
72	struct istate {	72	struct istate {
73	uint64_t rax;	73	uint64_t rax;
74	uint64_t rbx;	74	uint64_t rbx;
75	uint64_t rcx;	75	uint64_t rcx;
76	uint64_t rdx;	76	uint64_t rdx;
77	uint64_t rsi;	77	uint64_t rsi;
78	uint64_t rdi;	78	uint64_t rdi;
79	uint64_t r8;	79	uint64_t r8;
80	uint64_t r9;	80	uint64_t r9;
81	uint64_t r10;	81	uint64_t r10;
82	uint64_t r11;	82	uint64_t r11;
83	uint64_t r12;	83	uint64_t r12;
84	uint64_t r13;	84	uint64_t r13;
85	uint64_t r14;	85	uint64_t r14;
86	uint64_t r15;	86	uint64_t r15;
87	uint64_t rbp;	87	uint64_t rbp;
88	uint64_t error_word;	88	uint64_t error_word;
89	uint64_t rip;	89	uint64_t rip;
90	uint64_t cs;	90	uint64_t cs;
91	uint64_t rflags;	91	uint64_t rflags;
92	uint64_t stack[]; /* Additional data on stack */	92	uint64_t stack[]; /* Additional data on stack */
93	};	93	};
94		94
95	/** Return true if exception happened while in userspace */	95	/** Return true if exception happened while in userspace */
96	static inline int istate_from_uspace(istate_t *istate)	96	static inline int istate_from_uspace(istate_t *istate)
97	{	97	{
98	return !(istate->rip & 0x8000000000000000);	98	return !(istate->rip & 0x8000000000000000);
99	}	99	}
100		100
101	static inline void istate_set_retaddr(istate_t *istate, uintptr_t retaddr)	101	static inline void istate_set_retaddr(istate_t *istate, uintptr_t retaddr)
102	{	102	{
103	istate->rip = retaddr;	103	istate->rip = retaddr;
104	}	104	}
105	static inline unative_t istate_get_pc(istate_t *istate)	105	static inline unative_t istate_get_pc(istate_t *istate)
106	{	106	{
107	return istate->rip;	107	return istate->rip;
108	}	108	}
109		109
110	extern void (* disable_irqs_function)(uint16_t irqmask);	110	extern void (* disable_irqs_function)(uint16_t irqmask);
111	extern void (* enable_irqs_function)(uint16_t irqmask);	111	extern void (* enable_irqs_function)(uint16_t irqmask);
112	extern void (* eoi_function)(void);	112	extern void (* eoi_function)(void);
113		113
114	extern void decode_istate(int n, istate_t *istate);	114	extern void decode_istate(int n, istate_t *istate);
115	extern void interrupt_init(void);	115	extern void interrupt_init(void);
116	extern void trap_virtual_enable_irqs(uint16_t irqmask);	116	extern void trap_virtual_enable_irqs(uint16_t irqmask);
117	extern void trap_virtual_disable_irqs(uint16_t irqmask);	117	extern void trap_virtual_disable_irqs(uint16_t irqmask);
118	/* AMD64 - specific page handler */	118	/* AMD64 - specific page handler */
119	extern void ident_page_fault(int n, istate_t *istate);	119	extern void ident_page_fault(int n, istate_t *istate);
120		120
121	#endif	121	#endif
122		122
123	/** @}	123	/** @}
124	*/	124	*/
125		125

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(root)/trunk/kernel/arch/amd64/include/interrupt.h – Rev 1958 → 2071