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Rev 3855 Rev 3856
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#
 1 
#
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# Copyright (c) 2006 Martin Decky
 2 
# Copyright (c) 2006 Martin Decky
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# All rights reserved.
 3 
# All rights reserved.
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#
 4 
#
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# Redistribution and use in source and binary forms, with or without
 5 
# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions
 6 
# modification, are permitted provided that the following conditions
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# are met:
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# are met:
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#
 8 
#
9 
# - Redistributions of source code must retain the above copyright
 9 
# - Redistributions of source code must retain the above copyright
10 
#   notice, this list of conditions and the following disclaimer.
 10 
#   notice, this list of conditions and the following disclaimer.
11 
# - Redistributions in binary form must reproduce the above copyright
 11 
# - Redistributions in binary form must reproduce the above copyright
12 
#   notice, this list of conditions and the following disclaimer in the
 12 
#   notice, this list of conditions and the following disclaimer in the
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#   documentation and/or other materials provided with the distribution.
 13 
#   documentation and/or other materials provided with the distribution.
14 
# - The name of the author may not be used to endorse or promote products
 14 
# - The name of the author may not be used to endorse or promote products
15 
#   derived from this software without specific prior written permission.
 15 
#   derived from this software without specific prior written permission.
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#
 16 
#
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# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 17 
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 18 
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 19 
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 20 
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 21 
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 22 
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 23 
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 24 
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 25 
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 26 
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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#
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 28 
 
29 
#include "asm.h"
 29 
#include "asm.h"
30 
#include "regname.h"
 30 
#include "regname.h"
31 
 
 31 
 
32 
.macro FLUSH_CACHE addr
 32 
.macro SMC_COHERENCY addr
33 
	dcbst 0, \addr
 33 
	dcbst 0, \addr
34 
	sync
 34 
	sync
35 
	icbi 0, \addr
 35 
	icbi 0, \addr
- 
 
 36 
	sync
36 
	isync
 37 
	isync
37 
.endm
 38 
.endm
38 
 
 39 
 
- 
 
 40 
.macro FLUSH_DCACHE addr
- 
 
 41 
	dcbst 0, \addr
- 
 
 42 
	sync
- 
 
 43 
	isync
- 
 
 44 
.endm
- 
 
 45 
 
- 
 
 46 
.macro TLB_FLUSH reg
- 
 
 47 
	tlbie \reg
- 
 
 48 
	addi \reg, \reg, 0x1000
- 
 
 49 
.endm
- 
 
 50 
 
39 
.text
 51 
.text
40 
 
 52 
 
41 
.global halt
 53 
.global halt
42 
.global memcpy
 54 
.global memcpy
43 
.global jump_to_kernel
 55 
.global jump_to_kernel
44 
 
 56 
 
45 
halt:
 57 
halt:
46 
	b halt
 58 
	b halt
47 
 
 59 
 
48 
memcpy:
 60 
memcpy:
49 
	srwi. r7, r5, 3
 61 
	srwi. r7, r5, 3
50 
	addi r6, r3, -4
 62 
	addi r6, r3, -4
51 
	addi r4, r4, -4
 63 
	addi r4, r4, -4
52 
	beq	2f
 64 
	beq	2f
53
65
54 
	andi. r0, r6, 3
 66 
	andi. r0, r6, 3
55 
	mtctr r7
 67 
	mtctr r7
56 
	bne 5f
 68 
	bne 5f
57
69
58 
	1:
 70 
	1:
59
71
60 
	lwz r7, 4(r4)
 72 
	lwz r7, 4(r4)
61 
	lwzu r8, 8(r4)
 73 
	lwzu r8, 8(r4)
62 
	stw r7, 4(r6)
 74 
	stw r7, 4(r6)
63 
	stwu r8, 8(r6)
 75 
	stwu r8, 8(r6)
64 
	bdnz 1b
 76 
	bdnz 1b
65
77
66 
	andi. r5, r5, 7
 78 
	andi. r5, r5, 7
67
79
68 
	2:
 80 
	2:
69
81
70 
	cmplwi 0, r5, 4
 82 
	cmplwi 0, r5, 4
71 
	blt 3f
 83 
	blt 3f
72
84
73 
	lwzu r0, 4(r4)
 85 
	lwzu r0, 4(r4)
74 
	addi r5, r5, -4
 86 
	addi r5, r5, -4
75 
	stwu r0, 4(r6)
 87 
	stwu r0, 4(r6)
76
88
77 
	3:
 89 
	3:
78
90
79 
	cmpwi 0, r5, 0
 91 
	cmpwi 0, r5, 0
80 
	beqlr
 92 
	beqlr
81 
	mtctr r5
 93 
	mtctr r5
82 
	addi r4, r4, 3
 94 
	addi r4, r4, 3
83 
	addi r6, r6, 3
 95 
	addi r6, r6, 3
84
96
85 
	4:
 97 
	4:
86
98
87 
	lbzu r0, 1(r4)
 99 
	lbzu r0, 1(r4)
88 
	stbu r0, 1(r6)
 100 
	stbu r0, 1(r6)
89 
	bdnz 4b
 101 
	bdnz 4b
90 
	blr
 102 
	blr
91
103
92 
	5:
 104 
	5:
93
105
94 
	subfic r0, r0, 4
 106 
	subfic r0, r0, 4
95 
	mtctr r0
 107 
	mtctr r0
96
108
97 
	6:
 109 
	6:
98
110
99 
	lbz r7, 4(r4)
 111 
	lbz r7, 4(r4)
100 
	addi r4, r4, 1
 112 
	addi r4, r4, 1
101 
	stb r7, 4(r6)
 113 
	stb r7, 4(r6)
102 
	addi r6, r6, 1
 114 
	addi r6, r6, 1
103 
	bdnz 6b
 115 
	bdnz 6b
104 
	subf r5, r0, r5
 116 
	subf r5, r0, r5
105 
	rlwinm. r7, r5, 32-3, 3, 31
 117 
	rlwinm. r7, r5, 32-3, 3, 31
106 
	beq 2b
 118 
	beq 2b
107 
	mtctr r7
 119 
	mtctr r7
108 
	b 1b
 120 
	b 1b
109 
 
 121 
 
110 
 
 122 
 
111 
jump_to_kernel:
 123 
jump_to_kernel:
112
124
113 
	# r3 = bootinfo (pa)
 125 
	# r3 = bootinfo (pa)
114 
	# r4 = bootinfo_size
 126 
	# r4 = bootinfo_size
115 
	# r5 = trans (pa)
 127 
	# r5 = trans (pa)
116 
	# r6 = bytes to copy
 128 
	# r6 = bytes to copy
117 
	# r7 = real_mode (pa)
 129 
	# r7 = real_mode (pa)
118 
	# r8 = framebuffer (pa)
 130 
	# r8 = framebuffer (pa)
119 
	# r9 = scanline
 131 
	# r9 = scanline
120
132
121 
	# disable interrupts
 133 
	# disable interrupts
122
134
123 
	mfmsr r31
 135 
	mfmsr r31
124 
	rlwinm r31, r31, 0, 17, 15
 136 
	rlwinm r31, r31, 0, 17, 15
125 
	mtmsr r31
 137 
	mtmsr r31
126
138
127 
	# set real_mode meeting point address
 139 
	# set real_mode meeting point address
128
140
129 
	mtspr srr0, r7
 141 
	mtspr srr0, r7
130
142
131 
	# jumps to real_mode
 143 
	# jumps to real_mode
132
144
133 
	mfmsr r31
 145 
	mfmsr r31
134 
	lis r30, ~0@h
 146 
	lis r30, ~0@h
135 
	ori r30, r30, ~(msr_ir | msr_dr | msr_ee)@l
 147 
	ori r30, r30, ~(msr_ir | msr_dr | msr_ee)@l
136 
	and r31, r31, r30
 148 
	and r31, r31, r30
137 
	mtspr srr1, r31
 149 
	mtspr srr1, r31
138
150
139 
	sync
 151 
	sync
140 
	isync
 152 
	isync
141 
	rfi
 153 
	rfi
142 
 
 154 
 
143 
.section REALMODE, "ax"
 155 
.section REALMODE, "ax"
144 
.align PAGE_WIDTH
 156 
.align PAGE_WIDTH
145 
.global real_mode
 157 
.global real_mode
146 
 
 158 
 
147 
real_mode:
 159 
real_mode:
148
160
149 
	# copy kernel to proper location
 161 
	# copy kernel to proper location
150 
	#
 162 
	#
151 
	# r5 = trans (pa)
 163 
	# r5 = trans (pa)
152 
	# r6 = bytes to copy
 164 
	# r6 = bytes to copy
153 
	# r8 = framebuffer (pa)
 165 
	# r8 = framebuffer (pa)
154 
	# r9 = scanline
 166 
	# r9 = scanline
155
167
156 
	li r31, PAGE_SIZE >> 2
 168 
	li r31, PAGE_SIZE >> 2
157 
	li r30, 0
 169 
	li r30, 0
158
170
159 
	page_copy:
 171 
	page_copy:
160
172
161 
		cmpwi r6, 0
 173 
		cmpwi r6, 0
162 
		beq copy_end
 174 
		beq copy_end
163
175
164 
		# copy page
 176 
		# copy page
165
177
166 
		mtctr r31
 178 
		mtctr r31
167 
		lwz r29, 0(r5)
 179 
		lwz r29, 0(r5)
168
180
169 
		copy_loop:
 181 
		copy_loop:
170
182
171 
			lwz r28, 0(r29)
 183 
			lwz r28, 0(r29)
172 
			stw r28, 0(r30)
 184 
			stw r28, 0(r30)
173
185
174 
			FLUSH_CACHE r30
 186 
			SMC_COHERENCY r30
175
187
176 
			addi r29, r29, 4
 188 
			addi r29, r29, 4
177 
			addi r30, r30, 4
 189 
			addi r30, r30, 4
178 
			subi r6, r6, 4
 190 
			subi r6, r6, 4
179
191
180 
			cmpwi r6, 0
 192 
			cmpwi r6, 0
181 
			beq copy_end
 193 
			beq copy_end
182
194
183 
			bdnz copy_loop
 195 
			bdnz copy_loop
184
196
185 
		addi r5, r5, 4
 197 
		addi r5, r5, 4
186 
		b page_copy
 198 
		b page_copy
187
199
188 
	copy_end:
 200 
	copy_end:
189
201
190 
	# initially fill segment registers
 202 
	# initially fill segment registers
191
203
192 
	li r31, 0
 204 
	li r31, 0
193
205
194 
	li r29, 8
 206 
	li r29, 8
195 
	mtctr r29
 207 
	mtctr r29
196 
	li r30, 0                     # ASID 0 (VSIDs 0 .. 7)
 208 
	li r30, 0                     # ASID 0 (VSIDs 0 .. 7)
197
209
198 
	seg_fill_uspace:
 210 
	seg_fill_uspace:
199
211
200 
		mtsrin r30, r31
 212 
		mtsrin r30, r31
201 
		addi r30, r30, 1
 213 
		addi r30, r30, 1
202 
		addis r31, r31, 0x1000    # move to next SR
 214 
		addis r31, r31, 0x1000    # move to next SR
203
215
204 
		bdnz seg_fill_uspace
 216 
		bdnz seg_fill_uspace
205
217
206 
	li r29, 8
 218 
	li r29, 8
207 
	mtctr r29
 219 
	mtctr r29
208 
	lis r30, 0x4000               # priviledged access only
 220 
	lis r30, 0x4000               # priviledged access only
209 
	ori r30, r30, 8               # ASID 0 (VSIDs 8 .. 15)
 221 
	ori r30, r30, 8               # ASID 0 (VSIDs 8 .. 15)
210
222
211 
	seg_fill_kernel:
 223 
	seg_fill_kernel:
212
224
213 
		mtsrin r30, r31
 225 
		mtsrin r30, r31
214 
		addi r30, r30, 1
 226 
		addi r30, r30, 1
215 
		addis r31, r31, 0x1000    # move to next SR
 227 
		addis r31, r31, 0x1000    # move to next SR
216
228
217 
		bdnz seg_fill_kernel
 229 
		bdnz seg_fill_kernel
218
230
219 
	# invalidate block address translation registers
 231 
	# invalidate block address translation registers
220
232
221 
	li r30, 0
 233 
	li r30, 0
222
234
223 
	mtspr ibat0u, r30
 235 
	mtspr ibat0u, r30
224 
	mtspr ibat0l, r30
 236 
	mtspr ibat0l, r30
225
237
226 
	mtspr ibat1u, r30
 238 
	mtspr ibat1u, r30
227 
	mtspr ibat1l, r30
 239 
	mtspr ibat1l, r30
228
240
229 
	mtspr ibat2u, r30
 241 
	mtspr ibat2u, r30
230 
	mtspr ibat2l, r30
 242 
	mtspr ibat2l, r30
231
243
232 
	mtspr ibat3u, r30
 244 
	mtspr ibat3u, r30
233 
	mtspr ibat3l, r30
 245 
	mtspr ibat3l, r30
234
246
235 
	mtspr dbat0u, r30
 247 
	mtspr dbat0u, r30
236 
	mtspr dbat0l, r30
 248 
	mtspr dbat0l, r30
237
249
238 
	mtspr dbat1u, r30
 250 
	mtspr dbat1u, r30
239 
	mtspr dbat1l, r30
 251 
	mtspr dbat1l, r30
240
252
241 
	mtspr dbat2u, r30
 253 
	mtspr dbat2u, r30
242 
	mtspr dbat2l, r30
 254 
	mtspr dbat2l, r30
243
255
244 
	mtspr dbat3u, r30
 256 
	mtspr dbat3u, r30
245 
	mtspr dbat3l, r30
 257 
	mtspr dbat3l, r30
246
258
247 
	# create empty Page Hash Table
 259 
	# create empty Page Hash Table
248 
	# on top of memory, size 64 KB
 260 
	# on top of memory, size 64 KB
249
261
250 
	lwz r31, 0(r3)                # r31 = memory size
 262 
	lwz r31, 0(r3)                # r31 = memory size
251
263
252 
	lis r30, 65536@h
 264 
	lis r30, 65536@h
253 
	ori r30, r30, 65536@l         # r30 = 65536
 265 
	ori r30, r30, 65536@l         # r30 = 65536
254
266
255 
	subi r29, r30, 1              # r29 = 65535
 267 
	subi r29, r30, 1              # r29 = 65535
256
268
257 
	sub r31, r31, r30
 269 
	sub r31, r31, r30
258 
	andc r31, r31, r29            # pht = ALIGN_DOWN(memory_size - 65536, 65536)
 270 
	andc r31, r31, r29            # pht = ALIGN_DOWN(memory_size - 65536, 65536)
259
271
260 
	mtsdr1 r31
 272 
	mtsdr1 r31
261
273
262 
	li r29, 2
 274 
	li r29, 2
263 
	srw r30, r30, r29             # r30 = 16384
 275 
	srw r30, r30, r29             # r30 = 16384
264 
	li r29, 0
 276 
	li r29, 0
265
277
266 
	pht_clear:
 278 
	pht_clear:
267
279
268 
		# write zeroes
 280 
		# write zeroes
269
281
270 
		stw r29, 0(r31)
 282 
		stw r29, 0(r31)
271 
		FLUSH_CACHE r31
 283 
		FLUSH_DCACHE r31
272
284
273 
		addi r31, r31, 4
 285 
		addi r31, r31, 4
274 
		subi r30, r30, 4
 286 
		subi r30, r30, 4
275
287
276 
		cmpwi r30, 0
 288 
		cmpwi r30, 0
277 
		beq clear_end
 289 
		beq clear_end
278
290
279 
		bdnz pht_clear
 291 
		bdnz pht_clear
280
292
281 
	clear_end:
 293 
	clear_end:
282
294
283 
#ifdef CONFIG_BAT
 295 
#ifdef CONFIG_BAT
284
296
285 
	# create BAT identity mapping
 297 
	# create BAT identity mapping
286
298
287 
	lwz r31, 0(r3)                # r31 = memory size
 299 
	lwz r31, 0(r3)                # r31 = memory size
288
300
289 
	lis r29, 0x0002
 301 
	lis r29, 0x0002
290 
	cmpw r31, r29
 302 
	cmpw r31, r29
291 
	blt no_bat                    # less than 128 KB -> no BAT
 303 
	blt no_bat                    # less than 128 KB -> no BAT
292
304
293 
	li r29, 18
 305 
	li r29, 18
294 
	srw r31, r31, r29             # r31 = total >> 18
 306 
	srw r31, r31, r29             # r31 = total >> 18
295
307
296 
	# create Block Length mask by replicating
 308 
	# create Block Length mask by replicating
297 
	# the leading logical one 14 times
 309 
	# the leading logical one 14 times
298
310
299 
	li r29, 14
 311 
	li r29, 14
300 
	mtctr r31
 312 
	mtctr r31
301 
	li r29, 1
 313 
	li r29, 1
302
314
303 
	bat_mask:
 315 
	bat_mask:
304 
		srw r30, r31, r29         # r30 = mask >> 1
 316 
		srw r30, r31, r29         # r30 = mask >> 1
305 
		or r31, r31, r30          # mask = mask | r30
 317 
		or r31, r31, r30          # mask = mask | r30
306
318
307 
		bdnz bat_mask
 319 
		bdnz bat_mask
308
320
309 
	andi. r31, r31, 0x07ff        # mask = mask & 0x07ff (BAT can map up to 256 MB)
 321 
	andi. r31, r31, 0x07ff        # mask = mask & 0x07ff (BAT can map up to 256 MB)
310
322
311 
	li r29, 2
 323 
	li r29, 2
312 
	slw r31, r31, r29             # mask = mask << 2
 324 
	slw r31, r31, r29             # mask = mask << 2
313 
	ori r31, r31, 0x0002          # mask = mask | 0x0002 (priviledged access only)
 325 
	ori r31, r31, 0x0002          # mask = mask | 0x0002 (priviledged access only)
314
326
315 
	lis r29, 0x8000
 327 
	lis r29, 0x8000
316 
	or r29, r29, r31
 328 
	or r29, r29, r31
317
329
318 
	lis r30, 0x0000
 330 
	lis r30, 0x0000
319 
	ori r30, r30, 0x0002
 331 
	ori r30, r30, 0x0002
320
332
321 
	mtspr ibat0u, r29
 333 
	mtspr ibat0u, r29
322 
	mtspr ibat0l, r30
 334 
	mtspr ibat0l, r30
323
335
324 
	mtspr dbat0u, r29
 336 
	mtspr dbat0u, r29
325 
	mtspr dbat0l, r30
 337 
	mtspr dbat0l, r30
326
338
327 
	no_bat:
 339 
	no_bat:
328
340
329 
#endif
 341 
#endif
330
342
- 
 
 343 
	# flush TLB
- 
 
 344
- 
 
 345 
	li r31, 0
- 
 
 346 
	sync
- 
 
 347
- 
 
 348 
	TLB_FLUSH r31
- 
 
 349 
	TLB_FLUSH r31
- 
 
 350 
	TLB_FLUSH r31
- 
 
 351 
	TLB_FLUSH r31
- 
 
 352 
	TLB_FLUSH r31
- 
 
 353 
	TLB_FLUSH r31
- 
 
 354 
	TLB_FLUSH r31
- 
 
 355 
	TLB_FLUSH r31
- 
 
 356
- 
 
 357 
	TLB_FLUSH r31
- 
 
 358 
	TLB_FLUSH r31
- 
 
 359 
	TLB_FLUSH r31
- 
 
 360 
	TLB_FLUSH r31
- 
 
 361 
	TLB_FLUSH r31
- 
 
 362 
	TLB_FLUSH r31
- 
 
 363 
	TLB_FLUSH r31
- 
 
 364 
	TLB_FLUSH r31
- 
 
 365
- 
 
 366 
	TLB_FLUSH r31
- 
 
 367 
	TLB_FLUSH r31
- 
 
 368 
	TLB_FLUSH r31
- 
 
 369 
	TLB_FLUSH r31
- 
 
 370 
	TLB_FLUSH r31
- 
 
 371 
	TLB_FLUSH r31
- 
 
 372 
	TLB_FLUSH r31
- 
 
 373 
	TLB_FLUSH r31
- 
 
 374
- 
 
 375 
	TLB_FLUSH r31
- 
 
 376 
	TLB_FLUSH r31
- 
 
 377 
	TLB_FLUSH r31
- 
 
 378 
	TLB_FLUSH r31
- 
 
 379 
	TLB_FLUSH r31
- 
 
 380 
	TLB_FLUSH r31
- 
 
 381 
	TLB_FLUSH r31
- 
 
 382 
	TLB_FLUSH r31
- 
 
 383
- 
 
 384 
	TLB_FLUSH r31
- 
 
 385 
	TLB_FLUSH r31
- 
 
 386 
	TLB_FLUSH r31
- 
 
 387 
	TLB_FLUSH r31
- 
 
 388 
	TLB_FLUSH r31
- 
 
 389 
	TLB_FLUSH r31
- 
 
 390 
	TLB_FLUSH r31
- 
 
 391 
	TLB_FLUSH r31
- 
 
 392
- 
 
 393 
	TLB_FLUSH r31
- 
 
 394 
	TLB_FLUSH r31
- 
 
 395 
	TLB_FLUSH r31
- 
 
 396 
	TLB_FLUSH r31
- 
 
 397 
	TLB_FLUSH r31
- 
 
 398 
	TLB_FLUSH r31
- 
 
 399 
	TLB_FLUSH r31
- 
 
 400 
	TLB_FLUSH r31
- 
 
 401
- 
 
 402 
	TLB_FLUSH r31
- 
 
 403 
	TLB_FLUSH r31
- 
 
 404 
	TLB_FLUSH r31
- 
 
 405 
	TLB_FLUSH r31
- 
 
 406 
	TLB_FLUSH r31
- 
 
 407 
	TLB_FLUSH r31
- 
 
 408 
	TLB_FLUSH r31
- 
 
 409 
	TLB_FLUSH r31
- 
 
 410
- 
 
 411 
	TLB_FLUSH r31
- 
 
 412 
	TLB_FLUSH r31
- 
 
 413 
	TLB_FLUSH r31
- 
 
 414 
	TLB_FLUSH r31
- 
 
 415 
	TLB_FLUSH r31
- 
 
 416 
	TLB_FLUSH r31
- 
 
 417 
	TLB_FLUSH r31
- 
 
 418 
	TLB_FLUSH r31
- 
 
 419
- 
 
 420 
	eieio
331 
	tlbsync
 421 
	tlbsync
- 
 
 422 
	sync
332
423
333 
	# start the kernel
 424 
	# start the kernel
334 
	#
 425 
	#
335 
	# pc = KERNEL_START_ADDR
 426 
	# pc = KERNEL_START_ADDR
336 
	# r3 = bootinfo (pa)
 427 
	# r3 = bootinfo (pa)
337 
	# sprg0 = KA2PA(KERNEL_START_ADDR)
 428 
	# sprg0 = KA2PA(KERNEL_START_ADDR)
338 
	# sprg3 = physical memory size
 429 
	# sprg3 = physical memory size
339 
	# sp = 0 (pa)
 430 
	# sp = 0 (pa)
340
431
341 
	lis r31, KERNEL_START_ADDR@ha
 432 
	lis r31, KERNEL_START_ADDR@ha
342 
	addi r31, r31, KERNEL_START_ADDR@l
 433 
	addi r31, r31, KERNEL_START_ADDR@l
343
434
344 
	mtspr srr0, r31
 435 
	mtspr srr0, r31
345
436
346 
	subis r31, r31, 0x8000
 437 
	subis r31, r31, 0x8000
347 
	mtsprg0 r31
 438 
	mtsprg0 r31
348
439
349 
	lwz r31, 0(r3)
 440 
	lwz r31, 0(r3)
350 
	mtsprg3 r31
 441 
	mtsprg3 r31
351
442
352 
	li sp, 0
 443 
	li sp, 0
353
444
354 
	mfmsr r31
 445 
	mfmsr r31
355 
	ori r31, r31, (msr_ir | msr_dr)@l
 446 
	ori r31, r31, (msr_ir | msr_dr)@l
356 
	mtspr srr1, r31
 447 
	mtspr srr1, r31
357
448
358 
	sync
 449 
	sync
359 
	isync
 450 
	isync
360 
	rfi
 451 
	rfi
361 
 
 452 
 
362 
.align PAGE_WIDTH
 453 
.align PAGE_WIDTH
363 
.global trans
 454 
.global trans
364 
trans:
 455 
trans:
365 
	.space (TRANS_SIZE * TRANS_ITEM_SIZE)
 456 
	.space (TRANS_SIZE * TRANS_ITEM_SIZE)
366 
 
 457