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Line 158... Line 158...
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 * @param v New value of Primary Context Register.
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 * @param v New value of Primary Context Register.
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 */
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 */
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static inline void mmu_primary_context_write(uint64_t v)
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static inline void mmu_primary_context_write(uint64_t v)
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{
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{
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    asi_u64_write(ASI_DMMU, VA_PRIMARY_CONTEXT_REG, v);
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    asi_u64_write(ASI_DMMU, VA_PRIMARY_CONTEXT_REG, v);
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    flush();
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    flush_pipeline();
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}
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}
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/** Read MMU Secondary Context Register.
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/** Read MMU Secondary Context Register.
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 *
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 *
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 * @return Current value of Secondary Context Register.
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 * @return Current value of Secondary Context Register.
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 * @param v New value of Primary Context Register.
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 * @param v New value of Primary Context Register.
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 */
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 */
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static inline void mmu_secondary_context_write(uint64_t v)
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static inline void mmu_secondary_context_write(uint64_t v)
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{
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{
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    asi_u64_write(ASI_DMMU, VA_SECONDARY_CONTEXT_REG, v);
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    asi_u64_write(ASI_DMMU, VA_SECONDARY_CONTEXT_REG, v);
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    flush();
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    flush_pipeline();
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}
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}
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/** Read IMMU TLB Data Access Register.
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/** Read IMMU TLB Data Access Register.
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 *
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 *
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 * @param entry TLB Entry index.
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 * @param entry TLB Entry index.
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    tlb_data_access_addr_t reg;
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    tlb_data_access_addr_t reg;
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    reg.value = 0;
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    reg.value = 0;
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    reg.tlb_entry = entry;
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    reg.tlb_entry = entry;
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    asi_u64_write(ASI_ITLB_DATA_ACCESS_REG, reg.value, value);
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    asi_u64_write(ASI_ITLB_DATA_ACCESS_REG, reg.value, value);
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    flush();
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    flush_pipeline();
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}
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}
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/** Read DMMU TLB Data Access Register.
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/** Read DMMU TLB Data Access Register.
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 *
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 *
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 * @param entry TLB Entry index.
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 * @param entry TLB Entry index.
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 * @param v Value to be written.
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 * @param v Value to be written.
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 */
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 */
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static inline void itlb_tag_access_write(uint64_t v)
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static inline void itlb_tag_access_write(uint64_t v)
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{
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{
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    asi_u64_write(ASI_IMMU, VA_IMMU_TAG_ACCESS, v);
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    asi_u64_write(ASI_IMMU, VA_IMMU_TAG_ACCESS, v);
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    flush();
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    flush_pipeline();
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}
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}
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/** Read IMMU TLB Tag Access Register.
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/** Read IMMU TLB Tag Access Register.
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 *
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 *
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 * @return Current value of IMMU TLB Tag Access Register.
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 * @return Current value of IMMU TLB Tag Access Register.
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 * @param v Value to be written.
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 * @param v Value to be written.
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 */
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 */
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static inline void itlb_data_in_write(uint64_t v)
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static inline void itlb_data_in_write(uint64_t v)
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{
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{
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    asi_u64_write(ASI_ITLB_DATA_IN_REG, 0, v);
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    asi_u64_write(ASI_ITLB_DATA_IN_REG, 0, v);
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    flush();
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    flush_pipeline();
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}
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}
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/** Write DMMU TLB Data in Register.
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/** Write DMMU TLB Data in Register.
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 *
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 *
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 * @param v Value to be written.
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 * @param v Value to be written.
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 * @param v New value of I-SFSR register.
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 * @param v New value of I-SFSR register.
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 */
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 */
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static inline void itlb_sfsr_write(uint64_t v)
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static inline void itlb_sfsr_write(uint64_t v)
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{
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{
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    asi_u64_write(ASI_IMMU, VA_IMMU_SFSR, v);
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    asi_u64_write(ASI_IMMU, VA_IMMU_SFSR, v);
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    flush();
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    flush_pipeline();
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}
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}
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/** Read DTLB Synchronous Fault Status Register.
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/** Read DTLB Synchronous Fault Status Register.
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 *
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 *
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 * @return Current content of D-SFSR register.
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 * @return Current content of D-SFSR register.
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    da.vpn = pg.vpn;
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    da.vpn = pg.vpn;
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    asi_u64_write(ASI_IMMU_DEMAP, da.value, 0); /* da.value is the
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    asi_u64_write(ASI_IMMU_DEMAP, da.value, 0); /* da.value is the
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                             * address within the
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                             * address within the
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                             * ASI */
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                             * ASI */
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    flush();
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    flush_pipeline();
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}
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}
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/** Perform DMMU TLB Demap Operation.
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/** Perform DMMU TLB Demap Operation.
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 *
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 *
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 * @param type Selects between context and page demap.
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 * @param type Selects between context and page demap.