WebSVN – HelenOS – Diff – /branches/tracing/kernel/arch/ppc32/src/mm/tlb.c


/*
 * Copyright (c) 2006 Martin Decky
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup ppc32mm
 * @{
 */
/** @file
 */
 
#include <mm/tlb.h>
#include <arch/mm/tlb.h>
#include <arch/interrupt.h>
#include <interrupt.h>
#include <mm/as.h>
#include <arch.h>
#include <print.h>
#include <macros.h>
#include <symtab.h>
 
static unsigned int seed = 10;
static unsigned int seed_real __attribute__ ((section("K_UNMAPPED_DATA_START"))) = 42;
 
 
#define TLB_FLUSH \
    "tlbie %0\n" \
    "addi %0, %0, 0x1000\n"
 
 
/** Try to find PTE for faulting address
 *
 * Try to find PTE for faulting address.
 * The as->lock must be held on entry to this function
 * if lock is true.
 *
 * @param as        Address space.
 * @param lock      Lock/unlock the address space.
 * @param badvaddr  Faulting virtual address.
 * @param access    Access mode that caused the fault.
 * @param istate    Pointer to interrupted state.
 * @param pfrc      Pointer to variable where as_page_fault() return code
 *          will be stored.
 * @return      PTE on success, NULL otherwise.
 *
 */
static pte_t *
find_mapping_and_check(as_t *as, bool lock, uintptr_t badvaddr, int access,
    istate_t *istate, int *pfrc)
{
    /*
     * Check if the mapping exists in page tables.
     */
    pte_t *pte = page_mapping_find(as, badvaddr);
    if ((pte) && (pte->present)) {
        /*
         * Mapping found in page tables.
         * Immediately succeed.
         */
        return pte;
    } else {
        int rc;
   
        /*
         * Mapping not found in page tables.
         * Resort to higher-level page fault handler.
         */
        page_table_unlock(as, lock);
        switch (rc = as_page_fault(badvaddr, access, istate)) {
        case AS_PF_OK:
            /*
             * The higher-level page fault handler succeeded,
             * The mapping ought to be in place.
             */
            page_table_lock(as, lock);
            pte = page_mapping_find(as, badvaddr);
            ASSERT((pte) && (pte->present));
            *pfrc = 0;
            return pte;
        case AS_PF_DEFER:
            page_table_lock(as, lock);
            *pfrc = rc;
            return NULL;
        case AS_PF_FAULT:
            page_table_lock(as, lock);
            *pfrc = rc;
            return NULL;
        default:
            panic("Unexpected rc (%d).", rc);
        }  
    }
}
 
 
static void pht_refill_fail(uintptr_t badvaddr, istate_t *istate)
{
    char *symbol;
    char *sym2;
 
    symbol = symtab_fmt_name_lookup(istate->pc);
    sym2 = symtab_fmt_name_lookup(istate->lr);
 
    fault_if_from_uspace(istate,
        "PHT Refill Exception on %p.", badvaddr);
    panic("%p: PHT Refill Exception at %p (%s<-%s).", badvaddr,
        istate->pc, symbol, sym2);
}
 
 
static void pht_insert(const uintptr_t vaddr, const pte_t *pte)
{
    uint32_t page = (vaddr >> 12) & 0xffff;
    uint32_t api = (vaddr >> 22) & 0x3f;
   
    uint32_t vsid;
    asm volatile (
        "mfsrin %0, %1\n"
        : "=r" (vsid)
        : "r" (vaddr)
    );
   
    uint32_t sdr1;
    asm volatile (
        "mfsdr1 %0\n"
        : "=r" (sdr1)
    );
    phte_t *phte = (phte_t *) PA2KA(sdr1 & 0xffff0000);
   
    /* Primary hash (xor) */
    uint32_t h = 0;
    uint32_t hash = vsid ^ page;
    uint32_t base = (hash & 0x3ff) << 3;
    uint32_t i;
    bool found = false;
   
    /* Find colliding PTE in PTEG */
    for (i = 0; i < 8; i++) {
        if ((phte[base + i].v)
            && (phte[base + i].vsid == vsid)
            && (phte[base + i].api == api)
            && (phte[base + i].h == 0)) {
            found = true;
            break;
        }
    }
   
    if (!found) {
        /* Find unused PTE in PTEG */
        for (i = 0; i < 8; i++) {
            if (!phte[base + i].v) {
                found = true;
                break;
            }
        }
    }
   
    if (!found) {
        /* Secondary hash (not) */
        uint32_t base2 = (~hash & 0x3ff) << 3;
       
        /* Find colliding PTE in PTEG */
        for (i = 0; i < 8; i++) {
            if ((phte[base2 + i].v)
                && (phte[base2 + i].vsid == vsid)
                && (phte[base2 + i].api == api)
                && (phte[base2 + i].h == 1)) {
                found = true;
                base = base2;
                h = 1;
                break;
            }
        }
       
        if (!found) {
            /* Find unused PTE in PTEG */
            for (i = 0; i < 8; i++) {
                if (!phte[base2 + i].v) {
                    found = true;
                    base = base2;
                    h = 1;
                    break;
                }
            }
        }
       
        if (!found)
            i = RANDI(seed) % 8;
    }
   
    phte[base + i].v = 1;
    phte[base + i].vsid = vsid;
    phte[base + i].h = h;
    phte[base + i].api = api;
    phte[base + i].rpn = pte->pfn;
    phte[base + i].r = 0;
    phte[base + i].c = 0;
    phte[base + i].wimg = (pte->page_cache_disable ? WIMG_NO_CACHE : 0);
    phte[base + i].pp = 2; // FIXME
}
 
 
/** Process Instruction/Data Storage Exception
 *
 * @param n      Exception vector number.
 * @param istate Interrupted register context.
 *
 */
void pht_refill(int n, istate_t *istate)
{
    uintptr_t badvaddr;
    pte_t *pte;
    int pfrc;
    as_t *as;
    bool lock;
   
    if (AS == NULL) {
        as = AS_KERNEL;
        lock = false;
    } else {
        as = AS;
        lock = true;
    }
   
    if (n == VECTOR_DATA_STORAGE)
        badvaddr = istate->dar;
    else
        badvaddr = istate->pc;
       
    page_table_lock(as, lock);
   
    pte = find_mapping_and_check(as, lock, badvaddr,
        PF_ACCESS_READ /* FIXME */, istate, &pfrc);
    if (!pte) {
        switch (pfrc) {
        case AS_PF_FAULT:
            goto fail;
            break;
        case AS_PF_DEFER:
            /*
             * The page fault came during copy_from_uspace()
             * or copy_to_uspace().
             */
            page_table_unlock(as, lock);
            return;
        default:
            panic("Unexpected pfrc (%d).", pfrc);
        }
    }
   
    pte->accessed = 1; /* Record access to PTE */
    pht_insert(badvaddr, pte);
   
    page_table_unlock(as, lock);
    return;
   
fail:
    page_table_unlock(as, lock);
    pht_refill_fail(badvaddr, istate);
}
 
 
/** Process Instruction/Data Storage Exception in Real Mode
 *
 * @param n      Exception vector number.
 * @param istate Interrupted register context.
 *
 */
bool pht_refill_real(int n, istate_t *istate)
{
    uintptr_t badvaddr;
   
    if (n == VECTOR_DATA_STORAGE)
        badvaddr = istate->dar;
    else
        badvaddr = istate->pc;
   
    uint32_t physmem;
    asm volatile (
        "mfsprg3 %0\n"
        : "=r" (physmem)
    );
   
    if ((badvaddr < PA2KA(0)) || (badvaddr >= PA2KA(physmem)))
        return false;
   
    uint32_t page = (badvaddr >> 12) & 0xffff;
    uint32_t api = (badvaddr >> 22) & 0x3f;
   
    uint32_t vsid;
    asm volatile (
        "mfsrin %0, %1\n"
        : "=r" (vsid)
        : "r" (badvaddr)
    );
   
    uint32_t sdr1;
    asm volatile (
        "mfsdr1 %0\n"
        : "=r" (sdr1)
    );
    phte_t *phte_real = (phte_t *) (sdr1 & 0xffff0000);
   
    /* Primary hash (xor) */
    uint32_t h = 0;
    uint32_t hash = vsid ^ page;
    uint32_t base = (hash & 0x3ff) << 3;
    uint32_t i;
    bool found = false;
   
    /* Find colliding PTE in PTEG */
    for (i = 0; i < 8; i++) {
        if ((phte_real[base + i].v)
            && (phte_real[base + i].vsid == vsid)
            && (phte_real[base + i].api == api)
            && (phte_real[base + i].h == 0)) {
            found = true;
            break;
        }
    }
   
    if (!found) {
        /* Find unused PTE in PTEG */
        for (i = 0; i < 8; i++) {
            if (!phte_real[base + i].v) {
                found = true;
                break;
            }
        }
    }
   
    if (!found) {
        /* Secondary hash (not) */
        uint32_t base2 = (~hash & 0x3ff) << 3;
       
        /* Find colliding PTE in PTEG */
        for (i = 0; i < 8; i++) {
            if ((phte_real[base2 + i].v)
                && (phte_real[base2 + i].vsid == vsid)
                && (phte_real[base2 + i].api == api)
                && (phte_real[base2 + i].h == 1)) {
                found = true;
                base = base2;
                h = 1;
                break;
            }
        }
       
        if (!found) {
            /* Find unused PTE in PTEG */
            for (i = 0; i < 8; i++) {
                if (!phte_real[base2 + i].v) {
                    found = true;
                    base = base2;
                    h = 1;
                    break;
                }
            }
        }
       
        if (!found) {
            /* Use secondary hash to avoid collisions
               with usual PHT refill handler. */
            i = RANDI(seed_real) % 8;
            base = base2;
            h = 1;
        }
    }
   
    phte_real[base + i].v = 1;
    phte_real[base + i].vsid = vsid;
    phte_real[base + i].h = h;
    phte_real[base + i].api = api;
    phte_real[base + i].rpn = KA2PA(badvaddr) >> 12;
    phte_real[base + i].r = 0;
    phte_real[base + i].c = 0;
    phte_real[base + i].wimg = 0;
    phte_real[base + i].pp = 2; // FIXME
   
    return true;
}
 
 
/** Process ITLB/DTLB Miss Exception in Real Mode
 *
 *
 */
void tlb_refill_real(int n, uint32_t tlbmiss, ptehi_t ptehi, ptelo_t ptelo, istate_t *istate)
{
    uint32_t badvaddr = tlbmiss & 0xfffffffc;
   
    uint32_t physmem;
    asm volatile (
        "mfsprg3 %0\n"
        : "=r" (physmem)
    );
   
    if ((badvaddr < PA2KA(0)) || (badvaddr >= PA2KA(physmem)))
        return; // FIXME
   
    ptelo.rpn = KA2PA(badvaddr) >> 12;
    ptelo.wimg = 0;
    ptelo.pp = 2; // FIXME
   
    uint32_t index = 0;
    asm volatile (
        "mtspr 981, %0\n"
        "mtspr 982, %1\n"
        "tlbld %2\n"
        "tlbli %2\n"
        : "=r" (index)
        : "r" (ptehi),
          "r" (ptelo)
    );
}
 
 
void tlb_arch_init(void)
{
    tlb_invalidate_all();
}
 
 
void tlb_invalidate_all(void)
{
    uint32_t index;
    asm volatile (
        "li %0, 0\n"
        "sync\n"
       
        TLB_FLUSH
        TLB_FLUSH
        TLB_FLUSH
        TLB_FLUSH
        TLB_FLUSH
        TLB_FLUSH
        TLB_FLUSH
        TLB_FLUSH
       
        TLB_FLUSH
        TLB_FLUSH
        TLB_FLUSH
        TLB_FLUSH
        TLB_FLUSH
        TLB_FLUSH
        TLB_FLUSH
        TLB_FLUSH
       
        TLB_FLUSH
        TLB_FLUSH
        TLB_FLUSH
        TLB_FLUSH
        TLB_FLUSH
        TLB_FLUSH
        TLB_FLUSH
        TLB_FLUSH
       
        TLB_FLUSH
        TLB_FLUSH
        TLB_FLUSH
        TLB_FLUSH
        TLB_FLUSH
        TLB_FLUSH
        TLB_FLUSH
        TLB_FLUSH
       
        TLB_FLUSH
        TLB_FLUSH
        TLB_FLUSH
        TLB_FLUSH
        TLB_FLUSH
        TLB_FLUSH
        TLB_FLUSH
        TLB_FLUSH
       
        TLB_FLUSH
        TLB_FLUSH
        TLB_FLUSH
        TLB_FLUSH
        TLB_FLUSH
        TLB_FLUSH
        TLB_FLUSH
        TLB_FLUSH
       
        TLB_FLUSH
        TLB_FLUSH
        TLB_FLUSH
        TLB_FLUSH
        TLB_FLUSH
        TLB_FLUSH
        TLB_FLUSH
        TLB_FLUSH
       
        TLB_FLUSH
        TLB_FLUSH
        TLB_FLUSH
        TLB_FLUSH
        TLB_FLUSH
        TLB_FLUSH
        TLB_FLUSH
        TLB_FLUSH
       
        "eieio\n"
        "tlbsync\n"
        "sync\n"
        : "=r" (index)
    );
}
 
 
void tlb_invalidate_asid(asid_t asid)
{
    uint32_t sdr1;
    asm volatile (
        "mfsdr1 %0\n"
        : "=r" (sdr1)
    );
    phte_t *phte = (phte_t *) PA2KA(sdr1 & 0xffff0000);
   
    uint32_t i;
    for (i = 0; i < 8192; i++) {
        if ((phte[i].v) && (phte[i].vsid >= (asid << 4)) &&
            (phte[i].vsid < ((asid << 4) + 16)))
            phte[i].v = 0;
    }
    tlb_invalidate_all();
}
 
 
void tlb_invalidate_pages(asid_t asid, uintptr_t page, size_t cnt)
{
    // TODO
    tlb_invalidate_all();
}
 
 
#define PRINT_BAT(name, ureg, lreg) \
    asm volatile ( \
        "mfspr %0," #ureg "\n" \
        "mfspr %1," #lreg "\n" \
        : "=r" (upper), "=r" (lower) \
    ); \
    mask = (upper & 0x1ffc) >> 2; \
    if (upper & 3) { \
        uint32_t tmp = mask; \
        length = 128; \
        while (tmp) { \
            if ((tmp & 1) == 0) { \
                printf("ibat[0]: error in mask\n"); \
                break; \
            } \
            length <<= 1; \
            tmp >>= 1; \
        } \
    } else \
        length = 0; \
    printf(name ": page=%.*p frame=%.*p length=%d KB (mask=%#x)%s%s\n", \
        sizeof(upper) * 2, upper & 0xffff0000, sizeof(lower) * 2, \
        lower & 0xffff0000, length, mask, \
        ((upper >> 1) & 1) ? " supervisor" : "", \
        (upper & 1) ? " user" : "");
 
 
void tlb_print(void)
{
    uint32_t sr;
   
    for (sr = 0; sr < 16; sr++) {
        uint32_t vsid;
        asm volatile (
            "mfsrin %0, %1\n"
            : "=r" (vsid)
            : "r" (sr << 28)
        );
        printf("sr[%02u]: vsid=%.*p (asid=%u)%s%s\n", sr,
            sizeof(vsid) * 2, vsid & 0xffffff, (vsid & 0xffffff) >> 4,
            ((vsid >> 30) & 1) ? " supervisor" : "",
            ((vsid >> 29) & 1) ? " user" : "");
    }
   
    uint32_t upper;
    uint32_t lower;
    uint32_t mask;
    uint32_t length;
   
    PRINT_BAT("ibat[0]", 528, 529);
    PRINT_BAT("ibat[1]", 530, 531);
    PRINT_BAT("ibat[2]", 532, 533);
    PRINT_BAT("ibat[3]", 534, 535);
   
    PRINT_BAT("dbat[0]", 536, 537);
    PRINT_BAT("dbat[1]", 538, 539);
    PRINT_BAT("dbat[2]", 540, 541);
    PRINT_BAT("dbat[3]", 542, 543);
}
 
/** @}
 */
 

Rev 4377	Rev 4692
1	/*	1	/*
2	* Copyright (c) 2006 Martin Decky	2	* Copyright (c) 2006 Martin Decky
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	/** @addtogroup ppc32mm	29	/** @addtogroup ppc32mm
30	* @{	30	* @{
31	*/	31	*/
32	/** @file	32	/** @file
33	*/	33	*/
34		34
35	#include <mm/tlb.h>	35	#include <mm/tlb.h>
36	#include <arch/mm/tlb.h>	36	#include <arch/mm/tlb.h>
37	#include <arch/interrupt.h>	37	#include <arch/interrupt.h>
38	#include <interrupt.h>	38	#include <interrupt.h>
39	#include <mm/as.h>	39	#include <mm/as.h>
40	#include <arch.h>	40	#include <arch.h>
41	#include <print.h>	41	#include <print.h>
42	#include <macros.h>	42	#include <macros.h>
43	#include <symtab.h>	43	#include <symtab.h>
44		44
45	static unsigned int seed = 10;	45	static unsigned int seed = 10;
46	static unsigned int seed_real __attribute__ ((section("K_UNMAPPED_DATA_START"))) = 42;	46	static unsigned int seed_real __attribute__ ((section("K_UNMAPPED_DATA_START"))) = 42;
47		47
48		48
49	#define TLB_FLUSH \	49	#define TLB_FLUSH \
50	"tlbie %0\n" \	50	"tlbie %0\n" \
51	"addi %0, %0, 0x1000\n"	51	"addi %0, %0, 0x1000\n"
52		52
53		53
54	/** Try to find PTE for faulting address	54	/** Try to find PTE for faulting address
55	*	55	*
56	* Try to find PTE for faulting address.	56	* Try to find PTE for faulting address.
57	* The as->lock must be held on entry to this function	57	* The as->lock must be held on entry to this function
58	* if lock is true.	58	* if lock is true.
59	*	59	*
60	* @param as Address space.	60	* @param as Address space.
61	* @param lock Lock/unlock the address space.	61	* @param lock Lock/unlock the address space.
62	* @param badvaddr Faulting virtual address.	62	* @param badvaddr Faulting virtual address.
63	* @param access Access mode that caused the fault.	63	* @param access Access mode that caused the fault.
64	* @param istate Pointer to interrupted state.	64	* @param istate Pointer to interrupted state.
65	* @param pfrc Pointer to variable where as_page_fault() return code	65	* @param pfrc Pointer to variable where as_page_fault() return code
66	* will be stored.	66	* will be stored.
67	* @return PTE on success, NULL otherwise.	67	* @return PTE on success, NULL otherwise.
68	*	68	*
69	*/	69	*/
70	static pte_t *	70	static pte_t *
71	find_mapping_and_check(as_t *as, bool lock, uintptr_t badvaddr, int access,	71	find_mapping_and_check(as_t *as, bool lock, uintptr_t badvaddr, int access,
72	istate_t istate, int pfrc)	72	istate_t istate, int pfrc)
73	{	73	{
74	/*	74	/*
75	* Check if the mapping exists in page tables.	75	* Check if the mapping exists in page tables.
76	*/	76	*/
77	pte_t *pte = page_mapping_find(as, badvaddr);	77	pte_t *pte = page_mapping_find(as, badvaddr);
78	if ((pte) && (pte->present)) {	78	if ((pte) && (pte->present)) {
79	/*	79	/*
80	* Mapping found in page tables.	80	* Mapping found in page tables.
81	* Immediately succeed.	81	* Immediately succeed.
82	*/	82	*/
83	return pte;	83	return pte;
84	} else {	84	} else {
85	int rc;	85	int rc;
86		86
87	/*	87	/*
88	* Mapping not found in page tables.	88	* Mapping not found in page tables.
89	* Resort to higher-level page fault handler.	89	* Resort to higher-level page fault handler.
90	*/	90	*/
91	page_table_unlock(as, lock);	91	page_table_unlock(as, lock);
92	switch (rc = as_page_fault(badvaddr, access, istate)) {	92	switch (rc = as_page_fault(badvaddr, access, istate)) {
93	case AS_PF_OK:	93	case AS_PF_OK:
94	/*	94	/*
95	* The higher-level page fault handler succeeded,	95	* The higher-level page fault handler succeeded,
96	* The mapping ought to be in place.	96	* The mapping ought to be in place.
97	*/	97	*/
98	page_table_lock(as, lock);	98	page_table_lock(as, lock);
99	pte = page_mapping_find(as, badvaddr);	99	pte = page_mapping_find(as, badvaddr);
100	ASSERT((pte) && (pte->present));	100	ASSERT((pte) && (pte->present));
101	*pfrc = 0;	101	*pfrc = 0;
102	return pte;	102	return pte;
103	case AS_PF_DEFER:	103	case AS_PF_DEFER:
104	page_table_lock(as, lock);	104	page_table_lock(as, lock);
105	*pfrc = rc;	105	*pfrc = rc;
106	return NULL;	106	return NULL;
107	case AS_PF_FAULT:	107	case AS_PF_FAULT:
108	page_table_lock(as, lock);	108	page_table_lock(as, lock);
109	*pfrc = rc;	109	*pfrc = rc;
110	return NULL;	110	return NULL;
111	default:	111	default:
112	panic("Unexpected rc (%d).", rc);	112	panic("Unexpected rc (%d).", rc);
113	}	113	}
114	}	114	}
115	}	115	}
116		116
117		117
118	static void pht_refill_fail(uintptr_t badvaddr, istate_t *istate)	118	static void pht_refill_fail(uintptr_t badvaddr, istate_t *istate)
119	{	119	{
120	char *symbol;	120	char *symbol;
121	char *sym2;	121	char *sym2;
122		122
123	symbol = symtab_fmt_name_lookup(istate->pc);	123	symbol = symtab_fmt_name_lookup(istate->pc);
124	sym2 = symtab_fmt_name_lookup(istate->lr);	124	sym2 = symtab_fmt_name_lookup(istate->lr);
125		125
126	fault_if_from_uspace(istate,	126	fault_if_from_uspace(istate,
127	"PHT Refill Exception on %p.", badvaddr);	127	"PHT Refill Exception on %p.", badvaddr);
128	panic("%p: PHT Refill Exception at %p (%s<-%s).", badvaddr,	128	panic("%p: PHT Refill Exception at %p (%s<-%s).", badvaddr,
129	istate->pc, symbol, sym2);	129	istate->pc, symbol, sym2);
130	}	130	}
131		131
132		132
133	static void pht_insert(const uintptr_t vaddr, const pte_t *pte)	133	static void pht_insert(const uintptr_t vaddr, const pte_t *pte)
134	{	134	{
135	uint32_t page = (vaddr >> 12) & 0xffff;	135	uint32_t page = (vaddr >> 12) & 0xffff;
136	uint32_t api = (vaddr >> 22) & 0x3f;	136	uint32_t api = (vaddr >> 22) & 0x3f;
137		137
138	uint32_t vsid;	138	uint32_t vsid;
139	asm volatile (	139	asm volatile (
140	"mfsrin %0, %1\n"	140	"mfsrin %0, %1\n"
141	: "=r" (vsid)	141	: "=r" (vsid)
142	: "r" (vaddr)	142	: "r" (vaddr)
143	);	143	);
144		144
145	uint32_t sdr1;	145	uint32_t sdr1;
146	asm volatile (	146	asm volatile (
147	"mfsdr1 %0\n"	147	"mfsdr1 %0\n"
148	: "=r" (sdr1)	148	: "=r" (sdr1)
149	);	149	);
150	phte_t phte = (phte_t ) PA2KA(sdr1 & 0xffff0000);	150	phte_t phte = (phte_t ) PA2KA(sdr1 & 0xffff0000);
151		151
152	/* Primary hash (xor) */	152	/* Primary hash (xor) */
153	uint32_t h = 0;	153	uint32_t h = 0;
154	uint32_t hash = vsid ^ page;	154	uint32_t hash = vsid ^ page;
155	uint32_t base = (hash & 0x3ff) << 3;	155	uint32_t base = (hash & 0x3ff) << 3;
156	uint32_t i;	156	uint32_t i;
157	bool found = false;	157	bool found = false;
158		158
159	/* Find colliding PTE in PTEG */	159	/* Find colliding PTE in PTEG */
160	for (i = 0; i < 8; i++) {	160	for (i = 0; i < 8; i++) {
161	if ((phte[base + i].v)	161	if ((phte[base + i].v)
162	&& (phte[base + i].vsid == vsid)	162	&& (phte[base + i].vsid == vsid)
163	&& (phte[base + i].api == api)	163	&& (phte[base + i].api == api)
164	&& (phte[base + i].h == 0)) {	164	&& (phte[base + i].h == 0)) {
165	found = true;	165	found = true;
166	break;	166	break;
167	}	167	}
168	}	168	}
169		169
170	if (!found) {	170	if (!found) {
171	/* Find unused PTE in PTEG */	171	/* Find unused PTE in PTEG */
172	for (i = 0; i < 8; i++) {	172	for (i = 0; i < 8; i++) {
173	if (!phte[base + i].v) {	173	if (!phte[base + i].v) {
174	found = true;	174	found = true;
175	break;	175	break;
176	}	176	}
177	}	177	}
178	}	178	}
179		179
180	if (!found) {	180	if (!found) {
181	/* Secondary hash (not) */	181	/* Secondary hash (not) */
182	uint32_t base2 = (~hash & 0x3ff) << 3;	182	uint32_t base2 = (~hash & 0x3ff) << 3;
183		183
184	/* Find colliding PTE in PTEG */	184	/* Find colliding PTE in PTEG */
185	for (i = 0; i < 8; i++) {	185	for (i = 0; i < 8; i++) {
186	if ((phte[base2 + i].v)	186	if ((phte[base2 + i].v)
187	&& (phte[base2 + i].vsid == vsid)	187	&& (phte[base2 + i].vsid == vsid)
188	&& (phte[base2 + i].api == api)	188	&& (phte[base2 + i].api == api)
189	&& (phte[base2 + i].h == 1)) {	189	&& (phte[base2 + i].h == 1)) {
190	found = true;	190	found = true;
191	base = base2;	191	base = base2;
192	h = 1;	192	h = 1;
193	break;	193	break;
194	}	194	}
195	}	195	}
196		196
197	if (!found) {	197	if (!found) {
198	/* Find unused PTE in PTEG */	198	/* Find unused PTE in PTEG */
199	for (i = 0; i < 8; i++) {	199	for (i = 0; i < 8; i++) {
200	if (!phte[base2 + i].v) {	200	if (!phte[base2 + i].v) {
201	found = true;	201	found = true;
202	base = base2;	202	base = base2;
203	h = 1;	203	h = 1;
204	break;	204	break;
205	}	205	}
206	}	206	}
207	}	207	}
208		208
209	if (!found)	209	if (!found)
210	i = RANDI(seed) % 8;	210	i = RANDI(seed) % 8;
211	}	211	}
212		212
213	phte[base + i].v = 1;	213	phte[base + i].v = 1;
214	phte[base + i].vsid = vsid;	214	phte[base + i].vsid = vsid;
215	phte[base + i].h = h;	215	phte[base + i].h = h;
216	phte[base + i].api = api;	216	phte[base + i].api = api;
217	phte[base + i].rpn = pte->pfn;	217	phte[base + i].rpn = pte->pfn;
218	phte[base + i].r = 0;	218	phte[base + i].r = 0;
219	phte[base + i].c = 0;	219	phte[base + i].c = 0;
220	phte[base + i].wimg = (pte->page_cache_disable ? WIMG_NO_CACHE : 0);	220	phte[base + i].wimg = (pte->page_cache_disable ? WIMG_NO_CACHE : 0);
221	phte[base + i].pp = 2; // FIXME	221	phte[base + i].pp = 2; // FIXME
222	}	222	}
223		223
224		224
225	/** Process Instruction/Data Storage Exception	225	/** Process Instruction/Data Storage Exception
226	*	226	*
227	* @param n Exception vector number.	227	* @param n Exception vector number.
228	* @param istate Interrupted register context.	228	* @param istate Interrupted register context.
229	*	229	*
230	*/	230	*/
231	void pht_refill(int n, istate_t *istate)	231	void pht_refill(int n, istate_t *istate)
232	{	232	{
233	uintptr_t badvaddr;	233	uintptr_t badvaddr;
234	pte_t *pte;	234	pte_t *pte;
235	int pfrc;	235	int pfrc;
236	as_t *as;	236	as_t *as;
237	bool lock;	237	bool lock;
238		238
239	if (AS == NULL) {	239	if (AS == NULL) {
240	as = AS_KERNEL;	240	as = AS_KERNEL;
241	lock = false;	241	lock = false;
242	} else {	242	} else {
243	as = AS;	243	as = AS;
244	lock = true;	244	lock = true;
245	}	245	}
246		246
247	if (n == VECTOR_DATA_STORAGE)	247	if (n == VECTOR_DATA_STORAGE)
248	badvaddr = istate->dar;	248	badvaddr = istate->dar;
249	else	249	else
250	badvaddr = istate->pc;	250	badvaddr = istate->pc;
251		251
252	page_table_lock(as, lock);	252	page_table_lock(as, lock);
253		253
254	pte = find_mapping_and_check(as, lock, badvaddr,	254	pte = find_mapping_and_check(as, lock, badvaddr,
255	PF_ACCESS_READ /* FIXME */, istate, &pfrc);	255	PF_ACCESS_READ /* FIXME */, istate, &pfrc);
256	if (!pte) {	256	if (!pte) {
257	switch (pfrc) {	257	switch (pfrc) {
258	case AS_PF_FAULT:	258	case AS_PF_FAULT:
259	goto fail;	259	goto fail;
260	break;	260	break;
261	case AS_PF_DEFER:	261	case AS_PF_DEFER:
262	/*	262	/*
263	* The page fault came during copy_from_uspace()	263	* The page fault came during copy_from_uspace()
264	* or copy_to_uspace().	264	* or copy_to_uspace().
265	*/	265	*/
266	page_table_unlock(as, lock);	266	page_table_unlock(as, lock);
267	return;	267	return;
268	default:	268	default:
269	panic("Unexpected pfrc (%d).", pfrc);	269	panic("Unexpected pfrc (%d).", pfrc);
270	}	270	}
271	}	271	}
272		272
273	pte->accessed = 1; /* Record access to PTE */	273	pte->accessed = 1; /* Record access to PTE */
274	pht_insert(badvaddr, pte);	274	pht_insert(badvaddr, pte);
275		275
276	page_table_unlock(as, lock);	276	page_table_unlock(as, lock);
277	return;	277	return;
278		278
279	fail:	279	fail:
280	page_table_unlock(as, lock);	280	page_table_unlock(as, lock);
281	pht_refill_fail(badvaddr, istate);	281	pht_refill_fail(badvaddr, istate);
282	}	282	}
283		283
284		284
285	/** Process Instruction/Data Storage Exception in Real Mode	285	/** Process Instruction/Data Storage Exception in Real Mode
286	*	286	*
287	* @param n Exception vector number.	287	* @param n Exception vector number.
288	* @param istate Interrupted register context.	288	* @param istate Interrupted register context.
289	*	289	*
290	*/	290	*/
291	bool pht_refill_real(int n, istate_t *istate)	291	bool pht_refill_real(int n, istate_t *istate)
292	{	292	{
293	uintptr_t badvaddr;	293	uintptr_t badvaddr;
294		294
295	if (n == VECTOR_DATA_STORAGE)	295	if (n == VECTOR_DATA_STORAGE)
296	badvaddr = istate->dar;	296	badvaddr = istate->dar;
297	else	297	else
298	badvaddr = istate->pc;	298	badvaddr = istate->pc;
299		299
300	uint32_t physmem;	300	uint32_t physmem;
301	asm volatile (	301	asm volatile (
302	"mfsprg3 %0\n"	302	"mfsprg3 %0\n"
303	: "=r" (physmem)	303	: "=r" (physmem)
304	);	304	);
305		305
306	if ((badvaddr < PA2KA(0)) \|\| (badvaddr >= PA2KA(physmem)))	306	if ((badvaddr < PA2KA(0)) \|\| (badvaddr >= PA2KA(physmem)))
307	return false;	307	return false;
308		308
309	uint32_t page = (badvaddr >> 12) & 0xffff;	309	uint32_t page = (badvaddr >> 12) & 0xffff;
310	uint32_t api = (badvaddr >> 22) & 0x3f;	310	uint32_t api = (badvaddr >> 22) & 0x3f;
311		311
312	uint32_t vsid;	312	uint32_t vsid;
313	asm volatile (	313	asm volatile (
314	"mfsrin %0, %1\n"	314	"mfsrin %0, %1\n"
315	: "=r" (vsid)	315	: "=r" (vsid)
316	: "r" (badvaddr)	316	: "r" (badvaddr)
317	);	317	);
318		318
319	uint32_t sdr1;	319	uint32_t sdr1;
320	asm volatile (	320	asm volatile (
321	"mfsdr1 %0\n"	321	"mfsdr1 %0\n"
322	: "=r" (sdr1)	322	: "=r" (sdr1)
323	);	323	);
324	phte_t phte_real = (phte_t ) (sdr1 & 0xffff0000);	324	phte_t phte_real = (phte_t ) (sdr1 & 0xffff0000);
325		325
326	/* Primary hash (xor) */	326	/* Primary hash (xor) */
327	uint32_t h = 0;	327	uint32_t h = 0;
328	uint32_t hash = vsid ^ page;	328	uint32_t hash = vsid ^ page;
329	uint32_t base = (hash & 0x3ff) << 3;	329	uint32_t base = (hash & 0x3ff) << 3;
330	uint32_t i;	330	uint32_t i;
331	bool found = false;	331	bool found = false;
332		332
333	/* Find colliding PTE in PTEG */	333	/* Find colliding PTE in PTEG */
334	for (i = 0; i < 8; i++) {	334	for (i = 0; i < 8; i++) {
335	if ((phte_real[base + i].v)	335	if ((phte_real[base + i].v)
336	&& (phte_real[base + i].vsid == vsid)	336	&& (phte_real[base + i].vsid == vsid)
337	&& (phte_real[base + i].api == api)	337	&& (phte_real[base + i].api == api)
338	&& (phte_real[base + i].h == 0)) {	338	&& (phte_real[base + i].h == 0)) {
339	found = true;	339	found = true;
340	break;	340	break;
341	}	341	}
342	}	342	}
343		343
344	if (!found) {	344	if (!found) {
345	/* Find unused PTE in PTEG */	345	/* Find unused PTE in PTEG */
346	for (i = 0; i < 8; i++) {	346	for (i = 0; i < 8; i++) {
347	if (!phte_real[base + i].v) {	347	if (!phte_real[base + i].v) {
348	found = true;	348	found = true;
349	break;	349	break;
350	}	350	}
351	}	351	}
352	}	352	}
353		353
354	if (!found) {	354	if (!found) {
355	/* Secondary hash (not) */	355	/* Secondary hash (not) */
356	uint32_t base2 = (~hash & 0x3ff) << 3;	356	uint32_t base2 = (~hash & 0x3ff) << 3;
357		357
358	/* Find colliding PTE in PTEG */	358	/* Find colliding PTE in PTEG */
359	for (i = 0; i < 8; i++) {	359	for (i = 0; i < 8; i++) {
360	if ((phte_real[base2 + i].v)	360	if ((phte_real[base2 + i].v)
361	&& (phte_real[base2 + i].vsid == vsid)	361	&& (phte_real[base2 + i].vsid == vsid)
362	&& (phte_real[base2 + i].api == api)	362	&& (phte_real[base2 + i].api == api)
363	&& (phte_real[base2 + i].h == 1)) {	363	&& (phte_real[base2 + i].h == 1)) {
364	found = true;	364	found = true;
365	base = base2;	365	base = base2;
366	h = 1;	366	h = 1;
367	break;	367	break;
368	}	368	}
369	}	369	}
370		370
371	if (!found) {	371	if (!found) {
372	/* Find unused PTE in PTEG */	372	/* Find unused PTE in PTEG */
373	for (i = 0; i < 8; i++) {	373	for (i = 0; i < 8; i++) {
374	if (!phte_real[base2 + i].v) {	374	if (!phte_real[base2 + i].v) {
375	found = true;	375	found = true;
376	base = base2;	376	base = base2;
377	h = 1;	377	h = 1;
378	break;	378	break;
379	}	379	}
380	}	380	}
381	}	381	}
382		382
383	if (!found) {	383	if (!found) {
384	/* Use secondary hash to avoid collisions	384	/* Use secondary hash to avoid collisions
385	with usual PHT refill handler. */	385	with usual PHT refill handler. */
386	i = RANDI(seed_real) % 8;	386	i = RANDI(seed_real) % 8;
387	base = base2;	387	base = base2;
388	h = 1;	388	h = 1;
389	}	389	}
390	}	390	}
391		391
392	phte_real[base + i].v = 1;	392	phte_real[base + i].v = 1;
393	phte_real[base + i].vsid = vsid;	393	phte_real[base + i].vsid = vsid;
394	phte_real[base + i].h = h;	394	phte_real[base + i].h = h;
395	phte_real[base + i].api = api;	395	phte_real[base + i].api = api;
396	phte_real[base + i].rpn = KA2PA(badvaddr) >> 12;	396	phte_real[base + i].rpn = KA2PA(badvaddr) >> 12;
397	phte_real[base + i].r = 0;	397	phte_real[base + i].r = 0;
398	phte_real[base + i].c = 0;	398	phte_real[base + i].c = 0;
399	phte_real[base + i].wimg = 0;	399	phte_real[base + i].wimg = 0;
400	phte_real[base + i].pp = 2; // FIXME	400	phte_real[base + i].pp = 2; // FIXME
401		401
402	return true;	402	return true;
403	}	403	}
404		404
405		405
406	/** Process ITLB/DTLB Miss Exception in Real Mode	406	/** Process ITLB/DTLB Miss Exception in Real Mode
407	*	407	*
408	*	408	*
409	*/	409	*/
410	void tlb_refill_real(int n, uint32_t tlbmiss, ptehi_t ptehi, ptelo_t ptelo, istate_t *istate)	410	void tlb_refill_real(int n, uint32_t tlbmiss, ptehi_t ptehi, ptelo_t ptelo, istate_t *istate)
411	{	411	{
412	uint32_t badvaddr = tlbmiss & 0xfffffffc;	412	uint32_t badvaddr = tlbmiss & 0xfffffffc;
413		413
414	uint32_t physmem;	414	uint32_t physmem;
415	asm volatile (	415	asm volatile (
416	"mfsprg3 %0\n"	416	"mfsprg3 %0\n"
417	: "=r" (physmem)	417	: "=r" (physmem)
418	);	418	);
419		419
420	if ((badvaddr < PA2KA(0)) \|\| (badvaddr >= PA2KA(physmem)))	420	if ((badvaddr < PA2KA(0)) \|\| (badvaddr >= PA2KA(physmem)))
421	return; // FIXME	421	return; // FIXME
422		422
423	ptelo.rpn = KA2PA(badvaddr) >> 12;	423	ptelo.rpn = KA2PA(badvaddr) >> 12;
424	ptelo.wimg = 0;	424	ptelo.wimg = 0;
425	ptelo.pp = 2; // FIXME	425	ptelo.pp = 2; // FIXME
426		426
427	uint32_t index = 0;	427	uint32_t index = 0;
428	asm volatile (	428	asm volatile (
429	"mtspr 981, %0\n"	429	"mtspr 981, %0\n"
430	"mtspr 982, %1\n"	430	"mtspr 982, %1\n"
431	"tlbld %2\n"	431	"tlbld %2\n"
432	"tlbli %2\n"	432	"tlbli %2\n"
433	: "=r" (index)	433	: "=r" (index)
434	: "r" (ptehi),	434	: "r" (ptehi),
435	"r" (ptelo)	435	"r" (ptelo)
436	);	436	);
437	}	437	}
438		438
439		439
440	void tlb_arch_init(void)	440	void tlb_arch_init(void)
441	{	441	{
442	tlb_invalidate_all();	442	tlb_invalidate_all();
443	}	443	}
444		444
445		445
446	void tlb_invalidate_all(void)	446	void tlb_invalidate_all(void)
447	{	447	{
448	uint32_t index;	448	uint32_t index;
449	asm volatile (	449	asm volatile (
450	"li %0, 0\n"	450	"li %0, 0\n"
451	"sync\n"	451	"sync\n"
452		452
453	TLB_FLUSH	453	TLB_FLUSH
454	TLB_FLUSH	454	TLB_FLUSH
455	TLB_FLUSH	455	TLB_FLUSH
456	TLB_FLUSH	456	TLB_FLUSH
457	TLB_FLUSH	457	TLB_FLUSH
458	TLB_FLUSH	458	TLB_FLUSH
459	TLB_FLUSH	459	TLB_FLUSH
460	TLB_FLUSH	460	TLB_FLUSH
461		461
462	TLB_FLUSH	462	TLB_FLUSH
463	TLB_FLUSH	463	TLB_FLUSH
464	TLB_FLUSH	464	TLB_FLUSH
465	TLB_FLUSH	465	TLB_FLUSH
466	TLB_FLUSH	466	TLB_FLUSH
467	TLB_FLUSH	467	TLB_FLUSH
468	TLB_FLUSH	468	TLB_FLUSH
469	TLB_FLUSH	469	TLB_FLUSH
470		470
471	TLB_FLUSH	471	TLB_FLUSH
472	TLB_FLUSH	472	TLB_FLUSH
473	TLB_FLUSH	473	TLB_FLUSH
474	TLB_FLUSH	474	TLB_FLUSH
475	TLB_FLUSH	475	TLB_FLUSH
476	TLB_FLUSH	476	TLB_FLUSH
477	TLB_FLUSH	477	TLB_FLUSH
478	TLB_FLUSH	478	TLB_FLUSH
479		479
480	TLB_FLUSH	480	TLB_FLUSH
481	TLB_FLUSH	481	TLB_FLUSH
482	TLB_FLUSH	482	TLB_FLUSH
483	TLB_FLUSH	483	TLB_FLUSH
484	TLB_FLUSH	484	TLB_FLUSH
485	TLB_FLUSH	485	TLB_FLUSH
486	TLB_FLUSH	486	TLB_FLUSH
487	TLB_FLUSH	487	TLB_FLUSH
488		488
489	TLB_FLUSH	489	TLB_FLUSH
490	TLB_FLUSH	490	TLB_FLUSH
491	TLB_FLUSH	491	TLB_FLUSH
492	TLB_FLUSH	492	TLB_FLUSH
493	TLB_FLUSH	493	TLB_FLUSH
494	TLB_FLUSH	494	TLB_FLUSH
495	TLB_FLUSH	495	TLB_FLUSH
496	TLB_FLUSH	496	TLB_FLUSH
497		497
498	TLB_FLUSH	498	TLB_FLUSH
499	TLB_FLUSH	499	TLB_FLUSH
500	TLB_FLUSH	500	TLB_FLUSH

Subversion Repositories HelenOS

(root)/branches/tracing/kernel/arch/ppc32/src/mm/tlb.c – Rev 4377 → 4692