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Line 90... Line 90...
90
#endif  
90
#endif  
91
}
91
}
92
 
92
 
93
/** Invalidate entries belonging to an address space.
93
/** Invalidate entries belonging to an address space.
94
 *
94
 *
95
 * @param asid Address space identifier.
95
 * @param asid      Address space identifier.
96
 */
96
 */
97
void tlb_invalidate_asid(asid_t asid)
97
void tlb_invalidate_asid(asid_t asid)
98
{
98
{
99
    tlb_invalidate_all();
99
    tlb_invalidate_all();
100
}
100
}
Line 129... Line 129...
129
        b++;
129
        b++;
130
    b >>= 1;
130
    b >>= 1;
131
    uint64_t ps;
131
    uint64_t ps;
132
   
132
   
133
    switch (b) {
133
    switch (b) {
134
    case 0: /*cnt 1-3*/
134
    case 0: /* cnt 1 - 3 */
135
        ps = PAGE_WIDTH;
135
        ps = PAGE_WIDTH;
136
        break;
136
        break;
137
    case 1: /*cnt 4-15*/
137
    case 1: /* cnt 4 - 15 */
138
        /*cnt=((cnt-1)/4)+1;*/
-
 
139
        ps = PAGE_WIDTH+2;
138
        ps = PAGE_WIDTH + 2;
140
        va &= ~((1<<ps)-1);
139
        va &= ~((1 << ps) - 1);
141
        break;
140
        break;
142
    case 2: /*cnt 16-63*/
141
    case 2: /* cnt 16 - 63 */
143
        /*cnt=((cnt-1)/16)+1;*/
-
 
144
        ps = PAGE_WIDTH+4;
142
        ps = PAGE_WIDTH + 4;
145
        va &= ~((1<<ps)-1);
143
        va &= ~((1 << ps) - 1);
146
        break;
144
        break;
147
    case 3: /*cnt 64-255*/
145
    case 3: /* cnt 64 - 255 */
148
        /*cnt=((cnt-1)/64)+1;*/
-
 
149
        ps = PAGE_WIDTH+6;
146
        ps = PAGE_WIDTH + 6;
150
        va &= ~((1<<ps)-1);
147
        va &= ~((1 << ps) - 1);
151
        break;
148
        break;
152
    case 4: /*cnt 256-1023*/
149
    case 4: /* cnt 256 - 1023 */
153
        /*cnt=((cnt-1)/256)+1;*/
-
 
154
        ps = PAGE_WIDTH+8;
150
        ps = PAGE_WIDTH + 8;
155
        va &= ~((1<<ps)-1);
151
        va &= ~((1 << ps) - 1);
156
        break;
152
        break;
157
    case 5: /*cnt 1024-4095*/
153
    case 5: /* cnt 1024 - 4095 */
158
        /*cnt=((cnt-1)/1024)+1;*/
-
 
159
        ps = PAGE_WIDTH+10;
154
        ps = PAGE_WIDTH + 10;
160
        va &= ~((1<<ps)-1);
155
        va &= ~((1 << ps) - 1);
161
        break;
156
        break;
162
    case 6: /*cnt 4096-16383*/
157
    case 6: /* cnt 4096 - 16383 */
163
        /*cnt=((cnt-1)/4096)+1;*/
-
 
164
        ps = PAGE_WIDTH+12;
158
        ps = PAGE_WIDTH + 12;
165
        va &= ~((1<<ps)-1);
159
        va &= ~((1 << ps) - 1);
166
        break;
160
        break;
167
    case 7: /*cnt 16384-65535*/
161
    case 7: /* cnt 16384 - 65535 */
168
    case 8: /*cnt 65536-(256K-1)*/
162
    case 8: /* cnt 65536 - (256K - 1) */
169
        /*cnt=((cnt-1)/16384)+1;*/
-
 
170
        ps = PAGE_WIDTH+14;
163
        ps = PAGE_WIDTH + 14;
171
        va &= ~((1<<ps)-1);
164
        va &= ~((1 << ps) - 1);
172
        break;
165
        break;
173
    default:
166
    default:
174
        /*cnt=((cnt-1)/(16384*16))+1;*/
-
 
175
        ps=PAGE_WIDTH+18;
167
        ps = PAGE_WIDTH + 18;
176
        va&=~((1<<ps)-1);
168
        va &= ~((1 << ps) - 1);
177
        break;
169
        break;
178
    }
170
    }
179
    /*cnt+=(page!=va);*/
-
 
180
    for(; va<(page+cnt*(PAGE_SIZE)); va += (1<<ps)) {
171
    for(; va < (page + cnt * PAGE_SIZE); va += (1 << ps))
181
        asm volatile (
-
 
182
            "ptc.l %0,%1;;"
-
 
183
            :
-
 
184
            : "r" (va), "r" (ps<<2)
172
        asm volatile ("ptc.l %0, %1;;" :: "r" (va), "r" (ps << 2));
185
        );
-
 
186
    }
-
 
187
    srlz_d();
173
    srlz_d();
188
    srlz_i();
174
    srlz_i();
189
   
175
   
190
    if (restore_rr) {
176
    if (restore_rr) {
191
        rr_write(VA2VRN(va), rr.word);
177
        rr_write(VA2VRN(va), rr.word);
Line 194... Line 180...
194
    }
180
    }
195
}
181
}
196
 
182
 
197
/** Insert data into data translation cache.
183
/** Insert data into data translation cache.
198
 *
184
 *
199
 * @param va Virtual page address.
185
 * @param va        Virtual page address.
200
 * @param asid Address space identifier.
186
 * @param asid      Address space identifier.
201
 * @param entry The rest of TLB entry as required by TLB insertion format.
187
 * @param entry     The rest of TLB entry as required by TLB insertion
-
 
188
 *          format.
202
 */
189
 */
203
void dtc_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry)
190
void dtc_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry)
204
{
191
{
205
    tc_mapping_insert(va, asid, entry, true);
192
    tc_mapping_insert(va, asid, entry, true);
206
}
193
}
207
 
194
 
208
/** Insert data into instruction translation cache.
195
/** Insert data into instruction translation cache.
209
 *
196
 *
210
 * @param va Virtual page address.
197
 * @param va        Virtual page address.
211
 * @param asid Address space identifier.
198
 * @param asid      Address space identifier.
212
 * @param entry The rest of TLB entry as required by TLB insertion format.
199
 * @param entry     The rest of TLB entry as required by TLB insertion
-
 
200
 *          format.
213
 */
201
 */
214
void itc_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry)
202
void itc_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry)
215
{
203
{
216
    tc_mapping_insert(va, asid, entry, false);
204
    tc_mapping_insert(va, asid, entry, false);
217
}
205
}
218
 
206
 
219
/** Insert data into instruction or data translation cache.
207
/** Insert data into instruction or data translation cache.
220
 *
208
 *
221
 * @param va Virtual page address.
209
 * @param va        Virtual page address.
222
 * @param asid Address space identifier.
210
 * @param asid      Address space identifier.
223
 * @param entry The rest of TLB entry as required by TLB insertion format.
211
 * @param entry     The rest of TLB entry as required by TLB insertion
-
 
212
 *          format.
224
 * @param dtc If true, insert into data translation cache, use instruction translation cache otherwise.
213
 * @param dtc       If true, insert into data translation cache, use
-
 
214
 *          instruction translation cache otherwise.
225
 */
215
 */
226
void tc_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, bool dtc)
216
void tc_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, bool dtc)
227
{
217
{
228
    region_register rr;
218
    region_register rr;
229
    bool restore_rr = false;
219
    bool restore_rr = false;
Line 242... Line 232...
242
        srlz_d();
232
        srlz_d();
243
        srlz_i();
233
        srlz_i();
244
    }
234
    }
245
   
235
   
246
    asm volatile (
236
    asm volatile (
247
        "mov r8=psr;;\n"
237
        "mov r8 = psr;;\n"
248
        "rsm %0;;\n"            /* PSR_IC_MASK */
238
        "rsm %0;;\n"            /* PSR_IC_MASK */
249
        "srlz.d;;\n"
239
        "srlz.d;;\n"
250
        "srlz.i;;\n"
240
        "srlz.i;;\n"
251
        "mov cr.ifa=%1\n"       /* va */
241
        "mov cr.ifa = %1\n"     /* va */
252
        "mov cr.itir=%2;;\n"        /* entry.word[1] */
242
        "mov cr.itir = %2;;\n"      /* entry.word[1] */
253
        "cmp.eq p6,p7 = %4,r0;;\n"  /* decide between itc and dtc */
243
        "cmp.eq p6,p7 = %4,r0;;\n"  /* decide between itc and dtc */
254
        "(p6) itc.i %3;;\n"
244
        "(p6) itc.i %3;;\n"
255
        "(p7) itc.d %3;;\n"
245
        "(p7) itc.d %3;;\n"
256
        "mov psr.l=r8;;\n"
246
        "mov psr.l = r8;;\n"
257
        "srlz.d;;\n"
247
        "srlz.d;;\n"
258
        :
248
        :
259
        : "i" (PSR_IC_MASK), "r" (va), "r" (entry.word[1]), "r" (entry.word[0]), "r" (dtc)
249
        : "i" (PSR_IC_MASK), "r" (va), "r" (entry.word[1]),
-
 
250
            "r" (entry.word[0]), "r" (dtc)
260
        : "p6", "p7", "r8"
251
        : "p6", "p7", "r8"
261
    );
252
    );
262
   
253
   
263
    if (restore_rr) {
254
    if (restore_rr) {
264
        rr_write(VA2VRN(va), rr.word);
255
        rr_write(VA2VRN(va), rr.word);
Line 267... Line 258...
267
    }
258
    }
268
}
259
}
269
 
260
 
270
/** Insert data into instruction translation register.
261
/** Insert data into instruction translation register.
271
 *
262
 *
272
 * @param va Virtual page address.
263
 * @param va        Virtual page address.
273
 * @param asid Address space identifier.
264
 * @param asid      Address space identifier.
274
 * @param entry The rest of TLB entry as required by TLB insertion format.
265
 * @param entry     The rest of TLB entry as required by TLB insertion
-
 
266
 *          format.
275
 * @param tr Translation register.
267
 * @param tr        Translation register.
276
 */
268
 */
-
 
269
void
277
void itr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, index_t tr)
270
itr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, index_t tr)
278
{
271
{
279
    tr_mapping_insert(va, asid, entry, false, tr);
272
    tr_mapping_insert(va, asid, entry, false, tr);
280
}
273
}
281
 
274
 
282
/** Insert data into data translation register.
275
/** Insert data into data translation register.
283
 *
276
 *
284
 * @param va Virtual page address.
277
 * @param va        Virtual page address.
285
 * @param asid Address space identifier.
278
 * @param asid      Address space identifier.
286
 * @param entry The rest of TLB entry as required by TLB insertion format.
279
 * @param entry     The rest of TLB entry as required by TLB insertion
-
 
280
 *          format.
287
 * @param tr Translation register.
281
 * @param tr        Translation register.
288
 */
282
 */
-
 
283
void
289
void dtr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, index_t tr)
284
dtr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, index_t tr)
290
{
285
{
291
    tr_mapping_insert(va, asid, entry, true, tr);
286
    tr_mapping_insert(va, asid, entry, true, tr);
292
}
287
}
293
 
288
 
294
/** Insert data into instruction or data translation register.
289
/** Insert data into instruction or data translation register.
295
 *
290
 *
296
 * @param va Virtual page address.
291
 * @param va        Virtual page address.
297
 * @param asid Address space identifier.
292
 * @param asid      Address space identifier.
298
 * @param entry The rest of TLB entry as required by TLB insertion format.
293
 * @param entry     The rest of TLB entry as required by TLB insertion
-
 
294
 *          format.
299
 * @param dtr If true, insert into data translation register, use instruction translation register otherwise.
295
 * @param dtr       If true, insert into data translation register, use
-
 
296
 *          instruction translation register otherwise.
300
 * @param tr Translation register.
297
 * @param tr        Translation register.
301
 */
298
 */
-
 
299
void
302
void tr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, bool dtr, index_t tr)
300
tr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, bool dtr,
-
 
301
    index_t tr)
303
{
302
{
304
    region_register rr;
303
    region_register rr;
305
    bool restore_rr = false;
304
    bool restore_rr = false;
306
 
305
 
307
    rr.word = rr_read(VA2VRN(va));
306
    rr.word = rr_read(VA2VRN(va));
Line 318... Line 317...
318
        srlz_d();
317
        srlz_d();
319
        srlz_i();
318
        srlz_i();
320
    }
319
    }
321
 
320
 
322
    asm volatile (
321
    asm volatile (
323
        "mov r8=psr;;\n"
322
        "mov r8 = psr;;\n"
324
        "rsm %0;;\n"            /* PSR_IC_MASK */
323
        "rsm %0;;\n"            /* PSR_IC_MASK */
325
        "srlz.d;;\n"
324
        "srlz.d;;\n"
326
        "srlz.i;;\n"
325
        "srlz.i;;\n"
327
        "mov cr.ifa=%1\n"           /* va */         
326
        "mov cr.ifa = %1\n"         /* va */         
328
        "mov cr.itir=%2;;\n"        /* entry.word[1] */
327
        "mov cr.itir = %2;;\n"      /* entry.word[1] */
329
        "cmp.eq p6,p7=%5,r0;;\n"    /* decide between itr and dtr */
328
        "cmp.eq p6,p7 = %5,r0;;\n"  /* decide between itr and dtr */
330
        "(p6) itr.i itr[%4]=%3;;\n"
329
        "(p6) itr.i itr[%4] = %3;;\n"
331
        "(p7) itr.d dtr[%4]=%3;;\n"
330
        "(p7) itr.d dtr[%4] = %3;;\n"
332
        "mov psr.l=r8;;\n"
331
        "mov psr.l = r8;;\n"
333
        "srlz.d;;\n"
332
        "srlz.d;;\n"
334
        :
333
        :
335
        : "i" (PSR_IC_MASK), "r" (va), "r" (entry.word[1]), "r" (entry.word[0]), "r" (tr), "r" (dtr)
334
        : "i" (PSR_IC_MASK), "r" (va), "r" (entry.word[1]),
-
 
335
            "r" (entry.word[0]), "r" (tr), "r" (dtr)
336
        : "p6", "p7", "r8"
336
        : "p6", "p7", "r8"
337
    );
337
    );
338
   
338
   
339
    if (restore_rr) {
339
    if (restore_rr) {
340
        rr_write(VA2VRN(va), rr.word);
340
        rr_write(VA2VRN(va), rr.word);
Line 343... Line 343...
343
    }
343
    }
344
}
344
}
345
 
345
 
346
/** Insert data into DTLB.
346
/** Insert data into DTLB.
347
 *
347
 *
348
 * @param page Virtual page address including VRN bits.
348
 * @param page      Virtual page address including VRN bits.
349
 * @param frame Physical frame address.
349
 * @param frame     Physical frame address.
350
 * @param dtr If true, insert into data translation register, use data translation cache otherwise.
350
 * @param dtr       If true, insert into data translation register, use data
-
 
351
 *          translation cache otherwise.
351
 * @param tr Translation register if dtr is true, ignored otherwise.
352
 * @param tr        Translation register if dtr is true, ignored otherwise.
352
 */
353
 */
-
 
354
void
353
void dtlb_kernel_mapping_insert(uintptr_t page, uintptr_t frame, bool dtr, index_t tr)
355
dtlb_kernel_mapping_insert(uintptr_t page, uintptr_t frame, bool dtr,
-
 
356
    index_t tr)
354
{
357
{
355
    tlb_entry_t entry;
358
    tlb_entry_t entry;
356
   
359
   
357
    entry.word[0] = 0;
360
    entry.word[0] = 0;
358
    entry.word[1] = 0;
361
    entry.word[1] = 0;
Line 374... Line 377...
374
 
377
 
375
/** Purge kernel entries from DTR.
378
/** Purge kernel entries from DTR.
376
 *
379
 *
377
 * Purge DTR entries used by the kernel.
380
 * Purge DTR entries used by the kernel.
378
 *
381
 *
379
 * @param page Virtual page address including VRN bits.
382
 * @param page      Virtual page address including VRN bits.
380
 * @param width Width of the purge in bits.
383
 * @param width     Width of the purge in bits.
381
 */
384
 */
382
void dtr_purge(uintptr_t page, count_t width)
385
void dtr_purge(uintptr_t page, count_t width)
383
{
386
{
384
    asm volatile ("ptr.d %0, %1\n" : : "r" (page), "r" (width<<2));
387
    asm volatile ("ptr.d %0, %1\n" : : "r" (page), "r" (width << 2));
385
}
388
}
386
 
389
 
387
 
390
 
388
/** Copy content of PTE into data translation cache.
391
/** Copy content of PTE into data translation cache.
389
 *
392
 *
390
 * @param t PTE.
393
 * @param t     PTE.
391
 */
394
 */
392
void dtc_pte_copy(pte_t *t)
395
void dtc_pte_copy(pte_t *t)
393
{
396
{
394
    tlb_entry_t entry;
397
    tlb_entry_t entry;
395
 
398
 
Line 411... Line 414...
411
#endif  
414
#endif  
412
}
415
}
413
 
416
 
414
/** Copy content of PTE into instruction translation cache.
417
/** Copy content of PTE into instruction translation cache.
415
 *
418
 *
416
 * @param t PTE.
419
 * @param t     PTE.
417
 */
420
 */
418
void itc_pte_copy(pte_t *t)
421
void itc_pte_copy(pte_t *t)
419
{
422
{
420
    tlb_entry_t entry;
423
    tlb_entry_t entry;
421
 
424
 
Line 438... Line 441...
438
#endif  
441
#endif  
439
}
442
}
440
 
443
 
441
/** Instruction TLB fault handler for faults with VHPT turned off.
444
/** Instruction TLB fault handler for faults with VHPT turned off.
442
 *
445
 *
443
 * @param vector Interruption vector.
446
 * @param vector        Interruption vector.
444
 * @param istate Structure with saved interruption state.
447
 * @param istate        Structure with saved interruption state.
445
 */
448
 */
446
void alternate_instruction_tlb_fault(uint64_t vector, istate_t *istate)
449
void alternate_instruction_tlb_fault(uint64_t vector, istate_t *istate)
447
{
450
{
448
    region_register rr;
451
    region_register rr;
449
    rid_t rid;
452
    rid_t rid;
Line 467... Line 470...
467
        /*
470
        /*
468
         * Forward the page fault to address space page fault handler.
471
         * Forward the page fault to address space page fault handler.
469
         */
472
         */
470
        page_table_unlock(AS, true);
473
        page_table_unlock(AS, true);
471
        if (as_page_fault(va, PF_ACCESS_EXEC, istate) == AS_PF_FAULT) {
474
        if (as_page_fault(va, PF_ACCESS_EXEC, istate) == AS_PF_FAULT) {
472
            fault_if_from_uspace(istate,"Page fault at %p",va);
475
            fault_if_from_uspace(istate,"Page fault at %p.",va);
473
            panic("%s: va=%p, rid=%d, iip=%p\n", __func__, va, rid, istate->cr_iip);
476
            panic("%s: va=%p, rid=%d, iip=%p.", __func__, va, rid,
-
 
477
                istate->cr_iip);
474
        }
478
        }
475
    }
479
    }
476
}
480
}
477
 
481
 
478
 
-
 
479
 
-
 
480
static int is_io_page_accessible(int page)
482
static int is_io_page_accessible(int page)
481
{
483
{
-
 
484
    if (TASK->arch.iomap)
482
    if(TASK->arch.iomap) return bitmap_get(TASK->arch.iomap,page);
485
        return bitmap_get(TASK->arch.iomap, page);
-
 
486
    else
483
    else return 0;
487
        return 0;
484
}
488
}
485
 
489
 
486
#define IO_FRAME_BASE 0xFFFFC000000
490
#define IO_FRAME_BASE 0xFFFFC000000
487
 
491
 
-
 
492
/**
488
/** There is special handling of memmaped lagacy io, because
493
 * There is special handling of memory mapped legacy io, because of 4KB sized
489
 * of 4KB sized access
-
 
490
 * only for userspace
494
 * access for userspace.
491
 *
-
 
492
 * @param va virtual address of page fault
-
 
493
 * @param istate Structure with saved interruption state.
-
 
494
 *
495
 *
-
 
496
 * @param va        Virtual address of page fault.
-
 
497
 * @param istate    Structure with saved interruption state.
495
 *
498
 *
496
 * @return 1 on success, 0 on fail
499
 * @return      One on success, zero on failure.
497
 */
500
 */
498
static int try_memmap_io_insertion(uintptr_t va, istate_t *istate)
501
static int try_memmap_io_insertion(uintptr_t va, istate_t *istate)
499
{
502
{
500
    if((va >= IO_OFFSET ) && (va < IO_OFFSET + (1<<IO_PAGE_WIDTH)))
503
    if ((va >= IO_OFFSET ) && (va < IO_OFFSET + (1 << IO_PAGE_WIDTH))) {
501
        if(TASK){
504
        if (TASK) {
502
           
-
 
503
            uint64_t io_page=(va &  ((1<<IO_PAGE_WIDTH)-1)) >> (USPACE_IO_PAGE_WIDTH);
505
            uint64_t io_page = (va & ((1 << IO_PAGE_WIDTH) - 1)) >>
504
            if(is_io_page_accessible(io_page)){
-
 
505
                //printf("Insert %llX\n",va);
506
                USPACE_IO_PAGE_WIDTH;
506
 
507
 
-
 
508
            if (is_io_page_accessible(io_page)) {
507
                uint64_t page,frame;
509
                uint64_t page, frame;
508
 
510
 
-
 
511
                page = IO_OFFSET +
509
                page = IO_OFFSET + (1 << USPACE_IO_PAGE_WIDTH) * io_page;
512
                    (1 << USPACE_IO_PAGE_WIDTH) * io_page;
-
 
513
                frame = IO_FRAME_BASE +
510
                frame = IO_FRAME_BASE + (1 << USPACE_IO_PAGE_WIDTH) * io_page;
514
                    (1 << USPACE_IO_PAGE_WIDTH) * io_page;
511
 
-
 
512
 
515
 
513
                tlb_entry_t entry;
516
                tlb_entry_t entry;
514
   
517
   
515
                entry.word[0] = 0;
518
                entry.word[0] = 0;
516
                entry.word[1] = 0;
519
                entry.word[1] = 0;
517
   
520
   
518
                entry.p = true;         /* present */
521
                entry.p = true;     /* present */
519
                entry.ma = MA_UNCACHEABLE;     
522
                entry.ma = MA_UNCACHEABLE;     
520
                entry.a = true;         /* already accessed */
523
                entry.a = true;     /* already accessed */
521
                entry.d = true;         /* already dirty */
524
                entry.d = true;     /* already dirty */
522
                entry.pl = PL_USER;
525
                entry.pl = PL_USER;
523
                entry.ar = AR_READ | AR_WRITE;
526
                entry.ar = AR_READ | AR_WRITE;
524
                entry.ppn = frame >> PPN_SHIFT;    //MUSIM spocitat frame
527
                entry.ppn = frame >> PPN_SHIFT;
525
                entry.ps = USPACE_IO_PAGE_WIDTH;
528
                entry.ps = USPACE_IO_PAGE_WIDTH;
526
   
529
   
527
                dtc_mapping_insert(page, TASK->as->asid, entry); //Musim zjistit ASID
530
                dtc_mapping_insert(page, TASK->as->asid, entry);
528
                return 1;
531
                return 1;
529
            }else {
532
            } else {
530
                fault_if_from_uspace(istate,"IO access fault at %p",va);
533
                fault_if_from_uspace(istate,
531
                return 0;
534
                    "IO access fault at %p.", va);
532
            }      
535
            }
533
        } else
536
        }
534
            return 0;
-
 
535
    else
537
    }
536
        return 0;
-
 
537
       
538
       
538
    return 0;
539
    return 0;
539
 
-
 
540
}
540
}
541
 
541
 
542
 
-
 
543
 
-
 
544
 
-
 
545
/** Data TLB fault handler for faults with VHPT turned off.
542
/** Data TLB fault handler for faults with VHPT turned off.
546
 *
543
 *
547
 * @param vector Interruption vector.
544
 * @param vector    Interruption vector.
548
 * @param istate Structure with saved interruption state.
545
 * @param istate    Structure with saved interruption state.
549
 */
546
 */
550
void alternate_data_tlb_fault(uint64_t vector, istate_t *istate)
547
void alternate_data_tlb_fault(uint64_t vector, istate_t *istate)
551
{
548
{
552
    region_register rr;
549
    region_register rr;
553
    rid_t rid;
550
    rid_t rid;
Line 577... Line 574...
577
         */
574
         */
578
        dtc_pte_copy(t);
575
        dtc_pte_copy(t);
579
        page_table_unlock(AS, true);
576
        page_table_unlock(AS, true);
580
    } else {
577
    } else {
581
        page_table_unlock(AS, true);
578
        page_table_unlock(AS, true);
582
        if (try_memmap_io_insertion(va,istate)) return;
579
        if (try_memmap_io_insertion(va, istate))
-
 
580
            return;
583
        /*
581
        /*
584
         * Forward the page fault to the address space page fault handler.
582
         * Forward the page fault to the address space page fault
-
 
583
         * handler.
585
         */
584
         */
586
        if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) {
585
        if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) {
587
            fault_if_from_uspace(istate,"Page fault at %p",va);
586
            fault_if_from_uspace(istate,"Page fault at %p.",va);
588
            panic("%s: va=%p, rid=%d, iip=%p\n", __func__, va, rid, istate->cr_iip);
587
            panic("%s: va=%p, rid=%d, iip=%p.", __func__, va, rid,
-
 
588
                istate->cr_iip);
589
        }
589
        }
590
    }
590
    }
591
}
591
}
592
 
592
 
593
/** Data nested TLB fault handler.
593
/** Data nested TLB fault handler.
594
 *
594
 *
595
 * This fault should not occur.
595
 * This fault should not occur.
596
 *
596
 *
597
 * @param vector Interruption vector.
597
 * @param vector    Interruption vector.
598
 * @param istate Structure with saved interruption state.
598
 * @param istate    Structure with saved interruption state.
599
 */
599
 */
600
void data_nested_tlb_fault(uint64_t vector, istate_t *istate)
600
void data_nested_tlb_fault(uint64_t vector, istate_t *istate)
601
{
601
{
602
    panic("%s\n", __func__);
602
    panic("%s.", __func__);
603
}
603
}
604
 
604
 
605
/** Data Dirty bit fault handler.
605
/** Data Dirty bit fault handler.
606
 *
606
 *
607
 * @param vector Interruption vector.
607
 * @param vector    Interruption vector.
608
 * @param istate Structure with saved interruption state.
608
 * @param istate    Structure with saved interruption state.
609
 */
609
 */
610
void data_dirty_bit_fault(uint64_t vector, istate_t *istate)
610
void data_dirty_bit_fault(uint64_t vector, istate_t *istate)
611
{
611
{
612
    region_register rr;
612
    region_register rr;
613
    rid_t rid;
613
    rid_t rid;
Line 628... Line 628...
628
         */
628
         */
629
        t->d = true;
629
        t->d = true;
630
        dtc_pte_copy(t);
630
        dtc_pte_copy(t);
631
    } else {
631
    } else {
632
        if (as_page_fault(va, PF_ACCESS_WRITE, istate) == AS_PF_FAULT) {
632
        if (as_page_fault(va, PF_ACCESS_WRITE, istate) == AS_PF_FAULT) {
633
            fault_if_from_uspace(istate,"Page fault at %p",va);
633
            fault_if_from_uspace(istate,"Page fault at %p.",va);
634
            panic("%s: va=%p, rid=%d, iip=%p\n", __func__, va, rid, istate->cr_iip);
634
            panic("%s: va=%p, rid=%d, iip=%p.", __func__, va, rid,
635
            t->d = true;
-
 
636
            dtc_pte_copy(t);
635
                istate->cr_iip);
637
        }
636
        }
638
    }
637
    }
639
    page_table_unlock(AS, true);
638
    page_table_unlock(AS, true);
640
}
639
}
641
 
640
 
642
/** Instruction access bit fault handler.
641
/** Instruction access bit fault handler.
643
 *
642
 *
644
 * @param vector Interruption vector.
643
 * @param vector    Interruption vector.
645
 * @param istate Structure with saved interruption state.
644
 * @param istate    Structure with saved interruption state.
646
 */
645
 */
647
void instruction_access_bit_fault(uint64_t vector, istate_t *istate)
646
void instruction_access_bit_fault(uint64_t vector, istate_t *istate)
648
{
647
{
649
    region_register rr;
648
    region_register rr;
650
    rid_t rid;
649
    rid_t rid;
Line 665... Line 664...
665
         */
664
         */
666
        t->a = true;
665
        t->a = true;
667
        itc_pte_copy(t);
666
        itc_pte_copy(t);
668
    } else {
667
    } else {
669
        if (as_page_fault(va, PF_ACCESS_EXEC, istate) == AS_PF_FAULT) {
668
        if (as_page_fault(va, PF_ACCESS_EXEC, istate) == AS_PF_FAULT) {
670
            fault_if_from_uspace(istate,"Page fault at %p",va);
669
            fault_if_from_uspace(istate, "Page fault at %p.", va);
671
            panic("%s: va=%p, rid=%d, iip=%p\n", __func__, va, rid, istate->cr_iip);
670
            panic("%s: va=%p, rid=%d, iip=%p.", __func__, va, rid,
672
            t->a = true;
-
 
673
            itc_pte_copy(t);
671
                istate->cr_iip);
674
        }
672
        }
675
    }
673
    }
676
    page_table_unlock(AS, true);
674
    page_table_unlock(AS, true);
677
}
675
}
678
 
676
 
Line 702... Line 700...
702
         */
700
         */
703
        t->a = true;
701
        t->a = true;
704
        dtc_pte_copy(t);
702
        dtc_pte_copy(t);
705
    } else {
703
    } else {
706
        if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) {
704
        if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) {
707
            fault_if_from_uspace(istate,"Page fault at %p",va);
705
            fault_if_from_uspace(istate, "Page fault at %p.", va);
708
            panic("%s: va=%p, rid=%d, iip=%p\n", __func__, va, rid, istate->cr_iip);
706
            panic("%s: va=%p, rid=%d, iip=%p.", __func__, va, rid,
709
            t->a = true;
-
 
710
            itc_pte_copy(t);
707
                istate->cr_iip);
711
        }
708
        }
712
    }
709
    }
713
    page_table_unlock(AS, true);
710
    page_table_unlock(AS, true);
714
}
711
}
715
 
712
 
Line 744... Line 741...
744
            dtc_pte_copy(t);
741
            dtc_pte_copy(t);
745
        page_table_unlock(AS, true);
742
        page_table_unlock(AS, true);
746
    } else {
743
    } else {
747
        page_table_unlock(AS, true);
744
        page_table_unlock(AS, true);
748
        if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) {
745
        if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) {
749
            fault_if_from_uspace(istate,"Page fault at %p",va);
746
            fault_if_from_uspace(istate, "Page fault at %p.", va);
750
            panic("%s: va=%p, rid=%d\n", __func__, va, rid);
747
            panic("%s: va=%p, rid=%d.", __func__, va, rid);
751
        }
748
        }
752
    }
749
    }
753
}
750
}
754
 
751
 
-
 
752
void tlb_arch_init(void)
-
 
753
{
-
 
754
}
-
 
755
 
-
 
756
void tlb_print(void)
-
 
757
{
-
 
758
}
-
 
759
 
755
/** @}
760
/** @}
756
 */
761
 */