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Line 135... Line 135...
135
    td->base_32_63 = ((base) >> 32);
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    td->base_32_63 = ((base) >> 32);
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}
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}
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void gdt_tss_setlimit(descriptor_t *d, uint32_t limit)
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void gdt_tss_setlimit(descriptor_t *d, uint32_t limit)
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{
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{
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    struct tss_descriptor *td = (tss_descriptor_t *) d;
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    tss_descriptor_t *td = (tss_descriptor_t *) d;
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    td->limit_0_15 = limit & 0xffff;
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    td->limit_0_15 = limit & 0xffff;
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    td->limit_16_19 = (limit >> 16) & 0xf;
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    td->limit_16_19 = (limit >> 16) & 0xf;
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}
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}
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void idt_setoffset(idescriptor_t *d, uintptr_t offset)
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void idt_setoffset(idescriptor_t *d, uintptr_t offset)
Line 183... Line 183...
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/** Initialize segmentation - code/data/idt tables
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/** Initialize segmentation - code/data/idt tables
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 *
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 *
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 */
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 */
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void pm_init(void)
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void pm_init(void)
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{
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{
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    descriptor_t *gdt_p = (struct descriptor *) gdtr.base;
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    descriptor_t *gdt_p = (descriptor_t *) gdtr.base;
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    tss_descriptor_t *tss_desc;
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    tss_descriptor_t *tss_desc;
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    /*
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    /*
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     * Each CPU has its private GDT and TSS.
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     * Each CPU has its private GDT and TSS.
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     * All CPUs share one IDT.
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     * All CPUs share one IDT.
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     */
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     */
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    if (config.cpu_active == 1) {
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    if (config.cpu_active == 1) {
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        idt_init();
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        idt_init();
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        /*
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        /*
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         * NOTE: bootstrap CPU has statically allocated TSS, because
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         * NOTE: bootstrap CPU has statically allocated TSS, because
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         * the heap hasn't been initialized so far.
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         * the heap hasn't been initialized so far.
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         */
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         */
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        tss_p = &tss;
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        tss_p = &tss;
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    }
-
 
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    else {
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    } else {
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        /* We are going to use malloc, which may return
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        /* We are going to use malloc, which may return
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         * non boot-mapped pointer, initialize the CR3 register
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         * non boot-mapped pointer, initialize the CR3 register
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         * ahead of page_init */
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         * ahead of page_init */
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        write_cr3((uintptr_t) AS_KERNEL->genarch.page_table);
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        write_cr3((uintptr_t) AS_KERNEL->genarch.page_table);
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        tss_p = (struct tss *) malloc(sizeof(tss_t), FRAME_ATOMIC);
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        tss_p = (tss_t *) malloc(sizeof(tss_t), FRAME_ATOMIC);
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        if (!tss_p)
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        if (!tss_p)
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            panic("could not allocate TSS\n");
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            panic("Cannot allocate TSS.");
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    }
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    }
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    tss_initialize(tss_p);
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    tss_initialize(tss_p);
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    tss_desc = (tss_descriptor_t *) (&gdt_p[TSS_DES]);
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    tss_desc = (tss_descriptor_t *) (&gdt_p[TSS_DES]);
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    tss_desc->present = 1;
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    tss_desc->present = 1;
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    tss_desc->type = AR_TSS;
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    tss_desc->type = AR_TSS;
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    tss_desc->dpl = PL_KERNEL;
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    tss_desc->dpl = PL_KERNEL;
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    gdt_tss_setbase(&gdt_p[TSS_DES], (uintptr_t) tss_p);
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    gdt_tss_setbase(&gdt_p[TSS_DES], (uintptr_t) tss_p);
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    gdt_tss_setlimit(&gdt_p[TSS_DES], TSS_BASIC_SIZE - 1);
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    gdt_tss_setlimit(&gdt_p[TSS_DES], TSS_BASIC_SIZE - 1);
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    gdtr_load(&gdtr);
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    gdtr_load(&gdtr);
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    idtr_load(&idtr);
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    idtr_load(&idtr);
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    /*
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    /*
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     * As of this moment, the current CPU has its own GDT pointing
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     * As of this moment, the current CPU has its own GDT pointing
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     * to its own TSS. We just need to load the TR register.
228
     * to its own TSS. We just need to load the TR register.
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     */
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     */
231
    tr_load(gdtselector(TSS_DES));
230
    tr_load(gdtselector(TSS_DES));
232
}
231
}
233
 
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/* Reboot the machine by initiating
-
 
235
 * a triple fault
-
 
236
 */
-
 
237
void arch_reboot(void)
-
 
238
{
-
 
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    preemption_disable();
-
 
240
    ipl_t ipl = interrupts_disable();
-
 
241
   
-
 
242
    memsetb(idt, sizeof(idt), 0);
-
 
243
    idtr_load(&idtr);
-
 
244
   
-
 
245
    interrupts_restore(ipl);
-
 
246
    asm volatile (
-
 
247
        "int $0x03\n"
-
 
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        "cli\n"
-
 
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        "hlt\n"
-
 
250
    );
-
 
251
}
-
 
252
 
-
 
253
/** @}
233
/** @}
254
 */
234
 */