WebSVN – HelenOS – Diff – /branches/sparc/kernel/arch/sparc64/src/sun4v/start.S


#
# Copyright (c) 2005 Jakub Jermar
# Copyright (c) 2008 Pavel Rimsky
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# - Redistributions of source code must retain the above copyright
#   notice, this list of conditions and the following disclaimer.
# - Redistributions in binary form must reproduce the above copyright
#   notice, this list of conditions and the following disclaimer in the
#   documentation and/or other materials provided with the distribution.
# - The name of the author may not be used to endorse or promote products
#   derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
 
#include <arch/arch.h>
#include <arch/stack.h>
#include <arch/sun4v/regdef.h>
#include <arch/sun4v/hypercall.h>
#include <arch/sun4v/arch.h>
#include <arch/sun4v/cpu.h>
#include <arch/mm/pagesize.h>
#include <arch/mm/sun4v/tte.h>
#include <arch/mm/sun4v/mmu.h>
#include <arch/mm/sun4v/tlb.h>
 
.register %g2, #scratch
.register %g3, #scratch
 
.section K_TEXT_START, "ax"
 
#define BSP_FLAG		1
#define PHYSMEM_ADDR_SIZE	56
 
/*
 * Flags set in the TTE data entry mapping the kernel.
 */
#ifdef CONFIG_VIRT_IDX_DCACHE
	#define TTE_FLAGS \
		(1 << TTE_V_SHIFT) \
		| (1 << TTE_EP_SHIFT) \
		| (1 << TTE_CP_SHIFT) \
		| (1 << TTE_CV_SHIFT) \
		| (1 << TTE_P_SHIFT) \
		| (1 << TTE_W_SHIFT)
#else
	#define TTE_FLAGS \
		(1 << TTE_V_SHIFT) \
		| (1 << TTE_EP_SHIFT) \
		| (1 << TTE_CP_SHIFT) \
		| (1 << TTE_P_SHIFT) \
		| (1 << TTE_W_SHIFT)
#endif
 
 
/*
 * Fills a register with a TTE Data item. The item will map the given virtual
 * address to a real address which will be computed by adding the starting
 * address of the physical memory to the virtual address.
 *
 * parameters:
 * 	addr:			virtual address to be mapped
 *	rphysmem_start:		register containing the starting address of the
 *				physical memory
 *	rtmp1:			a register to be used as temporary
 *	rtmp2:			a register to be used as temporary
 *	rd:			register where the result will be saved
 */
#define TTE_DATA(addr, rphysmem_start, rtmp1, rtmp2, rd) \
	setx TTE_FLAGS | PAGESIZE_4M, rtmp1, rd; \
	add rd, rphysmem_start, rd; \
	setx (addr), rtmp1, rtmp2; \
	add rd, rtmp2, rd;
 
/*
 * Here is where the kernel is passed control from the boot loader.
 * 
 * The registers are expected to be in this state:
 * - %o0 starting address of physical memory + bootstrap processor flag
 * 	bits 63...1:	physical memory starting address / 2
 *	bit 0:		non-zero on BSP processor, zero on AP processors
 * - %o1 bootinfo structure address (BSP only)
 * - %o2 bootinfo structure size (BSP only)
 *
 * Moreover, we depend on boot having established the following environment:
 * - TLBs are on
 * - identity mapping for the kernel image
 */
.global kernel_image_start
kernel_image_start:
	mov BSP_FLAG, %l0
	and %o0, %l0, %l7			! l7 <= bootstrap processor?
	andn %o0, %l0, %l6			! l6 <= start of physical memory
	or %o1, %g0, %l1
	or %o2, %g0, %l2
 
	! Get bits (PHYSMEM_ADDR_SIZE - 1):13 of physmem_base.
	srlx %l6, 13, %l5
	
	! l5 <= physmem_base[(PHYSMEM_ADDR_SIZE - 1):13]
	sllx %l5, 13 + (63 - (PHYSMEM_ADDR_SIZE - 1)), %l5
	srlx %l5, 63 - (PHYSMEM_ADDR_SIZE - 1), %l5	
 
	/*
	 * Setup basic runtime environment.
	 */
	wrpr %g0, NWINDOWS - 2, %cansave	! set maximum saveable windows
	wrpr %g0, 0, %canrestore		! get rid of windows we will
						! never need again
	wrpr %g0, 0, %otherwin			! make sure the window state is
						! consistent
	wrpr %g0, NWINDOWS - 1, %cleanwin	! prevent needless clean_window
						! traps for kernel
						
	wrpr %g0, 0, %wstate			! use default spill/fill trap
 
	wrpr %g0, 0, %tl			! TL = 0, primary context
						! register is used
 
	wrpr %g0, PSTATE_PRIV_BIT, %pstate	! disable interrupts and disable
						! 32-bit address masking
 
	wrpr %g0, 0, %pil			! intialize %pil
 
	/*
	 * Switch to kernel trap table.
	 */
	sethi %hi(trap_table), %g1
	wrpr %g1, %lo(trap_table), %tba
 
 
	/*
	 * Take over the MMU.
	 */
 
	! map kernel in context 1
	set kernel_image_start, %o0				! virt. address
	set 1, %o1						! context
	TTE_DATA(kernel_image_start, %l5, %g2, %g3, %o2)	! TTE data
	set MMU_FLAG_DTLB | MMU_FLAG_ITLB, %o3			! MMU flags
	__HYPERCALL_HYPERFAST(MMU_MAP_ADDR)
 
	! switch to context 1
	set 1, %o0
	set VA_PRIMARY_CONTEXT_REG, %o1
	stxa %o0, [%o1] ASI_PRIMARY_CONTEXT_REG
 
	! demap all in context 0
	set 0, %o0						! reserved
	set 0, %o1						! reserved
	set 0, %o2						! context
	set MMU_FLAG_DTLB | MMU_FLAG_ITLB, %o3			! MMU flags
	__HYPERCALL_FAST(MMU_DEMAP_CTX)
 
	! install permanent mapping for kernel in context 0
	set kernel_image_start, %o0				! virtual address
	set 0, %o1						! context
	TTE_DATA(kernel_image_start, %l5, %g2, %g3, %o2)	! TTE data
	set MMU_FLAG_DTLB | MMU_FLAG_ITLB, %o3			! MMU flags
	__HYPERCALL_FAST(MMU_MAP_PERM_ADDR)
 
	! switch to context 0
	mov 0, %o0
	set VA_PRIMARY_CONTEXT_REG, %o1
	stxa %o0, [%o1] ASI_PRIMARY_CONTEXT_REG
 
	! demap all in context 1 (cleanup)
	set 0, %o0						! reserved
	set 0, %o1						! reserved
	set 1, %o2						! context
	set MMU_FLAG_DTLB | MMU_FLAG_ITLB, %o3			! MMU flags
	__HYPERCALL_FAST(MMU_DEMAP_CTX)
	
	/*
	 * Save physmem_base for use by the mm subsystem.
	 * %l6 contains starting physical address
	 */
	sethi %hi(physmem_base), %l4
	stx %l6, [%l4 + %lo(physmem_base)]
 
	/*
	 * Set CPUID.
	 */
	__HYPERCALL_FAST(CPU_MYID)
	mov SCRATCHPAD_CPUID, %g1
	stxa %o1, [%g1] ASI_SCRATCHPAD
 
	/*
	 * Set MMU fault status area for the current CPU.
	 */
	set mmu_fsas, %o0			! o0 <= addr. of fault status areas array
	add %o0, %l6, %o0			! kernel address to real address
	mulx %o1, MMU_FSA_SIZE, %g1		! g1 <= offset of current CPU's fault status area
	add %g1, %o0, %o0			! o0 <= FSA of the current CPU
	mov SCRATCHPAD_MMU_FSA, %g1
	stxa %o0, [%g1] ASI_SCRATCHPAD		! remember MMU fault status area to speed up miss handler
	__HYPERCALL_FAST(MMU_FAULT_AREA_CONF)
	
	/*
	 * Store a template of a TTE Data entry for kernel mappings.
	 * This template will be used from the kernel MMU miss handler.
	 */
	!TTE_DATA(0, %l5, %g2, %g3, %g1)
	setx TTE_FLAGS | PAGESIZE_8K, %g2, %g1; \
	add %g1, %l5, %g1; \
	set kernel_8k_tlb_data_template, %g4
	stx %g1, [%g4]
 
	/*
	 * So far, we have not touched the stack.
	 * It is a good idea to set the kernel stack to a known state now.
	 */
	sethi %hi(temporary_boot_stack), %sp
	or %sp, %lo(temporary_boot_stack), %sp
	sub %sp, STACK_BIAS, %sp
 
	or %l1, %g0, %o1
	or %l2, %g0, %o2
	sethi %hi(bootinfo), %o0
	call memcpy				! copy bootinfo
	or %o0, %lo(bootinfo), %o0
 
	call arch_pre_main
	nop
	
	call main_bsp
	nop
 
	/* Not reached. */
 
0:
	ba 0b
	nop
 
.section K_DATA_START, "aw", @progbits
 
#define INITIAL_STACK_SIZE		1024
 
.align STACK_ALIGNMENT
	.space INITIAL_STACK_SIZE
.align STACK_ALIGNMENT
temporary_boot_stack:
	.space STACK_WINDOW_SAVE_AREA_SIZE
 
 
.data
 
.align 8
.global physmem_base		! copy of the physical memory base address
physmem_base:
	.quad 0
 
.global kernel_8k_tlb_data_template
kernel_8k_tlb_data_template:
	.quad 0
 
/* MMU fault status areas for all CPUs */
.align MMU_FSA_ALIGNMENT
.global mmu_fsas
mmu_fsas:
	!.space (MMU_FSA_SIZE * MAX_NUM_STRANDS)
	.space 8192
 

Rev 3770	Rev 3835
1	#	1	#
2	# Copyright (c) 2005 Jakub Jermar	2	# Copyright (c) 2005 Jakub Jermar
3	# Copyright (c) 2008 Pavel Rimsky	3	# Copyright (c) 2008 Pavel Rimsky
4	# All rights reserved.	4	# All rights reserved.
5	#	5	#
6	# Redistribution and use in source and binary forms, with or without	6	# Redistribution and use in source and binary forms, with or without
7	# modification, are permitted provided that the following conditions	7	# modification, are permitted provided that the following conditions
8	# are met:	8	# are met:
9	#	9	#
10	# - Redistributions of source code must retain the above copyright	10	# - Redistributions of source code must retain the above copyright
11	# notice, this list of conditions and the following disclaimer.	11	# notice, this list of conditions and the following disclaimer.
12	# - Redistributions in binary form must reproduce the above copyright	12	# - Redistributions in binary form must reproduce the above copyright
13	# notice, this list of conditions and the following disclaimer in the	13	# notice, this list of conditions and the following disclaimer in the
14	# documentation and/or other materials provided with the distribution.	14	# documentation and/or other materials provided with the distribution.
15	# - The name of the author may not be used to endorse or promote products	15	# - The name of the author may not be used to endorse or promote products
16	# derived from this software without specific prior written permission.	16	# derived from this software without specific prior written permission.
17	#	17	#
18	# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	18	# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19	# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	19	# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20	# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	20	# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21	# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	21	# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22	# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	22	# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23	# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	23	# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24	# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	24	# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25	# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	25	# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26	# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	26	# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27	# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	27	# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28	#	28	#
29		29
30	#include <arch/arch.h>	30	#include <arch/arch.h>
31	#include <arch/stack.h>	31	#include <arch/stack.h>
32	#include <arch/sun4v/regdef.h>	32	#include <arch/sun4v/regdef.h>
33	#include <arch/sun4v/hypercall.h>	33	#include <arch/sun4v/hypercall.h>
-		34	#include <arch/sun4v/arch.h>
-		35	#include <arch/sun4v/cpu.h>
34	#include <arch/mm/pagesize.h>	36	#include <arch/mm/pagesize.h>
35	#include <arch/mm/sun4v/tte.h>	37	#include <arch/mm/sun4v/tte.h>
36	#include <arch/mm/sun4v/mmu.h>	38	#include <arch/mm/sun4v/mmu.h>
37	#include <arch/mm/sun4v/tlb.h>	39	#include <arch/mm/sun4v/tlb.h>
38		40
39	.register %g2, #scratch	41	.register %g2, #scratch
40	.register %g3, #scratch	42	.register %g3, #scratch
41		43
42	.section K_TEXT_START, "ax"	44	.section K_TEXT_START, "ax"
43		45
44	#define BSP_FLAG 1	46	#define BSP_FLAG 1
45	#define PHYSMEM_ADDR_SIZE 56	47	#define PHYSMEM_ADDR_SIZE 56
46		48
47	/*	49	/*
48	* Flags set in the TTE data entry mapping the kernel.	50	* Flags set in the TTE data entry mapping the kernel.
49	*/	51	*/
50	#ifdef CONFIG_VIRT_IDX_DCACHE	52	#ifdef CONFIG_VIRT_IDX_DCACHE
51	#define TTE_FLAGS \	53	#define TTE_FLAGS \
52	(1 << TTE_V_SHIFT) \	54	(1 << TTE_V_SHIFT) \
53	\| (1 << TTE_EP_SHIFT) \	55	\| (1 << TTE_EP_SHIFT) \
54	\| (1 << TTE_CP_SHIFT) \	56	\| (1 << TTE_CP_SHIFT) \
55	\| (1 << TTE_CV_SHIFT) \	57	\| (1 << TTE_CV_SHIFT) \
56	\| (1 << TTE_P_SHIFT) \	58	\| (1 << TTE_P_SHIFT) \
57	\| (1 << TTE_W_SHIFT)	59	\| (1 << TTE_W_SHIFT)
58	#else	60	#else
59	#define TTE_FLAGS \	61	#define TTE_FLAGS \
60	(1 << TTE_V_SHIFT) \	62	(1 << TTE_V_SHIFT) \
61	\| (1 << TTE_EP_SHIFT) \	63	\| (1 << TTE_EP_SHIFT) \
62	\| (1 << TTE_CP_SHIFT) \	64	\| (1 << TTE_CP_SHIFT) \
63	\| (1 << TTE_P_SHIFT) \	65	\| (1 << TTE_P_SHIFT) \
64	\| (1 << TTE_W_SHIFT)	66	\| (1 << TTE_W_SHIFT)
65	#endif	67	#endif
66		68
67		69
68	/*	70	/*
69	* Fills a register with a TTE Data item. The item will map the given virtual	71	* Fills a register with a TTE Data item. The item will map the given virtual
70	* address to a real address which will be computed by adding the starting	72	* address to a real address which will be computed by adding the starting
71	* address of the physical memory to the virtual address.	73	* address of the physical memory to the virtual address.
72	*	74	*
73	* parameters:	75	* parameters:
74	* addr: virtual address to be mapped	76	* addr: virtual address to be mapped
75	* rphysmem_start: register containing the starting address of the	77	* rphysmem_start: register containing the starting address of the
76	* physical memory	78	* physical memory
77	* rtmp1: a register to be used as temporary	79	* rtmp1: a register to be used as temporary
78	* rtmp2: a register to be used as temporary	80	* rtmp2: a register to be used as temporary
79	* rd: register where the result will be saved	81	* rd: register where the result will be saved
80	*/	82	*/
81	#define TTE_DATA(addr, rphysmem_start, rtmp1, rtmp2, rd) \	83	#define TTE_DATA(addr, rphysmem_start, rtmp1, rtmp2, rd) \
82	setx TTE_FLAGS \| PAGESIZE_4M, rtmp1, rd; \	84	setx TTE_FLAGS \| PAGESIZE_4M, rtmp1, rd; \
83	add rd, rphysmem_start, rd; \	85	add rd, rphysmem_start, rd; \
84	setx (addr), rtmp1, rtmp2; \	86	setx (addr), rtmp1, rtmp2; \
85	add rd, rtmp2, rd;	87	add rd, rtmp2, rd;
86		88
87	/*	89	/*
88	* Here is where the kernel is passed control from the boot loader.	90	* Here is where the kernel is passed control from the boot loader.
89	*	91	*
90	* The registers are expected to be in this state:	92	* The registers are expected to be in this state:
91	* - %o0 starting address of physical memory + bootstrap processor flag	93	* - %o0 starting address of physical memory + bootstrap processor flag
92	* bits 63...1: physical memory starting address / 2	94	* bits 63...1: physical memory starting address / 2
93	* bit 0: non-zero on BSP processor, zero on AP processors	95	* bit 0: non-zero on BSP processor, zero on AP processors
94	* - %o1 bootinfo structure address (BSP only)	96	* - %o1 bootinfo structure address (BSP only)
95	* - %o2 bootinfo structure size (BSP only)	97	* - %o2 bootinfo structure size (BSP only)
96	*	98	*
97	* Moreover, we depend on boot having established the following environment:	99	* Moreover, we depend on boot having established the following environment:
98	* - TLBs are on	100	* - TLBs are on
99	* - identity mapping for the kernel image	101	* - identity mapping for the kernel image
100	*/	102	*/
101	.global kernel_image_start	103	.global kernel_image_start
102	kernel_image_start:	104	kernel_image_start:
103	mov BSP_FLAG, %l0	105	mov BSP_FLAG, %l0
104	and %o0, %l0, %l7 ! l7 <= bootstrap processor?	106	and %o0, %l0, %l7 ! l7 <= bootstrap processor?
105	andn %o0, %l0, %l6 ! l6 <= start of physical memory	107	andn %o0, %l0, %l6 ! l6 <= start of physical memory
106	or %o1, %g0, %l1	108	or %o1, %g0, %l1
107	or %o2, %g0, %l2	109	or %o2, %g0, %l2
108		110
109	! Get bits (PHYSMEM_ADDR_SIZE - 1):13 of physmem_base.	111	! Get bits (PHYSMEM_ADDR_SIZE - 1):13 of physmem_base.
110	srlx %l6, 13, %l5	112	srlx %l6, 13, %l5
111		113
112	! l5 <= physmem_base[(PHYSMEM_ADDR_SIZE - 1):13]	114	! l5 <= physmem_base[(PHYSMEM_ADDR_SIZE - 1):13]
113	sllx %l5, 13 + (63 - (PHYSMEM_ADDR_SIZE - 1)), %l5	115	sllx %l5, 13 + (63 - (PHYSMEM_ADDR_SIZE - 1)), %l5
114	srlx %l5, 63 - (PHYSMEM_ADDR_SIZE - 1), %l5	116	srlx %l5, 63 - (PHYSMEM_ADDR_SIZE - 1), %l5
115		117
116	/*	118	/*
117	* Setup basic runtime environment.	119	* Setup basic runtime environment.
118	*/	120	*/
119	wrpr %g0, NWINDOWS - 2, %cansave ! set maximum saveable windows	121	wrpr %g0, NWINDOWS - 2, %cansave ! set maximum saveable windows
120	wrpr %g0, 0, %canrestore ! get rid of windows we will	122	wrpr %g0, 0, %canrestore ! get rid of windows we will
121	! never need again	123	! never need again
122	wrpr %g0, 0, %otherwin ! make sure the window state is	124	wrpr %g0, 0, %otherwin ! make sure the window state is
123	! consistent	125	! consistent
124	wrpr %g0, NWINDOWS - 1, %cleanwin ! prevent needless clean_window	126	wrpr %g0, NWINDOWS - 1, %cleanwin ! prevent needless clean_window
125	! traps for kernel	127	! traps for kernel
126		128
127	wrpr %g0, 0, %wstate ! use default spill/fill trap	129	wrpr %g0, 0, %wstate ! use default spill/fill trap
128		130
129	wrpr %g0, 0, %tl ! TL = 0, primary context	131	wrpr %g0, 0, %tl ! TL = 0, primary context
130	! register is used	132	! register is used
131		133
132	wrpr %g0, PSTATE_PRIV_BIT, %pstate ! disable interrupts and disable	134	wrpr %g0, PSTATE_PRIV_BIT, %pstate ! disable interrupts and disable
133	! 32-bit address masking	135	! 32-bit address masking
134		136
135	wrpr %g0, 0, %pil ! intialize %pil	137	wrpr %g0, 0, %pil ! intialize %pil
136		138
137	/*	139	/*
138	* Switch to kernel trap table.	140	* Switch to kernel trap table.
139	*/	141	*/
140	sethi %hi(trap_table), %g1	142	sethi %hi(trap_table), %g1
141	wrpr %g1, %lo(trap_table), %tba	143	wrpr %g1, %lo(trap_table), %tba
142		144
143		145
144	/*	146	/*
145	* Take over the MMU.	147	* Take over the MMU.
146	*/	148	*/
147		149
148	! map kernel in context 1	150	! map kernel in context 1
149	set kernel_image_start, %o0 ! virt. address	151	set kernel_image_start, %o0 ! virt. address
150	set 1, %o1 ! context	152	set 1, %o1 ! context
151	TTE_DATA(kernel_image_start, %l5, %g2, %g3, %o2) ! TTE data	153	TTE_DATA(kernel_image_start, %l5, %g2, %g3, %o2) ! TTE data
152	set MMU_FLAG_DTLB \| MMU_FLAG_ITLB, %o3 ! MMU flags	154	set MMU_FLAG_DTLB \| MMU_FLAG_ITLB, %o3 ! MMU flags
153	__HYPERCALL_HYPERFAST(MMU_MAP_ADDR)	155	__HYPERCALL_HYPERFAST(MMU_MAP_ADDR)
154		156
155	! switch to context 1	157	! switch to context 1
156	set 1, %o0	158	set 1, %o0
157	set VA_PRIMARY_CONTEXT_REG, %o1	159	set VA_PRIMARY_CONTEXT_REG, %o1
158	stxa %o0, [%o1] ASI_PRIMARY_CONTEXT_REG	160	stxa %o0, [%o1] ASI_PRIMARY_CONTEXT_REG
159		161
160	! demap all in context 0	162	! demap all in context 0
161	set 0, %o0 ! reserved	163	set 0, %o0 ! reserved
162	set 0, %o1 ! reserved	164	set 0, %o1 ! reserved
163	set 0, %o2 ! context	165	set 0, %o2 ! context
164	set MMU_FLAG_DTLB \| MMU_FLAG_ITLB, %o3 ! MMU flags	166	set MMU_FLAG_DTLB \| MMU_FLAG_ITLB, %o3 ! MMU flags
165	__HYPERCALL_FAST(MMU_DEMAP_CTX)	167	__HYPERCALL_FAST(MMU_DEMAP_CTX)
166		168
167	! install permanent mapping for kernel in context 0	169	! install permanent mapping for kernel in context 0
168	set kernel_image_start, %o0 ! virtual address	170	set kernel_image_start, %o0 ! virtual address
169	set 0, %o1 ! context	171	set 0, %o1 ! context
170	TTE_DATA(kernel_image_start, %l5, %g2, %g3, %o2) ! TTE data	172	TTE_DATA(kernel_image_start, %l5, %g2, %g3, %o2) ! TTE data
171	set MMU_FLAG_DTLB \| MMU_FLAG_ITLB, %o3 ! MMU flags	173	set MMU_FLAG_DTLB \| MMU_FLAG_ITLB, %o3 ! MMU flags
172	__HYPERCALL_FAST(MMU_MAP_PERM_ADDR)	174	__HYPERCALL_FAST(MMU_MAP_PERM_ADDR)
173		175
174	! switch to context 0	176	! switch to context 0
175	mov 0, %o0	177	mov 0, %o0
176	set VA_PRIMARY_CONTEXT_REG, %o1	178	set VA_PRIMARY_CONTEXT_REG, %o1
177	stxa %o0, [%o1] ASI_PRIMARY_CONTEXT_REG	179	stxa %o0, [%o1] ASI_PRIMARY_CONTEXT_REG
178		180
179	! demap all in context 1 (cleanup)	181	! demap all in context 1 (cleanup)
180	set 0, %o0 ! reserved	182	set 0, %o0 ! reserved
181	set 0, %o1 ! reserved	183	set 0, %o1 ! reserved
182	set 1, %o2 ! context	184	set 1, %o2 ! context
183	set MMU_FLAG_DTLB \| MMU_FLAG_ITLB, %o3 ! MMU flags	185	set MMU_FLAG_DTLB \| MMU_FLAG_ITLB, %o3 ! MMU flags
184	__HYPERCALL_FAST(MMU_DEMAP_CTX)	186	__HYPERCALL_FAST(MMU_DEMAP_CTX)
185		187
186	/*	188	/*
187	* Save physmem_base for use by the mm subsystem.	189	* Save physmem_base for use by the mm subsystem.
188	* %l6 contains starting physical address	190	* %l6 contains starting physical address
189	*/	191	*/
190	sethi %hi(physmem_base), %l4	192	sethi %hi(physmem_base), %l4
191	stx %l6, [%l4 + %lo(physmem_base)]	193	stx %l6, [%l4 + %lo(physmem_base)]
192		194
193	/*	195	/*
-		196	* Set CPUID.
-		197	*/
-		198	__HYPERCALL_FAST(CPU_MYID)
-		199	mov SCRATCHPAD_CPUID, %g1
-		200	stxa %o1, [%g1] ASI_SCRATCHPAD
-		201
-		202	/*
-		203	* Set MMU fault status area for the current CPU.
-		204	*/
-		205	set mmu_fsas, %o0 ! o0 <= addr. of fault status areas array
-		206	add %o0, %l6, %o0 ! kernel address to real address
-		207	mulx %o1, MMU_FSA_SIZE, %g1 ! g1 <= offset of current CPU's fault status area
-		208	add %g1, %o0, %o0 ! o0 <= FSA of the current CPU
-		209	mov SCRATCHPAD_MMU_FSA, %g1
-		210	stxa %o0, [%g1] ASI_SCRATCHPAD ! remember MMU fault status area to speed up miss handler
-		211	__HYPERCALL_FAST(MMU_FAULT_AREA_CONF)
-		212
-		213	/*
-		214	* Store a template of a TTE Data entry for kernel mappings.
-		215	* This template will be used from the kernel MMU miss handler.
-		216	*/
-		217	!TTE_DATA(0, %l5, %g2, %g3, %g1)
-		218	setx TTE_FLAGS \| PAGESIZE_8K, %g2, %g1; \
-		219	add %g1, %l5, %g1; \
-		220	set kernel_8k_tlb_data_template, %g4
-		221	stx %g1, [%g4]
-		222
-		223	/*
194	* So far, we have not touched the stack.	224	* So far, we have not touched the stack.
195	* It is a good idea to set the kernel stack to a known state now.	225	* It is a good idea to set the kernel stack to a known state now.
196	*/	226	*/
197	sethi %hi(temporary_boot_stack), %sp	227	sethi %hi(temporary_boot_stack), %sp
198	or %sp, %lo(temporary_boot_stack), %sp	228	or %sp, %lo(temporary_boot_stack), %sp
199	sub %sp, STACK_BIAS, %sp	229	sub %sp, STACK_BIAS, %sp
200		230
201	or %l1, %g0, %o1	231	or %l1, %g0, %o1
202	or %l2, %g0, %o2	232	or %l2, %g0, %o2
203	sethi %hi(bootinfo), %o0	233	sethi %hi(bootinfo), %o0
204	call memcpy ! copy bootinfo	234	call memcpy ! copy bootinfo
205	or %o0, %lo(bootinfo), %o0	235	or %o0, %lo(bootinfo), %o0
206		236
207	call arch_pre_main	237	call arch_pre_main
208	nop	238	nop
209		239
210	call main_bsp	240	call main_bsp
211	nop	241	nop
212		242
213	/* Not reached. */	243	/* Not reached. */
214		244
215	0:	245	0:
216	ba 0b	246	ba 0b
217	nop	247	nop
218		248
219	.section K_DATA_START, "aw", @progbits	249	.section K_DATA_START, "aw", @progbits
220		250
221	#define INITIAL_STACK_SIZE 1024	251	#define INITIAL_STACK_SIZE 1024
222		252
223	.align STACK_ALIGNMENT	253	.align STACK_ALIGNMENT
224	.space INITIAL_STACK_SIZE	254	.space INITIAL_STACK_SIZE
225	.align STACK_ALIGNMENT	255	.align STACK_ALIGNMENT
226	temporary_boot_stack:	256	temporary_boot_stack:
227	.space STACK_WINDOW_SAVE_AREA_SIZE	257	.space STACK_WINDOW_SAVE_AREA_SIZE
228		258
229		259
230	.data	260	.data
231		261
232	.align 8	262	.align 8
233	.global physmem_base ! copy of the physical memory base address	263	.global physmem_base ! copy of the physical memory base address
234	physmem_base:	264	physmem_base:
235	.quad 0	265	.quad 0
-		266
-		267	.global kernel_8k_tlb_data_template
-		268	kernel_8k_tlb_data_template:
-		269	.quad 0
-		270
-		271	/* MMU fault status areas for all CPUs */
-		272	.align MMU_FSA_ALIGNMENT
-		273	.global mmu_fsas
-		274	mmu_fsas:
-		275	!.space (MMU_FSA_SIZE * MAX_NUM_STRANDS)
-		276	.space 8192
236		277

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(root)/branches/sparc/kernel/arch/sparc64/src/sun4v/start.S – Rev 3770 → 3835