WebSVN – HelenOS – Diff – /branches/sparc/kernel/arch/sparc64/src/mm/tlb.c

 #ifdef CONFIG_TSB
 #include <arch/mm/tsb.h>
 #endif
-static void dtlb_pte_copy(pte_t *t, index_t index, bool ro);
+static void dtlb_pte_copy(pte_t *, index_t, bool);
-static void itlb_pte_copy(pte_t *t, index_t index);
+static void itlb_pte_copy(pte_t *, index_t);
-static void do_fast_instruction_access_mmu_miss_fault(istate_t *istate,
+static void do_fast_instruction_access_mmu_miss_fault(istate_t *, const char *);
-    const char *str);
-static void do_fast_data_access_mmu_miss_fault(istate_t *istate,
+static void do_fast_data_access_mmu_miss_fault(istate_t *, tlb_tag_access_reg_t,
-    tlb_tag_access_reg_t tag, const char *str);
+    const char *);
-static void do_fast_data_access_protection_fault(istate_t *istate,
+static void do_fast_data_access_protection_fault(istate_t *,
-    tlb_tag_access_reg_t tag, const char *str);
+    tlb_tag_access_reg_t, const char *);
 char *context_encoding[] = {
     "Primary",
     "Secondary",
     "Nucleus",
     itlb_sfsr_write(0);
+}
 /** Insert privileged mapping into DMMU TLB.
+ *
- * @param page Virtual page address.
+ * @param page      Virtual page address.
- * @param frame Physical frame address.
+ * @param frame     Physical frame address.
- * @param pagesize Page size.
+ * @param pagesize  Page size.
- * @param locked True for permanent mappings, false otherwise.
+ * @param locked    True for permanent mappings, false otherwise.
  * @param cacheable True if the mapping is cacheable, false otherwise.
  */
 void dtlb_insert_mapping(uintptr_t page, uintptr_t frame, int pagesize,
     bool locked, bool cacheable)
+{
     tlb_tag_access_reg_t tag;
     dtlb_data_in_write(data.value);
+}
 /** Copy PTE to TLB.
+ *
- * @param t     Page Table Entry to be copied.
+ * @param t         Page Table Entry to be copied.
- * @param index Zero if lower 8K-subpage, one if higher 8K-subpage.
+ * @param index     Zero if lower 8K-subpage, one if higher 8K-subpage.
- * @param ro    If true, the entry will be created read-only, regardless of its
+ * @param ro        If true, the entry will be created read-only, regardless
- *      w field.
+ *          of its w field.
  */
 void dtlb_pte_copy(pte_t *t, index_t index, bool ro)
+{
     tlb_tag_access_reg_t tag;
     tlb_data_t data;
     dtlb_data_in_write(data.value);
+}
 /** Copy PTE to ITLB.
+ *
  * @param t     Page Table Entry to be copied.
- * @param index Zero if lower 8K-subpage, one if higher 8K-subpage.
+ * @param index     Zero if lower 8K-subpage, one if higher 8K-subpage.
  */
 void itlb_pte_copy(pte_t *t, index_t index)
+{
     tlb_tag_access_reg_t tag;
     tlb_data_t data;
 /** DTLB miss handler.
+ *
  * Note that some faults (e.g. kernel faults) were already resolved by the
  * low-level, assembly language part of the fast_data_access_mmu_miss handler.
+ *
- * @param tag Content of the TLB Tag Access register as it existed when the
+ * @param tag       Content of the TLB Tag Access register as it existed
- *    trap happened. This is to prevent confusion created by clobbered
+ *          when the trap happened. This is to prevent confusion
- *    Tag Access register during a nested DTLB miss.
+ *          created by clobbered Tag Access register during a nested
+ *          DTLB miss.
- * @param istate Interrupted state saved on the stack.
+ * @param istate    Interrupted state saved on the stack.
  */
 void fast_data_access_mmu_miss(tlb_tag_access_reg_t tag, istate_t *istate)
+{
     uintptr_t va;
     index_t index;
+    }
+}
 /** DTLB protection fault handler.
+ *
- * @param tag Content of the TLB Tag Access register as it existed when the
+ * @param tag       Content of the TLB Tag Access register as it existed
- *    trap happened. This is to prevent confusion created by clobbered
+ *          when the trap happened. This is to prevent confusion
- *    Tag Access register during a nested DTLB miss.
+ *          created by clobbered Tag Access register during a nested
+ *          DTLB miss.
- * @param istate Interrupted state saved on the stack.
+ * @param istate    Interrupted state saved on the stack.
  */
 void fast_data_access_protection(tlb_tag_access_reg_t tag, istate_t *istate)
+{
     uintptr_t va;
     index_t index;
 /** Print TLB entry (for debugging purposes).
+ *
  * The diag field has been left out in order to make this function more generic
  * (there is no diag field in US3 architeture).
+ *
- * @param i TLB entry number
+ * @param i     TLB entry number
- * @param t TLB entry tag
+ * @param t     TLB entry tag
- * @param d TLB entry data
+ * @param d     TLB entry data
  */
 static void print_tlb_entry(int i, tlb_tag_read_reg_t t, tlb_data_t d)
+{
     printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, "
         "ie=%d, soft2=%#x, pfn=%#x, soft=%#x, l=%d, "
     printf("DTLB SFSR: asi=%#x, ft=%#x, e=%d, ct=%d, pr=%d, w=%d, ow=%d, "
         "fv=%d\n", sfsr.asi, sfsr.ft, sfsr.e, sfsr.ct, sfsr.pr, sfsr.w,
         sfsr.ow, sfsr.fv);
 #elif defined (US3)
     printf("DTLB SFSR: nf=%d, asi=%#x, tm=%d, ft=%#x, e=%d, ct=%d, pr=%d, "
-           "w=%d, ow=%d, fv=%d\n", sfsr.nf, sfsr.asi, sfsr.tm, sfsr.ft,
+        "w=%d, ow=%d, fv=%d\n", sfsr.nf, sfsr.asi, sfsr.tm, sfsr.ft,
         sfsr.e, sfsr.ct, sfsr.pr, sfsr.w, sfsr.ow, sfsr.fv);
 #endif
     printf("DTLB SFAR: address=%p\n", sfar);
     dtlb_sfsr_write(0);
+}
 #if defined (US3)
 /** Invalidates given TLB entry if and only if it is non-locked or global.
+ *
- * @param tlb
- *  TLB number (one of TLB_DSMALL, TLB_DBIG_0, TLB_DBIG_1,
+ * @param tlb       TLB number (one of TLB_DSMALL, TLB_DBIG_0, TLB_DBIG_1,
- *  TLB_ISMALL, TLB_IBIG)
+ *          TLB_ISMALL, TLB_IBIG).
- * @param entry entry index within the given TLB
+ * @param entry     Entry index within the given TLB.
  */
 static void tlb_invalidate_entry(int tlb, index_t entry)
+{
     tlb_data_t d;
     tlb_tag_read_reg_t t;
+}
 /** Invalidate all ITLB and DTLB entries for specified page range in specified
  * address space.
+ *
- * @param asid Address Space ID.
+ * @param asid      Address Space ID.
- * @param page First page which to sweep out from ITLB and DTLB.
+ * @param page      First page which to sweep out from ITLB and DTLB.
- * @param cnt Number of ITLB and DTLB entries to invalidate.
+ * @param cnt       Number of ITLB and DTLB entries to invalidate.
  */
 void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt)
+{
     unsigned int i;
     tlb_context_reg_t pc_save, ctx;

Subversion Repositories HelenOS

(root)/branches/sparc/kernel/arch/sparc64/src/mm/tlb.c – Rev 3618 → 3742