WebSVN – HelenOS – Diff – /branches/sparc/kernel/arch/sparc64/src/mm/sun4v/tlb.c


/*
 * Copyright (c) 2005 Jakub Jermar
 * Copyright (c) 2008 Pavel Rimsky
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup sparc64mm  
 * @{
 */
/** @file
 */
 
#include <mm/tlb.h>
#include <mm/as.h>
#include <mm/asid.h>
#include <arch/sun4v/hypercall.h>
#include <arch/mm/frame.h>
#include <arch/mm/page.h>
#include <arch/mm/tte.h>
#include <arch/mm/tlb.h>
#include <arch/interrupt.h>
#include <interrupt.h>
#include <arch.h>
#include <print.h>
#include <arch/types.h>
#include <config.h>
#include <arch/trap/trap.h>
#include <arch/trap/exception.h>
#include <panic.h>
#include <arch/asm.h>
#include <arch/cpu.h>
 
#ifdef CONFIG_TSB
#include <arch/mm/tsb.h>
#endif
 
#if 0
static void dtlb_pte_copy(pte_t *, index_t, bool);
static void itlb_pte_copy(pte_t *, index_t);
static void do_fast_instruction_access_mmu_miss_fault(istate_t *, const char *);
static void do_fast_data_access_mmu_miss_fault(istate_t *, tlb_tag_access_reg_t,
    const char *);
static void do_fast_data_access_protection_fault(istate_t *,
    tlb_tag_access_reg_t, const char *);
 
char *context_encoding[] = {
    "Primary",
    "Secondary",
    "Nucleus",
    "Reserved"
};
#endif
 
/*
 * Invalidate all non-locked DTLB and ITLB entries.
 */
void tlb_arch_init(void)
{
    tlb_invalidate_all();
}
 
/** Insert privileged mapping into DMMU TLB.
 *
 * @param page      Virtual page address.
 * @param frame     Physical frame address.
 * @param pagesize  Page size.
 * @param locked    True for permanent mappings, false otherwise.
 * @param cacheable True if the mapping is cacheable, false otherwise.
 */
void dtlb_insert_mapping(uintptr_t page, uintptr_t frame, int pagesize,
    bool locked, bool cacheable)
{
#if 0
    tlb_tag_access_reg_t tag;
    tlb_data_t data;
    page_address_t pg;
    frame_address_t fr;
 
    pg.address = page;
    fr.address = frame;
 
    tag.context = ASID_KERNEL;
    tag.vpn = pg.vpn;
 
    dtlb_tag_access_write(tag.value);
 
    data.value = 0;
    data.v = true;
    data.size = pagesize;
    data.pfn = fr.pfn;
    data.l = locked;
    data.cp = cacheable;
#ifdef CONFIG_VIRT_IDX_DCACHE
    data.cv = cacheable;
#endif /* CONFIG_VIRT_IDX_DCACHE */
    data.p = true;
    data.w = true;
    data.g = false;
 
    dtlb_data_in_write(data.value);
#endif
}
 
/** Copy PTE to TLB.
 *
 * @param t         Page Table Entry to be copied.
 * @param index     Zero if lower 8K-subpage, one if higher 8K-subpage.
 * @param ro        If true, the entry will be created read-only, regardless
 *          of its w field.
 */
#if 0
void dtlb_pte_copy(pte_t *t, index_t index, bool ro)
{
    tlb_tag_access_reg_t tag;
    tlb_data_t data;
    page_address_t pg;
    frame_address_t fr;
 
    pg.address = t->page + (index << MMU_PAGE_WIDTH);
    fr.address = t->frame + (index << MMU_PAGE_WIDTH);
 
    tag.value = 0;
    tag.context = t->as->asid;
    tag.vpn = pg.vpn;
 
    dtlb_tag_access_write(tag.value);
 
    data.value = 0;
    data.v = true;
    data.size = PAGESIZE_8K;
    data.pfn = fr.pfn;
    data.l = false;
    data.cp = t->c;
#ifdef CONFIG_VIRT_IDX_DCACHE
    data.cv = t->c;
#endif /* CONFIG_VIRT_IDX_DCACHE */
    data.p = t->k;      /* p like privileged */
    data.w = ro ? false : t->w;
    data.g = t->g;
 
    dtlb_data_in_write(data.value);
}
#endif
 
/** Copy PTE to ITLB.
 *
 * @param t     Page Table Entry to be copied.
 * @param index     Zero if lower 8K-subpage, one if higher 8K-subpage.
 */
#if 0
void itlb_pte_copy(pte_t *t, index_t index)
{
    tlb_tag_access_reg_t tag;
    tlb_data_t data;
    page_address_t pg;
    frame_address_t fr;
 
    pg.address = t->page + (index << MMU_PAGE_WIDTH);
    fr.address = t->frame + (index << MMU_PAGE_WIDTH);
 
    tag.value = 0;
    tag.context = t->as->asid;
    tag.vpn = pg.vpn;
   
    itlb_tag_access_write(tag.value);
   
    data.value = 0;
    data.v = true;
    data.size = PAGESIZE_8K;
    data.pfn = fr.pfn;
    data.l = false;
    data.cp = t->c;
    data.p = t->k;      /* p like privileged */
    data.w = false;
    data.g = t->g;
   
    itlb_data_in_write(data.value);
}
#endif
 
/** ITLB miss handler. */
void fast_instruction_access_mmu_miss(unative_t unused, istate_t *istate)
{
#if 0
    uintptr_t va = ALIGN_DOWN(istate->tpc, PAGE_SIZE);
    index_t index = (istate->tpc >> MMU_PAGE_WIDTH) % MMU_PAGES_PER_PAGE;
    pte_t *t;
 
    page_table_lock(AS, true);
    t = page_mapping_find(AS, va);
    if (t && PTE_EXECUTABLE(t)) {
        /*
         * The mapping was found in the software page hash table.
         * Insert it into ITLB.
         */
        t->a = true;
        itlb_pte_copy(t, index);
#ifdef CONFIG_TSB
        itsb_pte_copy(t, index);
#endif
        page_table_unlock(AS, true);
    } else {
        /*
         * Forward the page fault to the address space page fault
         * handler.
         */    
        page_table_unlock(AS, true);
        if (as_page_fault(va, PF_ACCESS_EXEC, istate) == AS_PF_FAULT) {
            do_fast_instruction_access_mmu_miss_fault(istate,
                __func__);
        }
    }
#endif
}
 
/** DTLB miss handler.
 *
 * Note that some faults (e.g. kernel faults) were already resolved by the
 * low-level, assembly language part of the fast_data_access_mmu_miss handler.
 *
 * @param tag       Content of the TLB Tag Access register as it existed
 *          when the trap happened. This is to prevent confusion
 *          created by clobbered Tag Access register during a nested
 *          DTLB miss.
 * @param istate    Interrupted state saved on the stack.
 */
//void fast_data_access_mmu_miss(tlb_tag_access_reg_t tag, istate_t *istate)
//{
#if 0
    uintptr_t va;
    index_t index;
    pte_t *t;
 
    va = ALIGN_DOWN((uint64_t) tag.vpn << MMU_PAGE_WIDTH, PAGE_SIZE);
    index = tag.vpn % MMU_PAGES_PER_PAGE;
 
    if (tag.context == ASID_KERNEL) {
        if (!tag.vpn) {
            /* NULL access in kernel */
            do_fast_data_access_mmu_miss_fault(istate, tag,
                __func__);
        }
        do_fast_data_access_mmu_miss_fault(istate, tag, "Unexpected "
            "kernel page fault.");
    }
 
    page_table_lock(AS, true);
    t = page_mapping_find(AS, va);
    if (t) {
        /*
         * The mapping was found in the software page hash table.
         * Insert it into DTLB.
         */
        t->a = true;
        dtlb_pte_copy(t, index, true);
#ifdef CONFIG_TSB
        dtsb_pte_copy(t, index, true);
#endif
        page_table_unlock(AS, true);
    } else {
        /*
         * Forward the page fault to the address space page fault
         * handler.
         */    
        page_table_unlock(AS, true);
        if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) {
            do_fast_data_access_mmu_miss_fault(istate, tag,
                __func__);
        }
    }
#endif
//}
 
/** DTLB protection fault handler.
 *
 * @param tag       Content of the TLB Tag Access register as it existed
 *          when the trap happened. This is to prevent confusion
 *          created by clobbered Tag Access register during a nested
 *          DTLB miss.
 * @param istate    Interrupted state saved on the stack.
 */
//void fast_data_access_protection(tlb_tag_access_reg_t tag, istate_t *istate)
//{
#if 0
    uintptr_t va;
    index_t index;
    pte_t *t;
 
    va = ALIGN_DOWN((uint64_t) tag.vpn << MMU_PAGE_WIDTH, PAGE_SIZE);
    index = tag.vpn % MMU_PAGES_PER_PAGE;   /* 16K-page emulation */
 
    page_table_lock(AS, true);
    t = page_mapping_find(AS, va);
    if (t && PTE_WRITABLE(t)) {
        /*
         * The mapping was found in the software page hash table and is
         * writable. Demap the old mapping and insert an updated mapping
         * into DTLB.
         */
        t->a = true;
        t->d = true;
        dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_SECONDARY,
            va + index * MMU_PAGE_SIZE);
        dtlb_pte_copy(t, index, false);
#ifdef CONFIG_TSB
        dtsb_pte_copy(t, index, false);
#endif
        page_table_unlock(AS, true);
    } else {
        /*
         * Forward the page fault to the address space page fault
         * handler.
         */    
        page_table_unlock(AS, true);
        if (as_page_fault(va, PF_ACCESS_WRITE, istate) == AS_PF_FAULT) {
            do_fast_data_access_protection_fault(istate, tag,
                __func__);
        }
    }
#endif
//}
 
/** Print TLB entry (for debugging purposes).
 *
 * The diag field has been left out in order to make this function more generic
 * (there is no diag field in US3 architeture).
 *
 * @param i     TLB entry number
 * @param t     TLB entry tag
 * @param d     TLB entry data
 */
#if 0
static void print_tlb_entry(int i, tlb_tag_read_reg_t t, tlb_data_t d)
{
    printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, "
        "ie=%d, soft2=%#x, pfn=%#x, soft=%#x, l=%d, "
        "cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n", i, t.vpn,
        t.context, d.v, d.size, d.nfo, d.ie, d.soft2,
        d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);
}
#endif
 
#if defined (US)
 
/** Print contents of both TLBs. */
void tlb_print(void)
#if 0
{
    int i;
    tlb_data_t d;
    tlb_tag_read_reg_t t;
   
    printf("I-TLB contents:\n");
    for (i = 0; i < ITLB_ENTRY_COUNT; i++) {
        d.value = itlb_data_access_read(i);
        t.value = itlb_tag_read_read(i);
        print_tlb_entry(i, t, d);
    }
 
    printf("D-TLB contents:\n");
    for (i = 0; i < DTLB_ENTRY_COUNT; i++) {
        d.value = dtlb_data_access_read(i);
        t.value = dtlb_tag_read_read(i);
        print_tlb_entry(i, t, d);
    }
#endif
}
 
#elif defined (US3)
 
/** Print contents of all TLBs. */
void tlb_print(void)
{
#if 0
    int i;
    tlb_data_t d;
    tlb_tag_read_reg_t t;
   
    printf("TLB_ISMALL contents:\n");
    for (i = 0; i < tlb_ismall_size(); i++) {
        d.value = dtlb_data_access_read(TLB_ISMALL, i);
        t.value = dtlb_tag_read_read(TLB_ISMALL, i);
        print_tlb_entry(i, t, d);
    }
   
    printf("TLB_IBIG contents:\n");
    for (i = 0; i < tlb_ibig_size(); i++) {
        d.value = dtlb_data_access_read(TLB_IBIG, i);
        t.value = dtlb_tag_read_read(TLB_IBIG, i);
        print_tlb_entry(i, t, d);
    }
   
    printf("TLB_DSMALL contents:\n");
    for (i = 0; i < tlb_dsmall_size(); i++) {
        d.value = dtlb_data_access_read(TLB_DSMALL, i);
        t.value = dtlb_tag_read_read(TLB_DSMALL, i);
        print_tlb_entry(i, t, d);
    }
   
    printf("TLB_DBIG_1 contents:\n");
    for (i = 0; i < tlb_dbig_size(); i++) {
        d.value = dtlb_data_access_read(TLB_DBIG_0, i);
        t.value = dtlb_tag_read_read(TLB_DBIG_0, i);
        print_tlb_entry(i, t, d);
    }
   
    printf("TLB_DBIG_2 contents:\n");
    for (i = 0; i < tlb_dbig_size(); i++) {
        d.value = dtlb_data_access_read(TLB_DBIG_1, i);
        t.value = dtlb_tag_read_read(TLB_DBIG_1, i);
        print_tlb_entry(i, t, d);
    }
#endif
}
 
#endif
 
#if 0
void do_fast_instruction_access_mmu_miss_fault(istate_t *istate,
    const char *str)
{
    fault_if_from_uspace(istate, "%s\n", str);
    dump_istate(istate);
    panic("%s\n", str);
}
#endif
 
#if 0
void do_fast_data_access_mmu_miss_fault(istate_t *istate,
    tlb_tag_access_reg_t tag, const char *str)
{
    uintptr_t va;
 
    va = tag.vpn << MMU_PAGE_WIDTH;
    if (tag.context) {
        fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d)\n", str, va,
            tag.context);
    }
    dump_istate(istate);
    printf("Faulting page: %p, ASID=%d\n", va, tag.context);
    panic("%s\n", str);
}
#endif
 
#if 0
void do_fast_data_access_protection_fault(istate_t *istate,
    tlb_tag_access_reg_t tag, const char *str)
{
    uintptr_t va;
 
    va = tag.vpn << MMU_PAGE_WIDTH;
 
    if (tag.context) {
        fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d)\n", str, va,
            tag.context);
    }
    printf("Faulting page: %p, ASID=%d\n", va, tag.context);
    dump_istate(istate);
    panic("%s\n", str);
}
#endif
 
void describe_mmu_fault(void)
{
}
 
#if defined (US3)
/** Invalidates given TLB entry if and only if it is non-locked or global.
 *
 * @param tlb       TLB number (one of TLB_DSMALL, TLB_DBIG_0, TLB_DBIG_1,
 *          TLB_ISMALL, TLB_IBIG).
 * @param entry     Entry index within the given TLB.
 */
#if 0
static void tlb_invalidate_entry(int tlb, index_t entry)
{
    tlb_data_t d;
    tlb_tag_read_reg_t t;
   
    if (tlb == TLB_DSMALL || tlb == TLB_DBIG_0 || tlb == TLB_DBIG_1) {
        d.value = dtlb_data_access_read(tlb, entry);
        if (!d.l || d.g) {
            t.value = dtlb_tag_read_read(tlb, entry);
            d.v = false;
            dtlb_tag_access_write(t.value);
            dtlb_data_access_write(tlb, entry, d.value);
        }
    } else if (tlb == TLB_ISMALL || tlb == TLB_IBIG) {
        d.value = itlb_data_access_read(tlb, entry);
        if (!d.l || d.g) {
            t.value = itlb_tag_read_read(tlb, entry);
            d.v = false;
            itlb_tag_access_write(t.value);
            itlb_data_access_write(tlb, entry, d.value);
        }
    }
}
#endif
#endif
 
/** Invalidate all unlocked ITLB and DTLB entries. */
void tlb_invalidate_all(void)
{
    uint64_t errno =  __hypercall_fast3(MMU_DEMAP_ALL, 0, 0,
        MMU_FLAG_DTLB | MMU_FLAG_ITLB);
    if (errno != EOK) {
        panic("Error code = %d.\n", errno);
    }
}
 
/** Invalidate all ITLB and DTLB entries that belong to specified ASID
 * (Context).
 *
 * @param asid Address Space ID.
 */
void tlb_invalidate_asid(asid_t asid)
{
#if 0
    tlb_context_reg_t pc_save, ctx;
   
    /* switch to nucleus because we are mapped by the primary context */
    nucleus_enter();
   
    ctx.v = pc_save.v = mmu_primary_context_read();
    ctx.context = asid;
    mmu_primary_context_write(ctx.v);
   
    itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_PRIMARY, 0);
    dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_PRIMARY, 0);
   
    mmu_primary_context_write(pc_save.v);
   
    nucleus_leave();
#endif
}
 
/** Invalidate all ITLB and DTLB entries for specified page range in specified
 * address space.
 *
 * @param asid      Address Space ID.
 * @param page      First page which to sweep out from ITLB and DTLB.
 * @param cnt       Number of ITLB and DTLB entries to invalidate.
 */
void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt)
{
#if 0
    unsigned int i;
    tlb_context_reg_t pc_save, ctx;
   
    /* switch to nucleus because we are mapped by the primary context */
    nucleus_enter();
   
    ctx.v = pc_save.v = mmu_primary_context_read();
    ctx.context = asid;
    mmu_primary_context_write(ctx.v);
   
    for (i = 0; i < cnt * MMU_PAGES_PER_PAGE; i++) {
        itlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_PRIMARY,
            page + i * MMU_PAGE_SIZE);
        dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_PRIMARY,
            page + i * MMU_PAGE_SIZE);
    }
   
    mmu_primary_context_write(pc_save.v);
   
    nucleus_leave();
#endif
}
 
/** @}
 */
 

Rev 3835	Rev 3862
1	/*	1	/*
2	* Copyright (c) 2005 Jakub Jermar	2	* Copyright (c) 2005 Jakub Jermar
3	* Copyright (c) 2008 Pavel Rimsky	3	* Copyright (c) 2008 Pavel Rimsky
4	* All rights reserved.	4	* All rights reserved.
5	*	5	*
6	* Redistribution and use in source and binary forms, with or without	6	* Redistribution and use in source and binary forms, with or without
7	* modification, are permitted provided that the following conditions	7	* modification, are permitted provided that the following conditions
8	* are met:	8	* are met:
9	*	9	*
10	* - Redistributions of source code must retain the above copyright	10	* - Redistributions of source code must retain the above copyright
11	* notice, this list of conditions and the following disclaimer.	11	* notice, this list of conditions and the following disclaimer.
12	* - Redistributions in binary form must reproduce the above copyright	12	* - Redistributions in binary form must reproduce the above copyright
13	* notice, this list of conditions and the following disclaimer in the	13	* notice, this list of conditions and the following disclaimer in the
14	* documentation and/or other materials provided with the distribution.	14	* documentation and/or other materials provided with the distribution.
15	* - The name of the author may not be used to endorse or promote products	15	* - The name of the author may not be used to endorse or promote products
16	* derived from this software without specific prior written permission.	16	* derived from this software without specific prior written permission.
17	*	17	*
18	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	18	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	19	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	20	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	21	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	22	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	23	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	24	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	25	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	26	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	27	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28	*/	28	*/
29		29
30	/** @addtogroup sparc64mm	30	/** @addtogroup sparc64mm
31	* @{	31	* @{
32	*/	32	*/
33	/** @file	33	/** @file
34	*/	34	*/
35		35
36	#include <mm/tlb.h>	36	#include <mm/tlb.h>
37	#include <mm/as.h>	37	#include <mm/as.h>
38	#include <mm/asid.h>	38	#include <mm/asid.h>
39	#include <arch/sun4v/hypercall.h>	39	#include <arch/sun4v/hypercall.h>
40	#include <arch/mm/frame.h>	40	#include <arch/mm/frame.h>
41	#include <arch/mm/page.h>	41	#include <arch/mm/page.h>
42	#include <arch/mm/sun4v/tte.h>	42	#include <arch/mm/tte.h>
43	#include <arch/mm/sun4v/tlb.h>	43	#include <arch/mm/tlb.h>
44	#include <arch/interrupt.h>	44	#include <arch/interrupt.h>
45	#include <interrupt.h>	45	#include <interrupt.h>
46	#include <arch.h>	46	#include <arch.h>
47	#include <print.h>	47	#include <print.h>
48	#include <arch/types.h>	48	#include <arch/types.h>
49	#include <config.h>	49	#include <config.h>
50	#include <arch/trap/trap.h>	50	#include <arch/trap/trap.h>
51	#include <arch/trap/exception.h>	51	#include <arch/trap/exception.h>
52	#include <panic.h>	52	#include <panic.h>
53	#include <arch/asm.h>	53	#include <arch/asm.h>
54	#include <arch/sun4v/cpu.h>	54	#include <arch/cpu.h>
55		55
56	#ifdef CONFIG_TSB	56	#ifdef CONFIG_TSB
57	#include <arch/mm/tsb.h>	57	#include <arch/mm/tsb.h>
58	#endif	58	#endif
59		59
60	#if 0	60	#if 0
61	static void dtlb_pte_copy(pte_t *, index_t, bool);	61	static void dtlb_pte_copy(pte_t *, index_t, bool);
62	static void itlb_pte_copy(pte_t *, index_t);	62	static void itlb_pte_copy(pte_t *, index_t);
63	static void do_fast_instruction_access_mmu_miss_fault(istate_t , const char );	63	static void do_fast_instruction_access_mmu_miss_fault(istate_t , const char );
64	static void do_fast_data_access_mmu_miss_fault(istate_t *, tlb_tag_access_reg_t,	64	static void do_fast_data_access_mmu_miss_fault(istate_t *, tlb_tag_access_reg_t,
65	const char *);	65	const char *);
66	static void do_fast_data_access_protection_fault(istate_t *,	66	static void do_fast_data_access_protection_fault(istate_t *,
67	tlb_tag_access_reg_t, const char *);	67	tlb_tag_access_reg_t, const char *);
68		68
69	char *context_encoding[] = {	69	char *context_encoding[] = {
70	"Primary",	70	"Primary",
71	"Secondary",	71	"Secondary",
72	"Nucleus",	72	"Nucleus",
73	"Reserved"	73	"Reserved"
74	};	74	};
75	#endif	75	#endif
76		76
77	/*	77	/*
78	* Invalidate all non-locked DTLB and ITLB entries.	78	* Invalidate all non-locked DTLB and ITLB entries.
79	*/	79	*/
80	void tlb_arch_init(void)	80	void tlb_arch_init(void)
81	{	81	{
82	tlb_invalidate_all();	82	tlb_invalidate_all();
83	}	83	}
84		84
85	/** Insert privileged mapping into DMMU TLB.	85	/** Insert privileged mapping into DMMU TLB.
86	*	86	*
87	* @param page Virtual page address.	87	* @param page Virtual page address.
88	* @param frame Physical frame address.	88	* @param frame Physical frame address.
89	* @param pagesize Page size.	89	* @param pagesize Page size.
90	* @param locked True for permanent mappings, false otherwise.	90	* @param locked True for permanent mappings, false otherwise.
91	* @param cacheable True if the mapping is cacheable, false otherwise.	91	* @param cacheable True if the mapping is cacheable, false otherwise.
92	*/	92	*/
93	void dtlb_insert_mapping(uintptr_t page, uintptr_t frame, int pagesize,	93	void dtlb_insert_mapping(uintptr_t page, uintptr_t frame, int pagesize,
94	bool locked, bool cacheable)	94	bool locked, bool cacheable)
95	{	95	{
96	#if 0	96	#if 0
97	tlb_tag_access_reg_t tag;	97	tlb_tag_access_reg_t tag;
98	tlb_data_t data;	98	tlb_data_t data;
99	page_address_t pg;	99	page_address_t pg;
100	frame_address_t fr;	100	frame_address_t fr;
101		101
102	pg.address = page;	102	pg.address = page;
103	fr.address = frame;	103	fr.address = frame;
104		104
105	tag.context = ASID_KERNEL;	105	tag.context = ASID_KERNEL;
106	tag.vpn = pg.vpn;	106	tag.vpn = pg.vpn;
107		107
108	dtlb_tag_access_write(tag.value);	108	dtlb_tag_access_write(tag.value);
109		109
110	data.value = 0;	110	data.value = 0;
111	data.v = true;	111	data.v = true;
112	data.size = pagesize;	112	data.size = pagesize;
113	data.pfn = fr.pfn;	113	data.pfn = fr.pfn;
114	data.l = locked;	114	data.l = locked;
115	data.cp = cacheable;	115	data.cp = cacheable;
116	#ifdef CONFIG_VIRT_IDX_DCACHE	116	#ifdef CONFIG_VIRT_IDX_DCACHE
117	data.cv = cacheable;	117	data.cv = cacheable;
118	#endif /* CONFIG_VIRT_IDX_DCACHE */	118	#endif /* CONFIG_VIRT_IDX_DCACHE */
119	data.p = true;	119	data.p = true;
120	data.w = true;	120	data.w = true;
121	data.g = false;	121	data.g = false;
122		122
123	dtlb_data_in_write(data.value);	123	dtlb_data_in_write(data.value);
124	#endif	124	#endif
125	}	125	}
126		126
127	/** Copy PTE to TLB.	127	/** Copy PTE to TLB.
128	*	128	*
129	* @param t Page Table Entry to be copied.	129	* @param t Page Table Entry to be copied.
130	* @param index Zero if lower 8K-subpage, one if higher 8K-subpage.	130	* @param index Zero if lower 8K-subpage, one if higher 8K-subpage.
131	* @param ro If true, the entry will be created read-only, regardless	131	* @param ro If true, the entry will be created read-only, regardless
132	* of its w field.	132	* of its w field.
133	*/	133	*/
134	#if 0	134	#if 0
135	void dtlb_pte_copy(pte_t *t, index_t index, bool ro)	135	void dtlb_pte_copy(pte_t *t, index_t index, bool ro)
136	{	136	{
137	tlb_tag_access_reg_t tag;	137	tlb_tag_access_reg_t tag;
138	tlb_data_t data;	138	tlb_data_t data;
139	page_address_t pg;	139	page_address_t pg;
140	frame_address_t fr;	140	frame_address_t fr;
141		141
142	pg.address = t->page + (index << MMU_PAGE_WIDTH);	142	pg.address = t->page + (index << MMU_PAGE_WIDTH);
143	fr.address = t->frame + (index << MMU_PAGE_WIDTH);	143	fr.address = t->frame + (index << MMU_PAGE_WIDTH);
144		144
145	tag.value = 0;	145	tag.value = 0;
146	tag.context = t->as->asid;	146	tag.context = t->as->asid;
147	tag.vpn = pg.vpn;	147	tag.vpn = pg.vpn;
148		148
149	dtlb_tag_access_write(tag.value);	149	dtlb_tag_access_write(tag.value);
150		150
151	data.value = 0;	151	data.value = 0;
152	data.v = true;	152	data.v = true;
153	data.size = PAGESIZE_8K;	153	data.size = PAGESIZE_8K;
154	data.pfn = fr.pfn;	154	data.pfn = fr.pfn;
155	data.l = false;	155	data.l = false;
156	data.cp = t->c;	156	data.cp = t->c;
157	#ifdef CONFIG_VIRT_IDX_DCACHE	157	#ifdef CONFIG_VIRT_IDX_DCACHE
158	data.cv = t->c;	158	data.cv = t->c;
159	#endif /* CONFIG_VIRT_IDX_DCACHE */	159	#endif /* CONFIG_VIRT_IDX_DCACHE */
160	data.p = t->k; /* p like privileged */	160	data.p = t->k; /* p like privileged */
161	data.w = ro ? false : t->w;	161	data.w = ro ? false : t->w;
162	data.g = t->g;	162	data.g = t->g;
163		163
164	dtlb_data_in_write(data.value);	164	dtlb_data_in_write(data.value);
165	}	165	}
166	#endif	166	#endif
167		167
168	/** Copy PTE to ITLB.	168	/** Copy PTE to ITLB.
169	*	169	*
170	* @param t Page Table Entry to be copied.	170	* @param t Page Table Entry to be copied.
171	* @param index Zero if lower 8K-subpage, one if higher 8K-subpage.	171	* @param index Zero if lower 8K-subpage, one if higher 8K-subpage.
172	*/	172	*/
173	#if 0	173	#if 0
174	void itlb_pte_copy(pte_t *t, index_t index)	174	void itlb_pte_copy(pte_t *t, index_t index)
175	{	175	{
176	tlb_tag_access_reg_t tag;	176	tlb_tag_access_reg_t tag;
177	tlb_data_t data;	177	tlb_data_t data;
178	page_address_t pg;	178	page_address_t pg;
179	frame_address_t fr;	179	frame_address_t fr;
180		180
181	pg.address = t->page + (index << MMU_PAGE_WIDTH);	181	pg.address = t->page + (index << MMU_PAGE_WIDTH);
182	fr.address = t->frame + (index << MMU_PAGE_WIDTH);	182	fr.address = t->frame + (index << MMU_PAGE_WIDTH);
183		183
184	tag.value = 0;	184	tag.value = 0;
185	tag.context = t->as->asid;	185	tag.context = t->as->asid;
186	tag.vpn = pg.vpn;	186	tag.vpn = pg.vpn;
187		187
188	itlb_tag_access_write(tag.value);	188	itlb_tag_access_write(tag.value);
189		189
190	data.value = 0;	190	data.value = 0;
191	data.v = true;	191	data.v = true;
192	data.size = PAGESIZE_8K;	192	data.size = PAGESIZE_8K;
193	data.pfn = fr.pfn;	193	data.pfn = fr.pfn;
194	data.l = false;	194	data.l = false;
195	data.cp = t->c;	195	data.cp = t->c;
196	data.p = t->k; /* p like privileged */	196	data.p = t->k; /* p like privileged */
197	data.w = false;	197	data.w = false;
198	data.g = t->g;	198	data.g = t->g;
199		199
200	itlb_data_in_write(data.value);	200	itlb_data_in_write(data.value);
201	}	201	}
202	#endif	202	#endif
203		203
204	/** ITLB miss handler. */	204	/** ITLB miss handler. */
205	void fast_instruction_access_mmu_miss(unative_t unused, istate_t *istate)	205	void fast_instruction_access_mmu_miss(unative_t unused, istate_t *istate)
206	{	206	{
207	#if 0	207	#if 0
208	uintptr_t va = ALIGN_DOWN(istate->tpc, PAGE_SIZE);	208	uintptr_t va = ALIGN_DOWN(istate->tpc, PAGE_SIZE);
209	index_t index = (istate->tpc >> MMU_PAGE_WIDTH) % MMU_PAGES_PER_PAGE;	209	index_t index = (istate->tpc >> MMU_PAGE_WIDTH) % MMU_PAGES_PER_PAGE;
210	pte_t *t;	210	pte_t *t;
211		211
212	page_table_lock(AS, true);	212	page_table_lock(AS, true);
213	t = page_mapping_find(AS, va);	213	t = page_mapping_find(AS, va);
214	if (t && PTE_EXECUTABLE(t)) {	214	if (t && PTE_EXECUTABLE(t)) {
215	/*	215	/*
216	* The mapping was found in the software page hash table.	216	* The mapping was found in the software page hash table.
217	* Insert it into ITLB.	217	* Insert it into ITLB.
218	*/	218	*/
219	t->a = true;	219	t->a = true;
220	itlb_pte_copy(t, index);	220	itlb_pte_copy(t, index);
221	#ifdef CONFIG_TSB	221	#ifdef CONFIG_TSB
222	itsb_pte_copy(t, index);	222	itsb_pte_copy(t, index);
223	#endif	223	#endif
224	page_table_unlock(AS, true);	224	page_table_unlock(AS, true);
225	} else {	225	} else {
226	/*	226	/*
227	* Forward the page fault to the address space page fault	227	* Forward the page fault to the address space page fault
228	* handler.	228	* handler.
229	*/	229	*/
230	page_table_unlock(AS, true);	230	page_table_unlock(AS, true);
231	if (as_page_fault(va, PF_ACCESS_EXEC, istate) == AS_PF_FAULT) {	231	if (as_page_fault(va, PF_ACCESS_EXEC, istate) == AS_PF_FAULT) {
232	do_fast_instruction_access_mmu_miss_fault(istate,	232	do_fast_instruction_access_mmu_miss_fault(istate,
233	__func__);	233	__func__);
234	}	234	}
235	}	235	}
236	#endif	236	#endif
237	}	237	}
238		238
239	/** DTLB miss handler.	239	/** DTLB miss handler.
240	*	240	*
241	* Note that some faults (e.g. kernel faults) were already resolved by the	241	* Note that some faults (e.g. kernel faults) were already resolved by the
242	* low-level, assembly language part of the fast_data_access_mmu_miss handler.	242	* low-level, assembly language part of the fast_data_access_mmu_miss handler.
243	*	243	*
244	* @param tag Content of the TLB Tag Access register as it existed	244	* @param tag Content of the TLB Tag Access register as it existed
245	* when the trap happened. This is to prevent confusion	245	* when the trap happened. This is to prevent confusion
246	* created by clobbered Tag Access register during a nested	246	* created by clobbered Tag Access register during a nested
247	* DTLB miss.	247	* DTLB miss.
248	* @param istate Interrupted state saved on the stack.	248	* @param istate Interrupted state saved on the stack.
249	*/	249	*/
250	//void fast_data_access_mmu_miss(tlb_tag_access_reg_t tag, istate_t *istate)	250	//void fast_data_access_mmu_miss(tlb_tag_access_reg_t tag, istate_t *istate)
251	//{	251	//{
252	#if 0	252	#if 0
253	uintptr_t va;	253	uintptr_t va;
254	index_t index;	254	index_t index;
255	pte_t *t;	255	pte_t *t;
256		256
257	va = ALIGN_DOWN((uint64_t) tag.vpn << MMU_PAGE_WIDTH, PAGE_SIZE);	257	va = ALIGN_DOWN((uint64_t) tag.vpn << MMU_PAGE_WIDTH, PAGE_SIZE);
258	index = tag.vpn % MMU_PAGES_PER_PAGE;	258	index = tag.vpn % MMU_PAGES_PER_PAGE;
259		259
260	if (tag.context == ASID_KERNEL) {	260	if (tag.context == ASID_KERNEL) {
261	if (!tag.vpn) {	261	if (!tag.vpn) {
262	/* NULL access in kernel */	262	/* NULL access in kernel */
263	do_fast_data_access_mmu_miss_fault(istate, tag,	263	do_fast_data_access_mmu_miss_fault(istate, tag,
264	__func__);	264	__func__);
265	}	265	}
266	do_fast_data_access_mmu_miss_fault(istate, tag, "Unexpected "	266	do_fast_data_access_mmu_miss_fault(istate, tag, "Unexpected "
267	"kernel page fault.");	267	"kernel page fault.");
268	}	268	}
269		269
270	page_table_lock(AS, true);	270	page_table_lock(AS, true);
271	t = page_mapping_find(AS, va);	271	t = page_mapping_find(AS, va);
272	if (t) {	272	if (t) {
273	/*	273	/*
274	* The mapping was found in the software page hash table.	274	* The mapping was found in the software page hash table.
275	* Insert it into DTLB.	275	* Insert it into DTLB.
276	*/	276	*/
277	t->a = true;	277	t->a = true;
278	dtlb_pte_copy(t, index, true);	278	dtlb_pte_copy(t, index, true);
279	#ifdef CONFIG_TSB	279	#ifdef CONFIG_TSB
280	dtsb_pte_copy(t, index, true);	280	dtsb_pte_copy(t, index, true);
281	#endif	281	#endif
282	page_table_unlock(AS, true);	282	page_table_unlock(AS, true);
283	} else {	283	} else {
284	/*	284	/*
285	* Forward the page fault to the address space page fault	285	* Forward the page fault to the address space page fault
286	* handler.	286	* handler.
287	*/	287	*/
288	page_table_unlock(AS, true);	288	page_table_unlock(AS, true);
289	if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) {	289	if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) {
290	do_fast_data_access_mmu_miss_fault(istate, tag,	290	do_fast_data_access_mmu_miss_fault(istate, tag,
291	__func__);	291	__func__);
292	}	292	}
293	}	293	}
294	#endif	294	#endif
295	//}	295	//}
296		296
297	/** DTLB protection fault handler.	297	/** DTLB protection fault handler.
298	*	298	*
299	* @param tag Content of the TLB Tag Access register as it existed	299	* @param tag Content of the TLB Tag Access register as it existed
300	* when the trap happened. This is to prevent confusion	300	* when the trap happened. This is to prevent confusion
301	* created by clobbered Tag Access register during a nested	301	* created by clobbered Tag Access register during a nested
302	* DTLB miss.	302	* DTLB miss.
303	* @param istate Interrupted state saved on the stack.	303	* @param istate Interrupted state saved on the stack.
304	*/	304	*/
305	//void fast_data_access_protection(tlb_tag_access_reg_t tag, istate_t *istate)	305	//void fast_data_access_protection(tlb_tag_access_reg_t tag, istate_t *istate)
306	//{	306	//{
307	#if 0	307	#if 0
308	uintptr_t va;	308	uintptr_t va;
309	index_t index;	309	index_t index;
310	pte_t *t;	310	pte_t *t;
311		311
312	va = ALIGN_DOWN((uint64_t) tag.vpn << MMU_PAGE_WIDTH, PAGE_SIZE);	312	va = ALIGN_DOWN((uint64_t) tag.vpn << MMU_PAGE_WIDTH, PAGE_SIZE);
313	index = tag.vpn % MMU_PAGES_PER_PAGE; /* 16K-page emulation */	313	index = tag.vpn % MMU_PAGES_PER_PAGE; /* 16K-page emulation */
314		314
315	page_table_lock(AS, true);	315	page_table_lock(AS, true);
316	t = page_mapping_find(AS, va);	316	t = page_mapping_find(AS, va);
317	if (t && PTE_WRITABLE(t)) {	317	if (t && PTE_WRITABLE(t)) {
318	/*	318	/*
319	* The mapping was found in the software page hash table and is	319	* The mapping was found in the software page hash table and is
320	* writable. Demap the old mapping and insert an updated mapping	320	* writable. Demap the old mapping and insert an updated mapping
321	* into DTLB.	321	* into DTLB.
322	*/	322	*/
323	t->a = true;	323	t->a = true;
324	t->d = true;	324	t->d = true;
325	dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_SECONDARY,	325	dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_SECONDARY,
326	va + index * MMU_PAGE_SIZE);	326	va + index * MMU_PAGE_SIZE);
327	dtlb_pte_copy(t, index, false);	327	dtlb_pte_copy(t, index, false);
328	#ifdef CONFIG_TSB	328	#ifdef CONFIG_TSB
329	dtsb_pte_copy(t, index, false);	329	dtsb_pte_copy(t, index, false);
330	#endif	330	#endif
331	page_table_unlock(AS, true);	331	page_table_unlock(AS, true);
332	} else {	332	} else {
333	/*	333	/*
334	* Forward the page fault to the address space page fault	334	* Forward the page fault to the address space page fault
335	* handler.	335	* handler.
336	*/	336	*/
337	page_table_unlock(AS, true);	337	page_table_unlock(AS, true);
338	if (as_page_fault(va, PF_ACCESS_WRITE, istate) == AS_PF_FAULT) {	338	if (as_page_fault(va, PF_ACCESS_WRITE, istate) == AS_PF_FAULT) {
339	do_fast_data_access_protection_fault(istate, tag,	339	do_fast_data_access_protection_fault(istate, tag,
340	__func__);	340	__func__);
341	}	341	}
342	}	342	}
343	#endif	343	#endif
344	//}	344	//}
345		345
346	/** Print TLB entry (for debugging purposes).	346	/** Print TLB entry (for debugging purposes).
347	*	347	*
348	* The diag field has been left out in order to make this function more generic	348	* The diag field has been left out in order to make this function more generic
349	* (there is no diag field in US3 architeture).	349	* (there is no diag field in US3 architeture).
350	*	350	*
351	* @param i TLB entry number	351	* @param i TLB entry number
352	* @param t TLB entry tag	352	* @param t TLB entry tag
353	* @param d TLB entry data	353	* @param d TLB entry data
354	*/	354	*/
355	#if 0	355	#if 0
356	static void print_tlb_entry(int i, tlb_tag_read_reg_t t, tlb_data_t d)	356	static void print_tlb_entry(int i, tlb_tag_read_reg_t t, tlb_data_t d)
357	{	357	{
358	printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, "	358	printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, "
359	"ie=%d, soft2=%#x, pfn=%#x, soft=%#x, l=%d, "	359	"ie=%d, soft2=%#x, pfn=%#x, soft=%#x, l=%d, "
360	"cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n", i, t.vpn,	360	"cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n", i, t.vpn,
361	t.context, d.v, d.size, d.nfo, d.ie, d.soft2,	361	t.context, d.v, d.size, d.nfo, d.ie, d.soft2,
362	d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);	362	d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);
363	}	363	}
364	#endif	364	#endif
365		365
366	#if defined (US)	366	#if defined (US)
367		367
368	/** Print contents of both TLBs. */	368	/** Print contents of both TLBs. */
369	void tlb_print(void)	369	void tlb_print(void)
370	#if 0	370	#if 0
371	{	371	{
372	int i;	372	int i;
373	tlb_data_t d;	373	tlb_data_t d;
374	tlb_tag_read_reg_t t;	374	tlb_tag_read_reg_t t;
375		375
376	printf("I-TLB contents:\n");	376	printf("I-TLB contents:\n");
377	for (i = 0; i < ITLB_ENTRY_COUNT; i++) {	377	for (i = 0; i < ITLB_ENTRY_COUNT; i++) {
378	d.value = itlb_data_access_read(i);	378	d.value = itlb_data_access_read(i);
379	t.value = itlb_tag_read_read(i);	379	t.value = itlb_tag_read_read(i);
380	print_tlb_entry(i, t, d);	380	print_tlb_entry(i, t, d);
381	}	381	}
382		382
383	printf("D-TLB contents:\n");	383	printf("D-TLB contents:\n");
384	for (i = 0; i < DTLB_ENTRY_COUNT; i++) {	384	for (i = 0; i < DTLB_ENTRY_COUNT; i++) {
385	d.value = dtlb_data_access_read(i);	385	d.value = dtlb_data_access_read(i);
386	t.value = dtlb_tag_read_read(i);	386	t.value = dtlb_tag_read_read(i);
387	print_tlb_entry(i, t, d);	387	print_tlb_entry(i, t, d);
388	}	388	}
389	#endif	389	#endif
390	}	390	}
391		391
392	#elif defined (US3)	392	#elif defined (US3)
393		393
394	/** Print contents of all TLBs. */	394	/** Print contents of all TLBs. */
395	void tlb_print(void)	395	void tlb_print(void)
396	{	396	{
397	#if 0	397	#if 0
398	int i;	398	int i;
399	tlb_data_t d;	399	tlb_data_t d;
400	tlb_tag_read_reg_t t;	400	tlb_tag_read_reg_t t;
401		401
402	printf("TLB_ISMALL contents:\n");	402	printf("TLB_ISMALL contents:\n");
403	for (i = 0; i < tlb_ismall_size(); i++) {	403	for (i = 0; i < tlb_ismall_size(); i++) {
404	d.value = dtlb_data_access_read(TLB_ISMALL, i);	404	d.value = dtlb_data_access_read(TLB_ISMALL, i);
405	t.value = dtlb_tag_read_read(TLB_ISMALL, i);	405	t.value = dtlb_tag_read_read(TLB_ISMALL, i);
406	print_tlb_entry(i, t, d);	406	print_tlb_entry(i, t, d);
407	}	407	}
408		408
409	printf("TLB_IBIG contents:\n");	409	printf("TLB_IBIG contents:\n");
410	for (i = 0; i < tlb_ibig_size(); i++) {	410	for (i = 0; i < tlb_ibig_size(); i++) {
411	d.value = dtlb_data_access_read(TLB_IBIG, i);	411	d.value = dtlb_data_access_read(TLB_IBIG, i);
412	t.value = dtlb_tag_read_read(TLB_IBIG, i);	412	t.value = dtlb_tag_read_read(TLB_IBIG, i);
413	print_tlb_entry(i, t, d);	413	print_tlb_entry(i, t, d);
414	}	414	}
415		415
416	printf("TLB_DSMALL contents:\n");	416	printf("TLB_DSMALL contents:\n");
417	for (i = 0; i < tlb_dsmall_size(); i++) {	417	for (i = 0; i < tlb_dsmall_size(); i++) {
418	d.value = dtlb_data_access_read(TLB_DSMALL, i);	418	d.value = dtlb_data_access_read(TLB_DSMALL, i);
419	t.value = dtlb_tag_read_read(TLB_DSMALL, i);	419	t.value = dtlb_tag_read_read(TLB_DSMALL, i);
420	print_tlb_entry(i, t, d);	420	print_tlb_entry(i, t, d);
421	}	421	}
422		422
423	printf("TLB_DBIG_1 contents:\n");	423	printf("TLB_DBIG_1 contents:\n");
424	for (i = 0; i < tlb_dbig_size(); i++) {	424	for (i = 0; i < tlb_dbig_size(); i++) {
425	d.value = dtlb_data_access_read(TLB_DBIG_0, i);	425	d.value = dtlb_data_access_read(TLB_DBIG_0, i);
426	t.value = dtlb_tag_read_read(TLB_DBIG_0, i);	426	t.value = dtlb_tag_read_read(TLB_DBIG_0, i);
427	print_tlb_entry(i, t, d);	427	print_tlb_entry(i, t, d);
428	}	428	}
429		429
430	printf("TLB_DBIG_2 contents:\n");	430	printf("TLB_DBIG_2 contents:\n");
431	for (i = 0; i < tlb_dbig_size(); i++) {	431	for (i = 0; i < tlb_dbig_size(); i++) {
432	d.value = dtlb_data_access_read(TLB_DBIG_1, i);	432	d.value = dtlb_data_access_read(TLB_DBIG_1, i);
433	t.value = dtlb_tag_read_read(TLB_DBIG_1, i);	433	t.value = dtlb_tag_read_read(TLB_DBIG_1, i);
434	print_tlb_entry(i, t, d);	434	print_tlb_entry(i, t, d);
435	}	435	}
436	#endif	436	#endif
437	}	437	}
438		438
439	#endif	439	#endif
440		440
441	#if 0	441	#if 0
442	void do_fast_instruction_access_mmu_miss_fault(istate_t *istate,	442	void do_fast_instruction_access_mmu_miss_fault(istate_t *istate,
443	const char *str)	443	const char *str)
444	{	444	{
445	fault_if_from_uspace(istate, "%s\n", str);	445	fault_if_from_uspace(istate, "%s\n", str);
446	dump_istate(istate);	446	dump_istate(istate);
447	panic("%s\n", str);	447	panic("%s\n", str);
448	}	448	}
449	#endif	449	#endif
450		450
451	#if 0	451	#if 0
452	void do_fast_data_access_mmu_miss_fault(istate_t *istate,	452	void do_fast_data_access_mmu_miss_fault(istate_t *istate,
453	tlb_tag_access_reg_t tag, const char *str)	453	tlb_tag_access_reg_t tag, const char *str)
454	{	454	{
455	uintptr_t va;	455	uintptr_t va;
456		456
457	va = tag.vpn << MMU_PAGE_WIDTH;	457	va = tag.vpn << MMU_PAGE_WIDTH;
458	if (tag.context) {	458	if (tag.context) {
459	fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d)\n", str, va,	459	fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d)\n", str, va,
460	tag.context);	460	tag.context);
461	}	461	}
462	dump_istate(istate);	462	dump_istate(istate);
463	printf("Faulting page: %p, ASID=%d\n", va, tag.context);	463	printf("Faulting page: %p, ASID=%d\n", va, tag.context);
464	panic("%s\n", str);	464	panic("%s\n", str);
465	}	465	}
466	#endif	466	#endif
467		467
468	#if 0	468	#if 0
469	void do_fast_data_access_protection_fault(istate_t *istate,	469	void do_fast_data_access_protection_fault(istate_t *istate,
470	tlb_tag_access_reg_t tag, const char *str)	470	tlb_tag_access_reg_t tag, const char *str)
471	{	471	{
472	uintptr_t va;	472	uintptr_t va;
473		473
474	va = tag.vpn << MMU_PAGE_WIDTH;	474	va = tag.vpn << MMU_PAGE_WIDTH;
475		475
476	if (tag.context) {	476	if (tag.context) {
477	fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d)\n", str, va,	477	fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d)\n", str, va,
478	tag.context);	478	tag.context);
479	}	479	}
480	printf("Faulting page: %p, ASID=%d\n", va, tag.context);	480	printf("Faulting page: %p, ASID=%d\n", va, tag.context);
481	dump_istate(istate);	481	dump_istate(istate);
482	panic("%s\n", str);	482	panic("%s\n", str);
483	}	483	}
484	#endif	484	#endif
485		485
486	void describe_mmu_fault(void)	486	void describe_mmu_fault(void)
487	{	487	{
488	}	488	}
489		489
490	#if defined (US3)	490	#if defined (US3)
491	/** Invalidates given TLB entry if and only if it is non-locked or global.	491	/** Invalidates given TLB entry if and only if it is non-locked or global.
492	*	492	*
493	* @param tlb TLB number (one of TLB_DSMALL, TLB_DBIG_0, TLB_DBIG_1,	493	* @param tlb TLB number (one of TLB_DSMALL, TLB_DBIG_0, TLB_DBIG_1,
494	* TLB_ISMALL, TLB_IBIG).	494	* TLB_ISMALL, TLB_IBIG).
495	* @param entry Entry index within the given TLB.	495	* @param entry Entry index within the given TLB.
496	*/	496	*/
497	#if 0	497	#if 0
498	static void tlb_invalidate_entry(int tlb, index_t entry)	498	static void tlb_invalidate_entry(int tlb, index_t entry)
499	{	499	{
500	tlb_data_t d;	500	tlb_data_t d;

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(root)/branches/sparc/kernel/arch/sparc64/src/mm/sun4v/tlb.c – Rev 3835 → 3862