WebSVN – HelenOS – Diff – /branches/sparc/kernel/arch/sparc64/src/drivers/tick.c


/*
 * Copyright (c) 2005 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup sparc64
 * @{
 */
/** @file
 */
 
#include <arch/drivers/tick.h>
#include <arch/interrupt.h>
#include <arch/sparc64.h>
#include <arch/asm.h>
#include <arch/register.h>
#include <arch/cpu.h>
#include <arch/boot/boot.h>
#include <time/clock.h>
#include <arch.h>
#include <debug.h>
 
#define TICK_RESTART_TIME   50  /* Worst case estimate. */
 
/** Initialize tick and stick interrupt. */
void tick_init(void)
{
    /* initialize TICK interrupt */
    tick_compare_reg_t compare;
 
    interrupt_register(14, "tick_int", tick_interrupt);
    compare.int_dis = false;
    compare.tick_cmpr = tick_counter_read() +
        CPU->arch.clock_frequency / HZ;
    CPU->arch.next_tick_cmpr = compare.tick_cmpr;
    tick_compare_write(compare.value);
 
 
#if defined (US3)
    /* disable STICK interrupts and clear any pending ones */
    tick_compare_reg_t stick_compare;
    softint_reg_t clear;
 
    stick_compare.value = stick_compare_read();
    stick_compare.int_dis = true;
    stick_compare.tick_cmpr = 0;
    stick_compare_write(stick_compare.value);
 
    clear.value = 0;
    clear.stick_int = 1;
    clear_softint_write(clear.value);
#endif
}
 
/** Process tick interrupt.
 *
 * @param n Interrupt Level, 14,  (can be ignored)
 * @param istate Interrupted state.
 */
void tick_interrupt(int n, istate_t *istate)
{
    softint_reg_t softint, clear;
    uint64_t drift;
 
    softint.value = softint_read();
   
    /*
     * Make sure we are servicing interrupt_level_14
     */
    ASSERT(n == 14);
   
    /*
     * Make sure we are servicing TICK_INT.
     */
    ASSERT(softint.tick_int);
 
    /*
     * Clear tick interrupt.
     */
    clear.value = 0;
    clear.tick_int = 1;
    clear_softint_write(clear.value);
   
    /*
     * Reprogram the compare register.
     * For now, we can ignore the potential of the registers to overflow.
     * On a 360MHz Ultra 60, the 63-bit compare counter will overflow in
     * about 812 years. If there was a 2GHz UltraSPARC computer, it would
     * overflow only in 146 years.
     */
    drift = tick_counter_read() - CPU->arch.next_tick_cmpr;
    while (drift > CPU->arch.clock_frequency / HZ) {
        drift -= CPU->arch.clock_frequency / HZ;
        CPU->missed_clock_ticks++;
    }
    CPU->arch.next_tick_cmpr = tick_counter_read() +
        (CPU->arch.clock_frequency / HZ) - drift;
    tick_compare_write(CPU->arch.next_tick_cmpr);
    clock();
}
 
/** @}
 */
 

Rev 3742	Rev 3770
1	/*	1	/*
2	* Copyright (c) 2005 Jakub Jermar	2	* Copyright (c) 2005 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	/** @addtogroup sparc64	29	/** @addtogroup sparc64
30	* @{	30	* @{
31	*/	31	*/
32	/** @file	32	/** @file
33	*/	33	*/
34		34
35	#include <arch/drivers/tick.h>	35	#include <arch/drivers/tick.h>
36	#include <arch/interrupt.h>	36	#include <arch/interrupt.h>
37	#include <arch/sparc64.h>	37	#include <arch/sparc64.h>
38	#include <arch/asm.h>	38	#include <arch/asm.h>
39	#include <arch/register.h>	39	#include <arch/register.h>
40	#include <arch/cpu.h>	40	#include <arch/cpu.h>
41	#include <arch/boot/boot.h>	41	#include <arch/boot/boot.h>
42	#include <time/clock.h>	42	#include <time/clock.h>
43	#include <arch.h>	43	#include <arch.h>
44	#include <debug.h>	44	#include <debug.h>
45		45
46	#define TICK_RESTART_TIME 50 /* Worst case estimate. */	46	#define TICK_RESTART_TIME 50 /* Worst case estimate. */
47		47
48	/** Initialize tick and stick interrupt. */	48	/** Initialize tick and stick interrupt. */
49	void tick_init(void)	49	void tick_init(void)
50	{	50	{
51	/* initialize TICK interrupt */	51	/* initialize TICK interrupt */
52	tick_compare_reg_t compare;	52	tick_compare_reg_t compare;
53		53
54	interrupt_register(14, "tick_int", tick_interrupt);	54	interrupt_register(14, "tick_int", tick_interrupt);
55	compare.int_dis = false;	55	compare.int_dis = false;
-		56	compare.tick_cmpr = tick_counter_read() +
56	compare.tick_cmpr = CPU->arch.clock_frequency / HZ;	57	CPU->arch.clock_frequency / HZ;
57	CPU->arch.next_tick_cmpr = compare.tick_cmpr;	58	CPU->arch.next_tick_cmpr = compare.tick_cmpr;
58	tick_compare_write(compare.value);	59	tick_compare_write(compare.value);
59	tick_write(0);	-
60		60
61	#if defined (US3)	61	#if defined (US3)
62	/* disable STICK interrupts and clear any pending ones */	62	/* disable STICK interrupts and clear any pending ones */
63	tick_compare_reg_t stick_compare;	63	tick_compare_reg_t stick_compare;
64	softint_reg_t clear;	64	softint_reg_t clear;
65		65
66	stick_compare.value = stick_compare_read();	66	stick_compare.value = stick_compare_read();
67	stick_compare.int_dis = true;	67	stick_compare.int_dis = true;
68	stick_compare.tick_cmpr = 0;	68	stick_compare.tick_cmpr = 0;
69	stick_compare_write(stick_compare.value);	69	stick_compare_write(stick_compare.value);
70		70
71	clear.value = 0;	71	clear.value = 0;
72	clear.stick_int = 1;	72	clear.stick_int = 1;
73	clear_softint_write(clear.value);	73	clear_softint_write(clear.value);
74	#endif	74	#endif
75	}	75	}
76		76
77	/** Process tick interrupt.	77	/** Process tick interrupt.
78	*	78	*
79	* @param n Interrupt Level, 14, (can be ignored)	79	* @param n Interrupt Level, 14, (can be ignored)
80	* @param istate Interrupted state.	80	* @param istate Interrupted state.
81	*/	81	*/
82	void tick_interrupt(int n, istate_t *istate)	82	void tick_interrupt(int n, istate_t *istate)
83	{	83	{
84	softint_reg_t softint, clear;	84	softint_reg_t softint, clear;
85	uint64_t drift;	85	uint64_t drift;
86		86
87	softint.value = softint_read();	87	softint.value = softint_read();
88		88
89	/*	89	/*
90	* Make sure we are servicing interrupt_level_14	90	* Make sure we are servicing interrupt_level_14
91	*/	91	*/
92	ASSERT(n == 14);	92	ASSERT(n == 14);
93		93
94	/*	94	/*
95	* Make sure we are servicing TICK_INT.	95	* Make sure we are servicing TICK_INT.
96	*/	96	*/
97	ASSERT(softint.tick_int);	97	ASSERT(softint.tick_int);
98		98
99	/*	99	/*
100	* Clear tick interrupt.	100	* Clear tick interrupt.
101	*/	101	*/
102	clear.value = 0;	102	clear.value = 0;
103	clear.tick_int = 1;	103	clear.tick_int = 1;
104	clear_softint_write(clear.value);	104	clear_softint_write(clear.value);
105		105
106	/*	106	/*
107	* Reprogram the compare register.	107	* Reprogram the compare register.
108	* For now, we can ignore the potential of the registers to overflow.	108	* For now, we can ignore the potential of the registers to overflow.
109	* On a 360MHz Ultra 60, the 63-bit compare counter will overflow in	109	* On a 360MHz Ultra 60, the 63-bit compare counter will overflow in
110	* about 812 years. If there was a 2GHz UltraSPARC computer, it would	110	* about 812 years. If there was a 2GHz UltraSPARC computer, it would
111	* overflow only in 146 years.	111	* overflow only in 146 years.
112	*/	112	*/
113	drift = tick_read() - CPU->arch.next_tick_cmpr;	113	drift = tick_counter_read() - CPU->arch.next_tick_cmpr;
114	while (drift > CPU->arch.clock_frequency / HZ) {	114	while (drift > CPU->arch.clock_frequency / HZ) {
115	drift -= CPU->arch.clock_frequency / HZ;	115	drift -= CPU->arch.clock_frequency / HZ;
116	CPU->missed_clock_ticks++;	116	CPU->missed_clock_ticks++;
117	}	117	}
118	CPU->arch.next_tick_cmpr = tick_read() +	118	CPU->arch.next_tick_cmpr = tick_counter_read() +
119	(CPU->arch.clock_frequency / HZ) - drift;	119	(CPU->arch.clock_frequency / HZ) - drift;
120	tick_compare_write(CPU->arch.next_tick_cmpr);	120	tick_compare_write(CPU->arch.next_tick_cmpr);
121	clock();	121	clock();
122	}	122	}
123		123
124	/** @}	124	/** @}
125	*/	125	*/
126		126

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(root)/branches/sparc/kernel/arch/sparc64/src/drivers/tick.c – Rev 3742 → 3770