WebSVN – HelenOS – Diff – /branches/sparc/kernel/arch/sparc64/include/trap/sun4u/mmu.h


/*
 * Copyright (c) 2006 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup sparc64interrupt
 * @{
 */
/**
 * @file
 * @brief This file contains fast MMU trap handlers.
 */
 
#ifndef KERN_sparc64_sun4u_MMU_TRAP_H_
#define KERN_sparc64_sun4u_MMU_TRAP_H_
 
#include <arch/stack.h>
#include <arch/sun4u/regdef.h>
#include <arch/mm/sun4u/tlb.h>
#include <arch/mm/sun4u/tlb.h>
#include <arch/mm/sun4u/mmu.h>
#include <arch/mm/sun4u/tte.h>
#include <arch/trap/regwin.h>
#include <arch/sun4u/arch.h>
 
#ifdef CONFIG_TSB
#include <arch/mm/tsb.h>
#endif
 
#define TT_FAST_INSTRUCTION_ACCESS_MMU_MISS 0x64
#define TT_FAST_DATA_ACCESS_MMU_MISS        0x68
#define TT_FAST_DATA_ACCESS_PROTECTION      0x6c
 
#define FAST_MMU_HANDLER_SIZE           128
 
#ifdef __ASM__
 
.macro FAST_INSTRUCTION_ACCESS_MMU_MISS_HANDLER
    /*
     * First, try to refill TLB from TSB.
     */
#ifdef CONFIG_TSB
    ldxa [%g0] ASI_IMMU, %g1            ! read TSB Tag Target Register
    ldxa [%g0] ASI_IMMU_TSB_8KB_PTR_REG, %g2    ! read TSB 8K Pointer
    ldda [%g2] ASI_NUCLEUS_QUAD_LDD, %g4        ! 16-byte atomic load into %g4 and %g5
    cmp %g1, %g4                    ! is this the entry we are looking for?
    bne,pn %xcc, 0f
    nop
    stxa %g5, [%g0] ASI_ITLB_DATA_IN_REG        ! copy mapping from ITSB to ITLB
    retry
 
#endif
0:
    wrpr %g0, PSTATE_PRIV_BIT | PSTATE_AG_BIT, %pstate
    PREEMPTIBLE_HANDLER fast_instruction_access_mmu_miss
.endm
 
.macro FAST_DATA_ACCESS_MMU_MISS_HANDLER tl
    /*
     * First, try to refill TLB from TSB.
     */
 
#ifdef CONFIG_TSB
    ldxa [%g0] ASI_DMMU, %g1            ! read TSB Tag Target Register
    srlx %g1, TSB_TAG_TARGET_CONTEXT_SHIFT, %g2 ! is this a kernel miss?
    brz,pn %g2, 0f
    ldxa [%g0] ASI_DMMU_TSB_8KB_PTR_REG, %g3    ! read TSB 8K Pointer
    ldda [%g3] ASI_NUCLEUS_QUAD_LDD, %g4        ! 16-byte atomic load into %g4 and %g5
    cmp %g1, %g4                    ! is this the entry we are looking for?
    bne,pn %xcc, 0f
    nop
    stxa %g5, [%g0] ASI_DTLB_DATA_IN_REG        ! copy mapping from DTSB to DTLB
    retry
#endif
 
    /*
     * Second, test if it is the portion of the kernel address space
     * which is faulting. If that is the case, immediately create
     * identity mapping for that page in DTLB. VPN 0 is excluded from
     * this treatment.
     *
     * Note that branch-delay slots are used in order to save space.
     */
0:
    mov VA_DMMU_TAG_ACCESS, %g1
    ldxa [%g1] ASI_DMMU, %g1            ! read the faulting Context and VPN
    set TLB_TAG_ACCESS_CONTEXT_MASK, %g2
    andcc %g1, %g2, %g3             ! get Context
    bnz 0f                      ! Context is non-zero
    andncc %g1, %g2, %g3                ! get page address into %g3
    bz 0f                       ! page address is zero
 
    sethi %hi(kernel_8k_tlb_data_template), %g2
    ldx [%g2 + %lo(kernel_8k_tlb_data_template)], %g2
    or %g3, %g2, %g2
    stxa %g2, [%g0] ASI_DTLB_DATA_IN_REG        ! identity map the kernel page
    retry
 
    /*
     * Third, catch and handle special cases when the trap is caused by
     * the userspace register window spill or fill handler. In case
     * one of these two traps caused this trap, we just lower the trap
     * level and service the DTLB miss. In the end, we restart
     * the offending SAVE or RESTORE.
     */
0:
.if (\tl > 0)
    wrpr %g0, 1, %tl
.endif
 
    /*
     * Switch from the MM globals.
     */
    wrpr %g0, PSTATE_PRIV_BIT | PSTATE_AG_BIT, %pstate
 
    /*
     * Read the Tag Access register for the higher-level handler.
     * This is necessary to survive nested DTLB misses.
     */
    mov VA_DMMU_TAG_ACCESS, %g2
    ldxa [%g2] ASI_DMMU, %g2
 
    /*
     * g2 will be passed as an argument to fast_data_access_mmu_miss().
     */
    PREEMPTIBLE_HANDLER fast_data_access_mmu_miss
.endm
 
.macro FAST_DATA_ACCESS_PROTECTION_HANDLER tl
    /*
     * The same special case as in FAST_DATA_ACCESS_MMU_MISS_HANDLER.
     */
 
.if (\tl > 0)
    wrpr %g0, 1, %tl
.endif
 
    /*
     * Switch from the MM globals.
     */
    wrpr %g0, PSTATE_PRIV_BIT | PSTATE_AG_BIT, %pstate
 
    /*
     * Read the Tag Access register for the higher-level handler.
     * This is necessary to survive nested DTLB misses.
     */
    mov VA_DMMU_TAG_ACCESS, %g2
    ldxa [%g2] ASI_DMMU, %g2
 
    /*
     * g2 will be passed as an argument to fast_data_access_mmu_miss().
     */
    PREEMPTIBLE_HANDLER fast_data_access_protection
.endm
 
#endif /* __ASM__ */
 
#endif
 
/** @}
 */
 

Subversion Repositories HelenOS

(root)/branches/sparc/kernel/arch/sparc64/include/trap/sun4u/mmu.h – Rev 3743 → 3770

Rev 3743		Rev 3770
1	/*	1	/*
2	* Copyright (c) 2006 Jakub Jermar	2	* Copyright (c) 2006 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	/** @addtogroup sparc64interrupt	29	/** @addtogroup sparc64interrupt
30	* @{	30	* @{
31	*/	31	*/
32	/**	32	/**
33	* @file	33	* @file
34	* @brief This file contains fast MMU trap handlers.	34	* @brief This file contains fast MMU trap handlers.
35	*/	35	*/
36		36
37	#ifndef KERN_sparc64_sun4u_MMU_TRAP_H_	37	#ifndef KERN_sparc64_sun4u_MMU_TRAP_H_
38	#define KERN_sparc64_sun4u_MMU_TRAP_H_	38	#define KERN_sparc64_sun4u_MMU_TRAP_H_
39		39
40	#include <arch/stack.h>	40	#include <arch/stack.h>
41	#include <arch/sun4u/regdef.h>	41	#include <arch/sun4u/regdef.h>
42	#include <arch/mm/tlb.h>	42	#include <arch/mm/sun4u/tlb.h>
43	#include <arch/mm/sun4u/tlb.h>	43	#include <arch/mm/sun4u/tlb.h>
44	#include <arch/mm/sun4u/mmu.h>	44	#include <arch/mm/sun4u/mmu.h>
45	#include <arch/mm/sun4u/tte.h>	45	#include <arch/mm/sun4u/tte.h>
46	#include <arch/trap/regwin.h>	46	#include <arch/trap/regwin.h>
47	#include <arch/sun4u/arch.h>	47	#include <arch/sun4u/arch.h>
48		48
49	#ifdef CONFIG_TSB	49	#ifdef CONFIG_TSB
50	#include <arch/mm/tsb.h>	50	#include <arch/mm/tsb.h>
51	#endif	51	#endif
52		52
53	#define TT_FAST_INSTRUCTION_ACCESS_MMU_MISS 0x64	53	#define TT_FAST_INSTRUCTION_ACCESS_MMU_MISS 0x64
54	#define TT_FAST_DATA_ACCESS_MMU_MISS 0x68	54	#define TT_FAST_DATA_ACCESS_MMU_MISS 0x68
55	#define TT_FAST_DATA_ACCESS_PROTECTION 0x6c	55	#define TT_FAST_DATA_ACCESS_PROTECTION 0x6c
56		56
57	#define FAST_MMU_HANDLER_SIZE 128	57	#define FAST_MMU_HANDLER_SIZE 128
58		58
59	#ifdef __ASM__	59	#ifdef __ASM__
60		60
61	.macro FAST_INSTRUCTION_ACCESS_MMU_MISS_HANDLER	61	.macro FAST_INSTRUCTION_ACCESS_MMU_MISS_HANDLER
62	/*	62	/*
63	* First, try to refill TLB from TSB.	63	* First, try to refill TLB from TSB.
64	*/	64	*/
65	#ifdef CONFIG_TSB	65	#ifdef CONFIG_TSB
66	ldxa [%g0] ASI_IMMU, %g1 ! read TSB Tag Target Register	66	ldxa [%g0] ASI_IMMU, %g1 ! read TSB Tag Target Register
67	ldxa [%g0] ASI_IMMU_TSB_8KB_PTR_REG, %g2 ! read TSB 8K Pointer	67	ldxa [%g0] ASI_IMMU_TSB_8KB_PTR_REG, %g2 ! read TSB 8K Pointer
68	ldda [%g2] ASI_NUCLEUS_QUAD_LDD, %g4 ! 16-byte atomic load into %g4 and %g5	68	ldda [%g2] ASI_NUCLEUS_QUAD_LDD, %g4 ! 16-byte atomic load into %g4 and %g5
69	cmp %g1, %g4 ! is this the entry we are looking for?	69	cmp %g1, %g4 ! is this the entry we are looking for?
70	bne,pn %xcc, 0f	70	bne,pn %xcc, 0f
71	nop	71	nop
72	stxa %g5, [%g0] ASI_ITLB_DATA_IN_REG ! copy mapping from ITSB to ITLB	72	stxa %g5, [%g0] ASI_ITLB_DATA_IN_REG ! copy mapping from ITSB to ITLB
73	retry	73	retry
74		74
75	#endif	75	#endif
76	0:	76	0:
77	wrpr %g0, PSTATE_PRIV_BIT \| PSTATE_AG_BIT, %pstate	77	wrpr %g0, PSTATE_PRIV_BIT \| PSTATE_AG_BIT, %pstate
78	PREEMPTIBLE_HANDLER fast_instruction_access_mmu_miss	78	PREEMPTIBLE_HANDLER fast_instruction_access_mmu_miss
79	.endm	79	.endm
80		80
81	.macro FAST_DATA_ACCESS_MMU_MISS_HANDLER tl	81	.macro FAST_DATA_ACCESS_MMU_MISS_HANDLER tl
82	/*	82	/*
83	* First, try to refill TLB from TSB.	83	* First, try to refill TLB from TSB.
84	*/	84	*/
85		85
86	#ifdef CONFIG_TSB	86	#ifdef CONFIG_TSB
87	ldxa [%g0] ASI_DMMU, %g1 ! read TSB Tag Target Register	87	ldxa [%g0] ASI_DMMU, %g1 ! read TSB Tag Target Register
88	srlx %g1, TSB_TAG_TARGET_CONTEXT_SHIFT, %g2 ! is this a kernel miss?	88	srlx %g1, TSB_TAG_TARGET_CONTEXT_SHIFT, %g2 ! is this a kernel miss?
89	brz,pn %g2, 0f	89	brz,pn %g2, 0f
90	ldxa [%g0] ASI_DMMU_TSB_8KB_PTR_REG, %g3 ! read TSB 8K Pointer	90	ldxa [%g0] ASI_DMMU_TSB_8KB_PTR_REG, %g3 ! read TSB 8K Pointer
91	ldda [%g3] ASI_NUCLEUS_QUAD_LDD, %g4 ! 16-byte atomic load into %g4 and %g5	91	ldda [%g3] ASI_NUCLEUS_QUAD_LDD, %g4 ! 16-byte atomic load into %g4 and %g5
92	cmp %g1, %g4 ! is this the entry we are looking for?	92	cmp %g1, %g4 ! is this the entry we are looking for?
93	bne,pn %xcc, 0f	93	bne,pn %xcc, 0f
94	nop	94	nop
95	stxa %g5, [%g0] ASI_DTLB_DATA_IN_REG ! copy mapping from DTSB to DTLB	95	stxa %g5, [%g0] ASI_DTLB_DATA_IN_REG ! copy mapping from DTSB to DTLB
96	retry	96	retry
97	#endif	97	#endif
98		98
99	/*	99	/*
100	* Second, test if it is the portion of the kernel address space	100	* Second, test if it is the portion of the kernel address space
101	* which is faulting. If that is the case, immediately create	101	* which is faulting. If that is the case, immediately create
102	* identity mapping for that page in DTLB. VPN 0 is excluded from	102	* identity mapping for that page in DTLB. VPN 0 is excluded from
103	* this treatment.	103	* this treatment.
104	*	104	*
105	* Note that branch-delay slots are used in order to save space.	105	* Note that branch-delay slots are used in order to save space.
106	*/	106	*/
107	0:	107	0:
108	mov VA_DMMU_TAG_ACCESS, %g1	108	mov VA_DMMU_TAG_ACCESS, %g1
109	ldxa [%g1] ASI_DMMU, %g1 ! read the faulting Context and VPN	109	ldxa [%g1] ASI_DMMU, %g1 ! read the faulting Context and VPN
110	set TLB_TAG_ACCESS_CONTEXT_MASK, %g2	110	set TLB_TAG_ACCESS_CONTEXT_MASK, %g2
111	andcc %g1, %g2, %g3 ! get Context	111	andcc %g1, %g2, %g3 ! get Context
112	bnz 0f ! Context is non-zero	112	bnz 0f ! Context is non-zero
113	andncc %g1, %g2, %g3 ! get page address into %g3	113	andncc %g1, %g2, %g3 ! get page address into %g3
114	bz 0f ! page address is zero	114	bz 0f ! page address is zero
115		115
116	sethi %hi(kernel_8k_tlb_data_template), %g2	116	sethi %hi(kernel_8k_tlb_data_template), %g2
117	ldx [%g2 + %lo(kernel_8k_tlb_data_template)], %g2	117	ldx [%g2 + %lo(kernel_8k_tlb_data_template)], %g2
118	or %g3, %g2, %g2	118	or %g3, %g2, %g2
119	stxa %g2, [%g0] ASI_DTLB_DATA_IN_REG ! identity map the kernel page	119	stxa %g2, [%g0] ASI_DTLB_DATA_IN_REG ! identity map the kernel page
120	retry	120	retry
121		121
122	/*	122	/*
123	* Third, catch and handle special cases when the trap is caused by	123	* Third, catch and handle special cases when the trap is caused by
124	* the userspace register window spill or fill handler. In case	124	* the userspace register window spill or fill handler. In case
125	* one of these two traps caused this trap, we just lower the trap	125	* one of these two traps caused this trap, we just lower the trap
126	* level and service the DTLB miss. In the end, we restart	126	* level and service the DTLB miss. In the end, we restart
127	* the offending SAVE or RESTORE.	127	* the offending SAVE or RESTORE.
128	*/	128	*/
129	0:	129	0:
130	.if (\tl > 0)	130	.if (\tl > 0)
131	wrpr %g0, 1, %tl	131	wrpr %g0, 1, %tl
132	.endif	132	.endif
133		133
134	/*	134	/*
135	* Switch from the MM globals.	135	* Switch from the MM globals.
136	*/	136	*/
137	wrpr %g0, PSTATE_PRIV_BIT \| PSTATE_AG_BIT, %pstate	137	wrpr %g0, PSTATE_PRIV_BIT \| PSTATE_AG_BIT, %pstate
138		138
139	/*	139	/*
140	* Read the Tag Access register for the higher-level handler.	140	* Read the Tag Access register for the higher-level handler.
141	* This is necessary to survive nested DTLB misses.	141	* This is necessary to survive nested DTLB misses.
142	*/	142	*/
143	mov VA_DMMU_TAG_ACCESS, %g2	143	mov VA_DMMU_TAG_ACCESS, %g2
144	ldxa [%g2] ASI_DMMU, %g2	144	ldxa [%g2] ASI_DMMU, %g2
145		145
146	/*	146	/*
147	* g2 will be passed as an argument to fast_data_access_mmu_miss().	147	* g2 will be passed as an argument to fast_data_access_mmu_miss().
148	*/	148	*/
149	PREEMPTIBLE_HANDLER fast_data_access_mmu_miss	149	PREEMPTIBLE_HANDLER fast_data_access_mmu_miss
150	.endm	150	.endm
151		151
152	.macro FAST_DATA_ACCESS_PROTECTION_HANDLER tl	152	.macro FAST_DATA_ACCESS_PROTECTION_HANDLER tl
153	/*	153	/*
154	* The same special case as in FAST_DATA_ACCESS_MMU_MISS_HANDLER.	154	* The same special case as in FAST_DATA_ACCESS_MMU_MISS_HANDLER.
155	*/	155	*/
156		156
157	.if (\tl > 0)	157	.if (\tl > 0)
158	wrpr %g0, 1, %tl	158	wrpr %g0, 1, %tl
159	.endif	159	.endif
160		160
161	/*	161	/*
162	* Switch from the MM globals.	162	* Switch from the MM globals.
163	*/	163	*/
164	wrpr %g0, PSTATE_PRIV_BIT \| PSTATE_AG_BIT, %pstate	164	wrpr %g0, PSTATE_PRIV_BIT \| PSTATE_AG_BIT, %pstate
165		165
166	/*	166	/*
167	* Read the Tag Access register for the higher-level handler.	167	* Read the Tag Access register for the higher-level handler.
168	* This is necessary to survive nested DTLB misses.	168	* This is necessary to survive nested DTLB misses.
169	*/	169	*/
170	mov VA_DMMU_TAG_ACCESS, %g2	170	mov VA_DMMU_TAG_ACCESS, %g2
171	ldxa [%g2] ASI_DMMU, %g2	171	ldxa [%g2] ASI_DMMU, %g2
172		172
173	/*	173	/*
174	* g2 will be passed as an argument to fast_data_access_mmu_miss().	174	* g2 will be passed as an argument to fast_data_access_mmu_miss().
175	*/	175	*/
176	PREEMPTIBLE_HANDLER fast_data_access_protection	176	PREEMPTIBLE_HANDLER fast_data_access_protection
177	.endm	177	.endm
178		178
179	#endif /* __ASM__ */	179	#endif /* __ASM__ */
180		180
181	#endif	181	#endif
182		182
183	/** @}	183	/** @}
184	*/	184	*/
185		185