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135 | 135 | ||
136 | /* |
136 | /* |
137 | * In US3, I-MMU and D-MMU have different formats of the data |
137 | * In US3, I-MMU and D-MMU have different formats of the data |
138 | * access register virtual address. In the corresponding |
138 | * access register virtual address. In the corresponding |
139 | * structures the member variable for the entry number is |
139 | * structures the member variable for the entry number is |
140 | * called "local_tlb_entry" - it contrast with the "tlb_entry" |
140 | * called "local_tlb_entry" - it contrasts with the "tlb_entry" |
141 | * for the US data access register VA structure. The rationale |
141 | * for the US data access register VA structure. The rationale |
142 | * behind this is to prevent careless mistakes in the code |
142 | * behind this is to prevent careless mistakes in the code |
143 | * caused by setting only the entry number and not the TLB |
143 | * caused by setting only the entry number and not the TLB |
144 | * number in the US3 code (when taking the code from US). |
144 | * number in the US3 code (when taking the code from US). |
145 | */ |
145 | */ |
Line 237... | Line 237... | ||
237 | * Functions for determining the number of entries in TLBs. They either return |
237 | * Functions for determining the number of entries in TLBs. They either return |
238 | * a constant value or a value based on the CPU autodetection. |
238 | * a constant value or a value based on the CPU autodetection. |
239 | */ |
239 | */ |
240 | 240 | ||
241 | /** |
241 | /** |
242 | * Determine the number od entries in the DMMU's small TLB. |
242 | * Determine the number of entries in the DMMU's small TLB. |
243 | */ |
243 | */ |
244 | static inline uint16_t tlb_dsmall_size(void) |
244 | static inline uint16_t tlb_dsmall_size(void) |
245 | { |
245 | { |
246 | return 16; |
246 | return 16; |
247 | } |
247 | } |
248 | 248 | ||
249 | /** |
249 | /** |
250 | * Determine the number od entries in each DMMU's big TLB. |
250 | * Determine the number of entries in each DMMU's big TLB. |
251 | */ |
251 | */ |
252 | static inline uint16_t tlb_dbig_size(void) |
252 | static inline uint16_t tlb_dbig_size(void) |
253 | { |
253 | { |
254 | return 512; |
254 | return 512; |
255 | } |
255 | } |
256 | 256 | ||
257 | /** |
257 | /** |
258 | * Determine the number od entries in the IMMU's small TLB. |
258 | * Determine the number of entries in the IMMU's small TLB. |
259 | */ |
259 | */ |
260 | static inline uint16_t tlb_ismall_size(void) |
260 | static inline uint16_t tlb_ismall_size(void) |
261 | { |
261 | { |
262 | return 16; |
262 | return 16; |
263 | } |
263 | } |
264 | 264 | ||
265 | /** |
265 | /** |
266 | * Determine the number od entries in the IMMU's big TLB. |
266 | * Determine the number of entries in the IMMU's big TLB. |
267 | */ |
267 | */ |
268 | static inline uint16_t tlb_ibig_size(void) |
268 | static inline uint16_t tlb_ibig_size(void) |
269 | { |
269 | { |
270 | if (((ver_reg_t) ver_read()).impl == IMPL_ULTRASPARCIV_PLUS) |
270 | if (((ver_reg_t) ver_read()).impl == IMPL_ULTRASPARCIV_PLUS) |
271 | return 512; |
271 | return 512; |
Line 317... | Line 317... | ||
317 | 317 | ||
318 | /** Read IMMU TLB Data Access Register. |
318 | /** Read IMMU TLB Data Access Register. |
319 | * |
319 | * |
320 | * @param entry TLB Entry index. |
320 | * @param entry TLB Entry index. |
321 | * |
321 | * |
322 | * @return Current value of specified IMMU TLB Data Access Register. |
322 | * @return Current value of specified IMMU TLB Data Access |
- | 323 | * Register. |
|
323 | */ |
324 | */ |
324 | static inline uint64_t itlb_data_access_read(index_t entry) |
325 | static inline uint64_t itlb_data_access_read(index_t entry) |
325 | { |
326 | { |
326 | itlb_data_access_addr_t reg; |
327 | itlb_data_access_addr_t reg; |
327 | 328 | ||
Line 347... | Line 348... | ||
347 | 348 | ||
348 | /** Read DMMU TLB Data Access Register. |
349 | /** Read DMMU TLB Data Access Register. |
349 | * |
350 | * |
350 | * @param entry TLB Entry index. |
351 | * @param entry TLB Entry index. |
351 | * |
352 | * |
352 | * @return Current value of specified DMMU TLB Data Access Register. |
353 | * @return Current value of specified DMMU TLB Data Access |
- | 354 | * Register. |
|
353 | */ |
355 | */ |
354 | static inline uint64_t dtlb_data_access_read(index_t entry) |
356 | static inline uint64_t dtlb_data_access_read(index_t entry) |
355 | { |
357 | { |
356 | dtlb_data_access_addr_t reg; |
358 | dtlb_data_access_addr_t reg; |
357 | 359 | ||
Line 411... | Line 413... | ||
411 | /** Read IMMU TLB Data Access Register. |
413 | /** Read IMMU TLB Data Access Register. |
412 | * |
414 | * |
413 | * @param tlb TLB number (one of TLB_ISMALL or TLB_IBIG) |
415 | * @param tlb TLB number (one of TLB_ISMALL or TLB_IBIG) |
414 | * @param entry TLB Entry index. |
416 | * @param entry TLB Entry index. |
415 | * |
417 | * |
416 | * @return Current value of specified IMMU TLB Data Access Register. |
418 | * @return Current value of specified IMMU TLB Data Access |
- | 419 | * Register. |
|
417 | */ |
420 | */ |
418 | static inline uint64_t itlb_data_access_read(int tlb, index_t entry) |
421 | static inline uint64_t itlb_data_access_read(int tlb, index_t entry) |
419 | { |
422 | { |
420 | itlb_data_access_addr_t reg; |
423 | itlb_data_access_addr_t reg; |
421 | 424 | ||
Line 445... | Line 448... | ||
445 | /** Read DMMU TLB Data Access Register. |
448 | /** Read DMMU TLB Data Access Register. |
446 | * |
449 | * |
447 | * @param tlb TLB number (one of TLB_DSMALL, TLB_DBIG, TLB_DBIG) |
450 | * @param tlb TLB number (one of TLB_DSMALL, TLB_DBIG, TLB_DBIG) |
448 | * @param entry TLB Entry index. |
451 | * @param entry TLB Entry index. |
449 | * |
452 | * |
450 | * @return Current value of specified DMMU TLB Data Access Register. |
453 | * @return Current value of specified DMMU TLB Data Access |
- | 454 | * Register. |
|
451 | */ |
455 | */ |
452 | static inline uint64_t dtlb_data_access_read(int tlb, index_t entry) |
456 | static inline uint64_t dtlb_data_access_read(int tlb, index_t entry) |
453 | { |
457 | { |
454 | dtlb_data_access_addr_t reg; |
458 | dtlb_data_access_addr_t reg; |
455 | 459 | ||
Line 620... | Line 624... | ||
620 | return asi_u64_read(ASI_DMMU, VA_DMMU_SFAR); |
624 | return asi_u64_read(ASI_DMMU, VA_DMMU_SFAR); |
621 | } |
625 | } |
622 | 626 | ||
623 | /** Perform IMMU TLB Demap Operation. |
627 | /** Perform IMMU TLB Demap Operation. |
624 | * |
628 | * |
625 | * @param type |
- | |
626 | * Selects between context and page demap |
629 | * @param type Selects between context and page demap (and entire MMU |
627 | * (and entire MMU demap on US3). |
630 | * demap on US3). |
628 | * @param context_encoding Specifies which Context register has Context ID for |
631 | * @param context_encoding Specifies which Context register has Context ID for |
629 | * demap. |
632 | * demap. |
630 | * @param page Address which is on the page to be demapped. |
633 | * @param page Address which is on the page to be demapped. |
631 | */ |
634 | */ |
632 | static inline void itlb_demap(int type, int context_encoding, uintptr_t page) |
635 | static inline void itlb_demap(int type, int context_encoding, uintptr_t page) |
Line 639... | Line 642... | ||
639 | 642 | ||
640 | da.type = type; |
643 | da.type = type; |
641 | da.context = context_encoding; |
644 | da.context = context_encoding; |
642 | da.vpn = pg.vpn; |
645 | da.vpn = pg.vpn; |
643 | 646 | ||
644 | asi_u64_write(ASI_IMMU_DEMAP, da.value, 0); /* da.value is the |
- | |
645 | * address within the |
647 | /* da.value is the address within the ASI */ |
646 | * ASI */ |
648 | asi_u64_write(ASI_IMMU_DEMAP, da.value, 0); |
- | 649 | ||
647 | flush_pipeline(); |
650 | flush_pipeline(); |
648 | } |
651 | } |
649 | 652 | ||
650 | /** Perform DMMU TLB Demap Operation. |
653 | /** Perform DMMU TLB Demap Operation. |
651 | * |
654 | * |
652 | * @param type |
- | |
653 | * Selects between context and page demap |
655 | * @param type Selects between context and page demap (and entire MMU |
654 | * (and entire MMU demap on US3). |
656 | * demap on US3). |
655 | * @param context_encoding Specifies which Context register has Context ID for |
657 | * @param context_encoding Specifies which Context register has Context ID for |
656 | * demap. |
658 | * demap. |
657 | * @param page Address which is on the page to be demapped. |
659 | * @param page Address which is on the page to be demapped. |
658 | */ |
660 | */ |
659 | static inline void dtlb_demap(int type, int context_encoding, uintptr_t page) |
661 | static inline void dtlb_demap(int type, int context_encoding, uintptr_t page) |
Line 666... | Line 668... | ||
666 | 668 | ||
667 | da.type = type; |
669 | da.type = type; |
668 | da.context = context_encoding; |
670 | da.context = context_encoding; |
669 | da.vpn = pg.vpn; |
671 | da.vpn = pg.vpn; |
670 | 672 | ||
671 | asi_u64_write(ASI_DMMU_DEMAP, da.value, 0); /* da.value is the |
- | |
672 | * address within the |
673 | /* da.value is the address within the ASI */ |
673 | * ASI */ |
674 | asi_u64_write(ASI_DMMU_DEMAP, da.value, 0); |
- | 675 | ||
674 | membar(); |
676 | membar(); |
675 | } |
677 | } |
676 | 678 | ||
677 | extern void fast_instruction_access_mmu_miss(unative_t unused, istate_t *istate); |
679 | extern void fast_instruction_access_mmu_miss(unative_t, istate_t *); |
678 | extern void fast_data_access_mmu_miss(tlb_tag_access_reg_t tag, istate_t *istate); |
680 | extern void fast_data_access_mmu_miss(tlb_tag_access_reg_t, istate_t *); |
679 | extern void fast_data_access_protection(tlb_tag_access_reg_t tag , istate_t *istate); |
681 | extern void fast_data_access_protection(tlb_tag_access_reg_t , istate_t *); |
680 | 682 | ||
681 | extern void dtlb_insert_mapping(uintptr_t page, uintptr_t frame, int pagesize, bool locked, bool cacheable); |
683 | extern void dtlb_insert_mapping(uintptr_t, uintptr_t, int, bool, bool); |
682 | 684 | ||
683 | extern void dump_sfsr_and_sfar(void); |
685 | extern void dump_sfsr_and_sfar(void); |
684 | 686 | ||
685 | #endif /* !def __ASM__ */ |
687 | #endif /* !def __ASM__ */ |
686 | 688 |