WebSVN – HelenOS – Diff – /branches/sparc/kernel/arch/sparc64/include/mm/tlb.h


/*
 * Copyright (c) 2005 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup sparc64mm  
 * @{
 */
/** @file
 */
 
#ifndef KERN_sparc64_TLB_H_
#define KERN_sparc64_TLB_H_
 
#if defined (US)
#define ITLB_ENTRY_COUNT        64
#define DTLB_ENTRY_COUNT        64
#define DTLB_MAX_LOCKED_ENTRIES     DTLB_ENTRY_COUNT
#endif
 
/** TLB_DSMALL is the only of the three DMMUs that can hold locked entries. */
#if defined (US3)
#define DTLB_MAX_LOCKED_ENTRIES     16
#endif
 
#define MEM_CONTEXT_KERNEL      0
#define MEM_CONTEXT_TEMP        1
 
/** Page sizes. */
#define PAGESIZE_8K 0
#define PAGESIZE_64K    1
#define PAGESIZE_512K   2
#define PAGESIZE_4M 3
 
/** Bit width of the TLB-locked portion of kernel address space. */
#define KERNEL_PAGE_WIDTH       22  /* 4M */
 
/* TLB Demap Operation types. */
#define TLB_DEMAP_PAGE      0
#define TLB_DEMAP_CONTEXT   1
#if defined (US3)
#define TLB_DEMAP_ALL       2
#endif
 
#define TLB_DEMAP_TYPE_SHIFT    6
 
/* TLB Demap Operation Context register encodings. */
#define TLB_DEMAP_PRIMARY   0
#define TLB_DEMAP_SECONDARY 1
#define TLB_DEMAP_NUCLEUS   2
 
/* There are more TLBs in one MMU in US3, their codes are defined here. */
#if defined (US3)
/* D-MMU: one small (16-entry) TLB and two big (512-entry) TLBs */
#define TLB_DSMALL  0
#define TLB_DBIG_0  2
#define TLB_DBIG_1  3
   
/* I-MMU: one small (16-entry) TLB and one big TLB */
#define TLB_ISMALL  0
#define TLB_IBIG    2
#endif
 
#define TLB_DEMAP_CONTEXT_SHIFT 4
 
/* TLB Tag Access shifts */
#define TLB_TAG_ACCESS_CONTEXT_SHIFT    0
#define TLB_TAG_ACCESS_CONTEXT_MASK ((1 << 13) - 1)
#define TLB_TAG_ACCESS_VPN_SHIFT    13
 
#ifndef __ASM__
 
#include <arch/mm/tte.h>
#include <arch/mm/mmu.h>
#include <arch/mm/page.h>
#include <arch/asm.h>
#include <arch/barrier.h>
#include <arch/types.h>
#include <arch/register.h>
#include <arch/cpu.h>
 
union tlb_context_reg {
    uint64_t v;
    struct {
        unsigned long : 51;
        unsigned context : 13;      /**< Context/ASID. */
    } __attribute__ ((packed));
};
typedef union tlb_context_reg tlb_context_reg_t;
 
/** I-/D-TLB Data In/Access Register type. */
typedef tte_data_t tlb_data_t;
 
/** I-/D-TLB Data Access Address in Alternate Space. */
 
#if defined (US)
 
union tlb_data_access_addr {
    uint64_t value;
    struct {
        uint64_t : 55;
        unsigned tlb_entry : 6;
        unsigned : 3;
    } __attribute__ ((packed));
};
typedef union tlb_data_access_addr dtlb_data_access_addr_t;
typedef union tlb_data_access_addr dtlb_tag_read_addr_t;
typedef union tlb_data_access_addr itlb_data_access_addr_t;
typedef union tlb_data_access_addr itlb_tag_read_addr_t;
 
#elif defined (US3)
 
/*
 * In US3, I-MMU and D-MMU have different formats of the data
 * access register virtual address. In the corresponding
 * structures the member variable for the entry number is
 * called "local_tlb_entry" - it contrasts with the "tlb_entry"
 * for the US data access register VA structure. The rationale
 * behind this is to prevent careless mistakes in the code
 * caused by setting only the entry number and not the TLB
 * number in the US3 code (when taking the code from US).
 */
 
union dtlb_data_access_addr {
    uint64_t value;
    struct {
        uint64_t : 45;
        unsigned : 1;
        unsigned tlb_number : 2;
        unsigned : 4;
        unsigned local_tlb_entry : 9;
        unsigned : 3;
    } __attribute__ ((packed));
};
typedef union dtlb_data_access_addr dtlb_data_access_addr_t;
typedef union dtlb_data_access_addr dtlb_tag_read_addr_t;
 
union itlb_data_access_addr {
    uint64_t value;
    struct {
        uint64_t : 45;
        unsigned : 1;
        unsigned tlb_number : 2;
        unsigned : 6;
        unsigned local_tlb_entry : 7;
        unsigned : 3;
    } __attribute__ ((packed));
};
typedef union itlb_data_access_addr itlb_data_access_addr_t;
typedef union itlb_data_access_addr itlb_tag_read_addr_t;
 
#endif
 
/** I-/D-TLB Tag Read Register. */
union tlb_tag_read_reg {
    uint64_t value;
    struct {
        uint64_t vpn : 51;  /**< Virtual Address bits 63:13. */
        unsigned context : 13;  /**< Context identifier. */
    } __attribute__ ((packed));
};
typedef union tlb_tag_read_reg tlb_tag_read_reg_t;
typedef union tlb_tag_read_reg tlb_tag_access_reg_t;
 
 
/** TLB Demap Operation Address. */
union tlb_demap_addr {
    uint64_t value;
    struct {
        uint64_t vpn: 51;   /**< Virtual Address bits 63:13. */
#if defined (US)
        unsigned : 6;       /**< Ignored. */
        unsigned type : 1;  /**< The type of demap operation. */
#elif defined (US3)
        unsigned : 5;       /**< Ignored. */
        unsigned type: 2;   /**< The type of demap operation. */
#endif
        unsigned context : 2;   /**< Context register selection. */
        unsigned : 4;       /**< Zero. */
    } __attribute__ ((packed));
};
typedef union tlb_demap_addr tlb_demap_addr_t;
 
/** TLB Synchronous Fault Status Register. */
union tlb_sfsr_reg {
    uint64_t value;
    struct {
#if defined (US)
        unsigned long : 40; /**< Implementation dependent. */
        unsigned asi : 8;   /**< ASI. */
        unsigned : 2;
        unsigned ft : 7;    /**< Fault type. */
#elif defined (US3)
        unsigned long : 39; /**< Implementation dependent. */
        unsigned nf : 1;    /**< Non-faulting load. */
        unsigned asi : 8;   /**< ASI. */
        unsigned tm : 1;    /**< I-TLB miss. */
        unsigned : 3;       /**< Reserved. */
        unsigned ft : 5;    /**< Fault type. */
#endif
        unsigned e : 1;     /**< Side-effect bit. */
        unsigned ct : 2;    /**< Context Register selection. */
        unsigned pr : 1;    /**< Privilege bit. */
        unsigned w : 1;     /**< Write bit. */
        unsigned ow : 1;    /**< Overwrite bit. */
        unsigned fv : 1;    /**< Fault Valid bit. */
    } __attribute__ ((packed));
};
typedef union tlb_sfsr_reg tlb_sfsr_reg_t;
 
#if defined (US3)
 
/*
 * Functions for determining the number of entries in TLBs. They either return
 * a constant value or a value based on the CPU autodetection.
 */
 
/**
 * Determine the number of entries in the DMMU's small TLB.
 */
static inline uint16_t tlb_dsmall_size(void)
{
    return 16;
}
 
/**
 * Determine the number of entries in each DMMU's big TLB.
 */
static inline uint16_t tlb_dbig_size(void)
{
    return 512;
}
 
/**
 * Determine the number of entries in the IMMU's small TLB.
 */
static inline uint16_t tlb_ismall_size(void)
{
    return 16;
}
 
/**
 * Determine the number of entries in the IMMU's big TLB.
 */
static inline uint16_t tlb_ibig_size(void)
{
    if (((ver_reg_t) ver_read()).impl == IMPL_ULTRASPARCIV_PLUS)
        return 512;
    else
        return 128;
}
 
#endif
 
/** Read MMU Primary Context Register.
 *
 * @return      Current value of Primary Context Register.
 */
static inline uint64_t mmu_primary_context_read(void)
{
    return asi_u64_read(ASI_DMMU, VA_PRIMARY_CONTEXT_REG);
}
 
/** Write MMU Primary Context Register.
 *
 * @param v     New value of Primary Context Register.
 */
static inline void mmu_primary_context_write(uint64_t v)
{
    asi_u64_write(ASI_DMMU, VA_PRIMARY_CONTEXT_REG, v);
    flush_pipeline();
}
 
/** Read MMU Secondary Context Register.
 *
 * @return      Current value of Secondary Context Register.
 */
static inline uint64_t mmu_secondary_context_read(void)
{
    return asi_u64_read(ASI_DMMU, VA_SECONDARY_CONTEXT_REG);
}
 
/** Write MMU Primary Context Register.
 *
 * @param v     New value of Primary Context Register.
 */
static inline void mmu_secondary_context_write(uint64_t v)
{
    asi_u64_write(ASI_DMMU, VA_SECONDARY_CONTEXT_REG, v);
    flush_pipeline();
}
 
#if defined (US)
 
/** Read IMMU TLB Data Access Register.
 *
 * @param entry     TLB Entry index.
 *
 * @return      Current value of specified IMMU TLB Data Access
 *          Register.
 */
static inline uint64_t itlb_data_access_read(index_t entry)
{
    itlb_data_access_addr_t reg;
   
    reg.value = 0;
    reg.tlb_entry = entry;
    return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value);
}
 
/** Write IMMU TLB Data Access Register.
 *
 * @param entry     TLB Entry index.
 * @param value     Value to be written.
 */
static inline void itlb_data_access_write(index_t entry, uint64_t value)
{
    itlb_data_access_addr_t reg;
   
    reg.value = 0;
    reg.tlb_entry = entry;
    asi_u64_write(ASI_ITLB_DATA_ACCESS_REG, reg.value, value);
    flush_pipeline();
}
 
/** Read DMMU TLB Data Access Register.
 *
 * @param entry     TLB Entry index.
 *
 * @return      Current value of specified DMMU TLB Data Access
 *          Register.
 */
static inline uint64_t dtlb_data_access_read(index_t entry)
{
    dtlb_data_access_addr_t reg;
   
    reg.value = 0;
    reg.tlb_entry = entry;
    return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value);
}
 
/** Write DMMU TLB Data Access Register.
 *
 * @param entry     TLB Entry index.
 * @param value     Value to be written.
 */
static inline void dtlb_data_access_write(index_t entry, uint64_t value)
{
    dtlb_data_access_addr_t reg;
   
    reg.value = 0;
    reg.tlb_entry = entry;
    asi_u64_write(ASI_DTLB_DATA_ACCESS_REG, reg.value, value);
    membar();
}
 
/** Read IMMU TLB Tag Read Register.
 *
 * @param entry     TLB Entry index.
 *
 * @return      Current value of specified IMMU TLB Tag Read Register.
 */
static inline uint64_t itlb_tag_read_read(index_t entry)
{
    itlb_tag_read_addr_t tag;
 
    tag.value = 0;
    tag.tlb_entry = entry;
    return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value);
}
 
/** Read DMMU TLB Tag Read Register.
 *
 * @param entry     TLB Entry index.
 *
 * @return      Current value of specified DMMU TLB Tag Read Register.
 */
static inline uint64_t dtlb_tag_read_read(index_t entry)
{
    dtlb_tag_read_addr_t tag;
 
    tag.value = 0;
    tag.tlb_entry = entry;
    return asi_u64_read(ASI_DTLB_TAG_READ_REG, tag.value);
}
 
#elif defined (US3)
 
 
/** Read IMMU TLB Data Access Register.
 *
 * @param tlb       TLB number (one of TLB_ISMALL or TLB_IBIG)
 * @param entry     TLB Entry index.
 *
 * @return      Current value of specified IMMU TLB Data Access
 *          Register.
 */
static inline uint64_t itlb_data_access_read(int tlb, index_t entry)
{
    itlb_data_access_addr_t reg;
   
    reg.value = 0;
    reg.tlb_number = tlb;
    reg.local_tlb_entry = entry;
    return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value);
}
 
/** Write IMMU TLB Data Access Register.
 * @param tlb       TLB number (one of TLB_ISMALL or TLB_IBIG)
 * @param entry     TLB Entry index.
 * @param value     Value to be written.
 */
static inline void itlb_data_access_write(int tlb, index_t entry,
    uint64_t value)
{
    itlb_data_access_addr_t reg;
   
    reg.value = 0;
    reg.tlb_number = tlb;
    reg.local_tlb_entry = entry;
    asi_u64_write(ASI_ITLB_DATA_ACCESS_REG, reg.value, value);
    flush_pipeline();
}
 
/** Read DMMU TLB Data Access Register.
 *
 * @param tlb       TLB number (one of TLB_DSMALL, TLB_DBIG, TLB_DBIG)
 * @param entry     TLB Entry index.
 *
 * @return      Current value of specified DMMU TLB Data Access
 *          Register.
 */
static inline uint64_t dtlb_data_access_read(int tlb, index_t entry)
{
    dtlb_data_access_addr_t reg;
   
    reg.value = 0;
    reg.tlb_number = tlb;
    reg.local_tlb_entry = entry;
    return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value);
}
 
/** Write DMMU TLB Data Access Register.
 *
 * @param tlb       TLB number (one of TLB_DSMALL, TLB_DBIG_0, TLB_DBIG_1)  
 * @param entry     TLB Entry index.
 * @param value     Value to be written.
 */
static inline void dtlb_data_access_write(int tlb, index_t entry,
    uint64_t value)
{
    dtlb_data_access_addr_t reg;
   
    reg.value = 0;
    reg.tlb_number = tlb;
    reg.local_tlb_entry = entry;
    asi_u64_write(ASI_DTLB_DATA_ACCESS_REG, reg.value, value);
    membar();
}
 
/** Read IMMU TLB Tag Read Register.
 *
 * @param tlb       TLB number (one of TLB_ISMALL or TLB_IBIG)
 * @param entry     TLB Entry index.
 *
 * @return      Current value of specified IMMU TLB Tag Read Register.
 */
static inline uint64_t itlb_tag_read_read(int tlb, index_t entry)
{
    itlb_tag_read_addr_t tag;
 
    tag.value = 0;
    tag.tlb_number = tlb;
    tag.local_tlb_entry = entry;
    return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value);
}
 
/** Read DMMU TLB Tag Read Register.
 *
 * @param tlb       TLB number (one of TLB_DSMALL, TLB_DBIG_0, TLB_DBIG_1)
 * @param entry     TLB Entry index.
 *
 * @return      Current value of specified DMMU TLB Tag Read Register.
 */
static inline uint64_t dtlb_tag_read_read(int tlb, index_t entry)
{
    dtlb_tag_read_addr_t tag;
 
    tag.value = 0;
    tag.tlb_number = tlb;
    tag.local_tlb_entry = entry;
    return asi_u64_read(ASI_DTLB_TAG_READ_REG, tag.value);
}
 
#endif
 
 
/** Write IMMU TLB Tag Access Register.
 *
 * @param v     Value to be written.
 */
static inline void itlb_tag_access_write(uint64_t v)
{
    asi_u64_write(ASI_IMMU, VA_IMMU_TAG_ACCESS, v);
    flush_pipeline();
}
 
/** Read IMMU TLB Tag Access Register.
 *
 * @return      Current value of IMMU TLB Tag Access Register.
 */
static inline uint64_t itlb_tag_access_read(void)
{
    return asi_u64_read(ASI_IMMU, VA_IMMU_TAG_ACCESS);
}
 
/** Write DMMU TLB Tag Access Register.
 *
 * @param v     Value to be written.
 */
static inline void dtlb_tag_access_write(uint64_t v)
{
    asi_u64_write(ASI_DMMU, VA_DMMU_TAG_ACCESS, v);
    membar();
}
 
/** Read DMMU TLB Tag Access Register.
 *
 * @return      Current value of DMMU TLB Tag Access Register.
 */
static inline uint64_t dtlb_tag_access_read(void)
{
    return asi_u64_read(ASI_DMMU, VA_DMMU_TAG_ACCESS);
}
 
 
/** Write IMMU TLB Data in Register.
 *
 * @param v     Value to be written.
 */
static inline void itlb_data_in_write(uint64_t v)
{
    asi_u64_write(ASI_ITLB_DATA_IN_REG, 0, v);
    flush_pipeline();
}
 
/** Write DMMU TLB Data in Register.
 *
 * @param v     Value to be written.
 */
static inline void dtlb_data_in_write(uint64_t v)
{
    asi_u64_write(ASI_DTLB_DATA_IN_REG, 0, v);
    membar();
}
 
/** Read ITLB Synchronous Fault Status Register.
 *
 * @return      Current content of I-SFSR register.
 */
static inline uint64_t itlb_sfsr_read(void)
{
    return asi_u64_read(ASI_IMMU, VA_IMMU_SFSR);
}
 
/** Write ITLB Synchronous Fault Status Register.
 *
 * @param v     New value of I-SFSR register.
 */
static inline void itlb_sfsr_write(uint64_t v)
{
    asi_u64_write(ASI_IMMU, VA_IMMU_SFSR, v);
    flush_pipeline();
}
 
/** Read DTLB Synchronous Fault Status Register.
 *
 * @return      Current content of D-SFSR register.
 */
static inline uint64_t dtlb_sfsr_read(void)
{
    return asi_u64_read(ASI_DMMU, VA_DMMU_SFSR);
}
 
/** Write DTLB Synchronous Fault Status Register.
 *
 * @param v     New value of D-SFSR register.
 */
static inline void dtlb_sfsr_write(uint64_t v)
{
    asi_u64_write(ASI_DMMU, VA_DMMU_SFSR, v);
    membar();
}
 
/** Read DTLB Synchronous Fault Address Register.
 *
 * @return      Current content of D-SFAR register.
 */
static inline uint64_t dtlb_sfar_read(void)
{
    return asi_u64_read(ASI_DMMU, VA_DMMU_SFAR);
}
 
/** Perform IMMU TLB Demap Operation.
 *
 
 * @param type      Selects between context and page demap (and entire MMU
 *          demap on US3).
 * @param context_encoding Specifies which Context register has Context ID for
 *          demap.
 * @param page      Address which is on the page to be demapped.
 */
static inline void itlb_demap(int type, int context_encoding, uintptr_t page)
{
    tlb_demap_addr_t da;
    page_address_t pg;
   
    da.value = 0;
    pg.address = page;
   
    da.type = type;
    da.context = context_encoding;
    da.vpn = pg.vpn;
   
 
    /* da.value is the address within the ASI */
    asi_u64_write(ASI_IMMU_DEMAP, da.value, 0);
 
    flush_pipeline();
}
 
/** Perform DMMU TLB Demap Operation.
 *
 
 * @param type      Selects between context and page demap (and entire MMU
 *          demap on US3).
 * @param context_encoding Specifies which Context register has Context ID for
 *          demap.
 * @param page      Address which is on the page to be demapped.
 */
static inline void dtlb_demap(int type, int context_encoding, uintptr_t page)
{
    tlb_demap_addr_t da;
    page_address_t pg;
   
    da.value = 0;
    pg.address = page;
   
    da.type = type;
    da.context = context_encoding;
    da.vpn = pg.vpn;
   
 
    /* da.value is the address within the ASI */
    asi_u64_write(ASI_DMMU_DEMAP, da.value, 0);
 
    membar();
}
 
extern void fast_instruction_access_mmu_miss(unative_t, istate_t *);
extern void fast_data_access_mmu_miss(tlb_tag_access_reg_t, istate_t *);
extern void fast_data_access_protection(tlb_tag_access_reg_t , istate_t *);
 
extern void dtlb_insert_mapping(uintptr_t, uintptr_t, int, bool, bool);
 
extern void dump_sfsr_and_sfar(void);
 
#endif /* !def __ASM__ */
 
#endif
 
/** @}
 */
 

Rev 3618	Rev 3742
1	/*	1	/*
2	* Copyright (c) 2005 Jakub Jermar	2	* Copyright (c) 2005 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	/** @addtogroup sparc64mm	29	/** @addtogroup sparc64mm
30	* @{	30	* @{
31	*/	31	*/
32	/** @file	32	/** @file
33	*/	33	*/
34		34
35	#ifndef KERN_sparc64_TLB_H_	35	#ifndef KERN_sparc64_TLB_H_
36	#define KERN_sparc64_TLB_H_	36	#define KERN_sparc64_TLB_H_
37		37
38	#if defined (US)	38	#if defined (US)
39	#define ITLB_ENTRY_COUNT 64	39	#define ITLB_ENTRY_COUNT 64
40	#define DTLB_ENTRY_COUNT 64	40	#define DTLB_ENTRY_COUNT 64
41	#define DTLB_MAX_LOCKED_ENTRIES DTLB_ENTRY_COUNT	41	#define DTLB_MAX_LOCKED_ENTRIES DTLB_ENTRY_COUNT
42	#endif	42	#endif
43		43
44	/** TLB_DSMALL is the only of the three DMMUs that can hold locked entries. */	44	/** TLB_DSMALL is the only of the three DMMUs that can hold locked entries. */
45	#if defined (US3)	45	#if defined (US3)
46	#define DTLB_MAX_LOCKED_ENTRIES 16	46	#define DTLB_MAX_LOCKED_ENTRIES 16
47	#endif	47	#endif
48		48
49	#define MEM_CONTEXT_KERNEL 0	49	#define MEM_CONTEXT_KERNEL 0
50	#define MEM_CONTEXT_TEMP 1	50	#define MEM_CONTEXT_TEMP 1
51		51
52	/** Page sizes. */	52	/** Page sizes. */
53	#define PAGESIZE_8K 0	53	#define PAGESIZE_8K 0
54	#define PAGESIZE_64K 1	54	#define PAGESIZE_64K 1
55	#define PAGESIZE_512K 2	55	#define PAGESIZE_512K 2
56	#define PAGESIZE_4M 3	56	#define PAGESIZE_4M 3
57		57
58	/** Bit width of the TLB-locked portion of kernel address space. */	58	/** Bit width of the TLB-locked portion of kernel address space. */
59	#define KERNEL_PAGE_WIDTH 22 /* 4M */	59	#define KERNEL_PAGE_WIDTH 22 /* 4M */
60		60
61	/* TLB Demap Operation types. */	61	/* TLB Demap Operation types. */
62	#define TLB_DEMAP_PAGE 0	62	#define TLB_DEMAP_PAGE 0
63	#define TLB_DEMAP_CONTEXT 1	63	#define TLB_DEMAP_CONTEXT 1
64	#if defined (US3)	64	#if defined (US3)
65	#define TLB_DEMAP_ALL 2	65	#define TLB_DEMAP_ALL 2
66	#endif	66	#endif
67		67
68	#define TLB_DEMAP_TYPE_SHIFT 6	68	#define TLB_DEMAP_TYPE_SHIFT 6
69		69
70	/* TLB Demap Operation Context register encodings. */	70	/* TLB Demap Operation Context register encodings. */
71	#define TLB_DEMAP_PRIMARY 0	71	#define TLB_DEMAP_PRIMARY 0
72	#define TLB_DEMAP_SECONDARY 1	72	#define TLB_DEMAP_SECONDARY 1
73	#define TLB_DEMAP_NUCLEUS 2	73	#define TLB_DEMAP_NUCLEUS 2
74		74
75	/* There are more TLBs in one MMU in US3, their codes are defined here. */	75	/* There are more TLBs in one MMU in US3, their codes are defined here. */
76	#if defined (US3)	76	#if defined (US3)
77	/* D-MMU: one small (16-entry) TLB and two big (512-entry) TLBs */	77	/* D-MMU: one small (16-entry) TLB and two big (512-entry) TLBs */
78	#define TLB_DSMALL 0	78	#define TLB_DSMALL 0
79	#define TLB_DBIG_0 2	79	#define TLB_DBIG_0 2
80	#define TLB_DBIG_1 3	80	#define TLB_DBIG_1 3
81		81
82	/* I-MMU: one small (16-entry) TLB and one big TLB */	82	/* I-MMU: one small (16-entry) TLB and one big TLB */
83	#define TLB_ISMALL 0	83	#define TLB_ISMALL 0
84	#define TLB_IBIG 2	84	#define TLB_IBIG 2
85	#endif	85	#endif
86		86
87	#define TLB_DEMAP_CONTEXT_SHIFT 4	87	#define TLB_DEMAP_CONTEXT_SHIFT 4
88		88
89	/* TLB Tag Access shifts */	89	/* TLB Tag Access shifts */
90	#define TLB_TAG_ACCESS_CONTEXT_SHIFT 0	90	#define TLB_TAG_ACCESS_CONTEXT_SHIFT 0
91	#define TLB_TAG_ACCESS_CONTEXT_MASK ((1 << 13) - 1)	91	#define TLB_TAG_ACCESS_CONTEXT_MASK ((1 << 13) - 1)
92	#define TLB_TAG_ACCESS_VPN_SHIFT 13	92	#define TLB_TAG_ACCESS_VPN_SHIFT 13
93		93
94	#ifndef __ASM__	94	#ifndef __ASM__
95		95
96	#include <arch/mm/tte.h>	96	#include <arch/mm/tte.h>
97	#include <arch/mm/mmu.h>	97	#include <arch/mm/mmu.h>
98	#include <arch/mm/page.h>	98	#include <arch/mm/page.h>
99	#include <arch/asm.h>	99	#include <arch/asm.h>
100	#include <arch/barrier.h>	100	#include <arch/barrier.h>
101	#include <arch/types.h>	101	#include <arch/types.h>
102	#include <arch/register.h>	102	#include <arch/register.h>
103	#include <arch/cpu.h>	103	#include <arch/cpu.h>
104		104
105	union tlb_context_reg {	105	union tlb_context_reg {
106	uint64_t v;	106	uint64_t v;
107	struct {	107	struct {
108	unsigned long : 51;	108	unsigned long : 51;
109	unsigned context : 13; /*< Context/ASID. /	109	unsigned context : 13; /*< Context/ASID. /
110	} __attribute__ ((packed));	110	} __attribute__ ((packed));
111	};	111	};
112	typedef union tlb_context_reg tlb_context_reg_t;	112	typedef union tlb_context_reg tlb_context_reg_t;
113		113
114	/** I-/D-TLB Data In/Access Register type. */	114	/** I-/D-TLB Data In/Access Register type. */
115	typedef tte_data_t tlb_data_t;	115	typedef tte_data_t tlb_data_t;
116		116
117	/** I-/D-TLB Data Access Address in Alternate Space. */	117	/** I-/D-TLB Data Access Address in Alternate Space. */
118		118
119	#if defined (US)	119	#if defined (US)
120		120
121	union tlb_data_access_addr {	121	union tlb_data_access_addr {
122	uint64_t value;	122	uint64_t value;
123	struct {	123	struct {
124	uint64_t : 55;	124	uint64_t : 55;
125	unsigned tlb_entry : 6;	125	unsigned tlb_entry : 6;
126	unsigned : 3;	126	unsigned : 3;
127	} __attribute__ ((packed));	127	} __attribute__ ((packed));
128	};	128	};
129	typedef union tlb_data_access_addr dtlb_data_access_addr_t;	129	typedef union tlb_data_access_addr dtlb_data_access_addr_t;
130	typedef union tlb_data_access_addr dtlb_tag_read_addr_t;	130	typedef union tlb_data_access_addr dtlb_tag_read_addr_t;
131	typedef union tlb_data_access_addr itlb_data_access_addr_t;	131	typedef union tlb_data_access_addr itlb_data_access_addr_t;
132	typedef union tlb_data_access_addr itlb_tag_read_addr_t;	132	typedef union tlb_data_access_addr itlb_tag_read_addr_t;
133		133
134	#elif defined (US3)	134	#elif defined (US3)
135		135
136	/*	136	/*
137	* In US3, I-MMU and D-MMU have different formats of the data	137	* In US3, I-MMU and D-MMU have different formats of the data
138	* access register virtual address. In the corresponding	138	* access register virtual address. In the corresponding
139	* structures the member variable for the entry number is	139	* structures the member variable for the entry number is
140	* called "local_tlb_entry" - it contrast with the "tlb_entry"	140	* called "local_tlb_entry" - it contrasts with the "tlb_entry"
141	* for the US data access register VA structure. The rationale	141	* for the US data access register VA structure. The rationale
142	* behind this is to prevent careless mistakes in the code	142	* behind this is to prevent careless mistakes in the code
143	* caused by setting only the entry number and not the TLB	143	* caused by setting only the entry number and not the TLB
144	* number in the US3 code (when taking the code from US).	144	* number in the US3 code (when taking the code from US).
145	*/	145	*/
146		146
147	union dtlb_data_access_addr {	147	union dtlb_data_access_addr {
148	uint64_t value;	148	uint64_t value;
149	struct {	149	struct {
150	uint64_t : 45;	150	uint64_t : 45;
151	unsigned : 1;	151	unsigned : 1;
152	unsigned tlb_number : 2;	152	unsigned tlb_number : 2;
153	unsigned : 4;	153	unsigned : 4;
154	unsigned local_tlb_entry : 9;	154	unsigned local_tlb_entry : 9;
155	unsigned : 3;	155	unsigned : 3;
156	} __attribute__ ((packed));	156	} __attribute__ ((packed));
157	};	157	};
158	typedef union dtlb_data_access_addr dtlb_data_access_addr_t;	158	typedef union dtlb_data_access_addr dtlb_data_access_addr_t;
159	typedef union dtlb_data_access_addr dtlb_tag_read_addr_t;	159	typedef union dtlb_data_access_addr dtlb_tag_read_addr_t;
160		160
161	union itlb_data_access_addr {	161	union itlb_data_access_addr {
162	uint64_t value;	162	uint64_t value;
163	struct {	163	struct {
164	uint64_t : 45;	164	uint64_t : 45;
165	unsigned : 1;	165	unsigned : 1;
166	unsigned tlb_number : 2;	166	unsigned tlb_number : 2;
167	unsigned : 6;	167	unsigned : 6;
168	unsigned local_tlb_entry : 7;	168	unsigned local_tlb_entry : 7;
169	unsigned : 3;	169	unsigned : 3;
170	} __attribute__ ((packed));	170	} __attribute__ ((packed));
171	};	171	};
172	typedef union itlb_data_access_addr itlb_data_access_addr_t;	172	typedef union itlb_data_access_addr itlb_data_access_addr_t;
173	typedef union itlb_data_access_addr itlb_tag_read_addr_t;	173	typedef union itlb_data_access_addr itlb_tag_read_addr_t;
174		174
175	#endif	175	#endif
176		176
177	/** I-/D-TLB Tag Read Register. */	177	/** I-/D-TLB Tag Read Register. */
178	union tlb_tag_read_reg {	178	union tlb_tag_read_reg {
179	uint64_t value;	179	uint64_t value;
180	struct {	180	struct {
181	uint64_t vpn : 51; /*< Virtual Address bits 63:13. /	181	uint64_t vpn : 51; /*< Virtual Address bits 63:13. /
182	unsigned context : 13; /*< Context identifier. /	182	unsigned context : 13; /*< Context identifier. /
183	} __attribute__ ((packed));	183	} __attribute__ ((packed));
184	};	184	};
185	typedef union tlb_tag_read_reg tlb_tag_read_reg_t;	185	typedef union tlb_tag_read_reg tlb_tag_read_reg_t;
186	typedef union tlb_tag_read_reg tlb_tag_access_reg_t;	186	typedef union tlb_tag_read_reg tlb_tag_access_reg_t;
187		187
188		188
189	/** TLB Demap Operation Address. */	189	/** TLB Demap Operation Address. */
190	union tlb_demap_addr {	190	union tlb_demap_addr {
191	uint64_t value;	191	uint64_t value;
192	struct {	192	struct {
193	uint64_t vpn: 51; /*< Virtual Address bits 63:13. /	193	uint64_t vpn: 51; /*< Virtual Address bits 63:13. /
194	#if defined (US)	194	#if defined (US)
195	unsigned : 6; /*< Ignored. /	195	unsigned : 6; /*< Ignored. /
196	unsigned type : 1; /*< The type of demap operation. /	196	unsigned type : 1; /*< The type of demap operation. /
197	#elif defined (US3)	197	#elif defined (US3)
198	unsigned : 5; /*< Ignored. /	198	unsigned : 5; /*< Ignored. /
199	unsigned type: 2; /*< The type of demap operation. /	199	unsigned type: 2; /*< The type of demap operation. /
200	#endif	200	#endif
201	unsigned context : 2; /*< Context register selection. /	201	unsigned context : 2; /*< Context register selection. /
202	unsigned : 4; /*< Zero. /	202	unsigned : 4; /*< Zero. /
203	} __attribute__ ((packed));	203	} __attribute__ ((packed));
204	};	204	};
205	typedef union tlb_demap_addr tlb_demap_addr_t;	205	typedef union tlb_demap_addr tlb_demap_addr_t;
206		206
207	/** TLB Synchronous Fault Status Register. */	207	/** TLB Synchronous Fault Status Register. */
208	union tlb_sfsr_reg {	208	union tlb_sfsr_reg {
209	uint64_t value;	209	uint64_t value;
210	struct {	210	struct {
211	#if defined (US)	211	#if defined (US)
212	unsigned long : 40; /*< Implementation dependent. /	212	unsigned long : 40; /*< Implementation dependent. /
213	unsigned asi : 8; /*< ASI. /	213	unsigned asi : 8; /*< ASI. /
214	unsigned : 2;	214	unsigned : 2;
215	unsigned ft : 7; /*< Fault type. /	215	unsigned ft : 7; /*< Fault type. /
216	#elif defined (US3)	216	#elif defined (US3)
217	unsigned long : 39; /*< Implementation dependent. /	217	unsigned long : 39; /*< Implementation dependent. /
218	unsigned nf : 1; /*< Non-faulting load. /	218	unsigned nf : 1; /*< Non-faulting load. /
219	unsigned asi : 8; /*< ASI. /	219	unsigned asi : 8; /*< ASI. /
220	unsigned tm : 1; /*< I-TLB miss. /	220	unsigned tm : 1; /*< I-TLB miss. /
221	unsigned : 3; /*< Reserved. /	221	unsigned : 3; /*< Reserved. /
222	unsigned ft : 5; /*< Fault type. /	222	unsigned ft : 5; /*< Fault type. /
223	#endif	223	#endif
224	unsigned e : 1; /*< Side-effect bit. /	224	unsigned e : 1; /*< Side-effect bit. /
225	unsigned ct : 2; /*< Context Register selection. /	225	unsigned ct : 2; /*< Context Register selection. /
226	unsigned pr : 1; /*< Privilege bit. /	226	unsigned pr : 1; /*< Privilege bit. /
227	unsigned w : 1; /*< Write bit. /	227	unsigned w : 1; /*< Write bit. /
228	unsigned ow : 1; /*< Overwrite bit. /	228	unsigned ow : 1; /*< Overwrite bit. /
229	unsigned fv : 1; /*< Fault Valid bit. /	229	unsigned fv : 1; /*< Fault Valid bit. /
230	} __attribute__ ((packed));	230	} __attribute__ ((packed));
231	};	231	};
232	typedef union tlb_sfsr_reg tlb_sfsr_reg_t;	232	typedef union tlb_sfsr_reg tlb_sfsr_reg_t;
233		233
234	#if defined (US3)	234	#if defined (US3)
235		235
236	/*	236	/*
237	* Functions for determining the number of entries in TLBs. They either return	237	* Functions for determining the number of entries in TLBs. They either return
238	* a constant value or a value based on the CPU autodetection.	238	* a constant value or a value based on the CPU autodetection.
239	*/	239	*/
240		240
241	/**	241	/**
242	* Determine the number od entries in the DMMU's small TLB.	242	* Determine the number of entries in the DMMU's small TLB.
243	*/	243	*/
244	static inline uint16_t tlb_dsmall_size(void)	244	static inline uint16_t tlb_dsmall_size(void)
245	{	245	{
246	return 16;	246	return 16;
247	}	247	}
248		248
249	/**	249	/**
250	* Determine the number od entries in each DMMU's big TLB.	250	* Determine the number of entries in each DMMU's big TLB.
251	*/	251	*/
252	static inline uint16_t tlb_dbig_size(void)	252	static inline uint16_t tlb_dbig_size(void)
253	{	253	{
254	return 512;	254	return 512;
255	}	255	}
256		256
257	/**	257	/**
258	* Determine the number od entries in the IMMU's small TLB.	258	* Determine the number of entries in the IMMU's small TLB.
259	*/	259	*/
260	static inline uint16_t tlb_ismall_size(void)	260	static inline uint16_t tlb_ismall_size(void)
261	{	261	{
262	return 16;	262	return 16;
263	}	263	}
264		264
265	/**	265	/**
266	* Determine the number od entries in the IMMU's big TLB.	266	* Determine the number of entries in the IMMU's big TLB.
267	*/	267	*/
268	static inline uint16_t tlb_ibig_size(void)	268	static inline uint16_t tlb_ibig_size(void)
269	{	269	{
270	if (((ver_reg_t) ver_read()).impl == IMPL_ULTRASPARCIV_PLUS)	270	if (((ver_reg_t) ver_read()).impl == IMPL_ULTRASPARCIV_PLUS)
271	return 512;	271	return 512;
272	else	272	else
273	return 128;	273	return 128;
274	}	274	}
275		275
276	#endif	276	#endif
277		277
278	/** Read MMU Primary Context Register.	278	/** Read MMU Primary Context Register.
279	*	279	*
280	* @return Current value of Primary Context Register.	280	* @return Current value of Primary Context Register.
281	*/	281	*/
282	static inline uint64_t mmu_primary_context_read(void)	282	static inline uint64_t mmu_primary_context_read(void)
283	{	283	{
284	return asi_u64_read(ASI_DMMU, VA_PRIMARY_CONTEXT_REG);	284	return asi_u64_read(ASI_DMMU, VA_PRIMARY_CONTEXT_REG);
285	}	285	}
286		286
287	/** Write MMU Primary Context Register.	287	/** Write MMU Primary Context Register.
288	*	288	*
289	* @param v New value of Primary Context Register.	289	* @param v New value of Primary Context Register.
290	*/	290	*/
291	static inline void mmu_primary_context_write(uint64_t v)	291	static inline void mmu_primary_context_write(uint64_t v)
292	{	292	{
293	asi_u64_write(ASI_DMMU, VA_PRIMARY_CONTEXT_REG, v);	293	asi_u64_write(ASI_DMMU, VA_PRIMARY_CONTEXT_REG, v);
294	flush_pipeline();	294	flush_pipeline();
295	}	295	}
296		296
297	/** Read MMU Secondary Context Register.	297	/** Read MMU Secondary Context Register.
298	*	298	*
299	* @return Current value of Secondary Context Register.	299	* @return Current value of Secondary Context Register.
300	*/	300	*/
301	static inline uint64_t mmu_secondary_context_read(void)	301	static inline uint64_t mmu_secondary_context_read(void)
302	{	302	{
303	return asi_u64_read(ASI_DMMU, VA_SECONDARY_CONTEXT_REG);	303	return asi_u64_read(ASI_DMMU, VA_SECONDARY_CONTEXT_REG);
304	}	304	}
305		305
306	/** Write MMU Primary Context Register.	306	/** Write MMU Primary Context Register.
307	*	307	*
308	* @param v New value of Primary Context Register.	308	* @param v New value of Primary Context Register.
309	*/	309	*/
310	static inline void mmu_secondary_context_write(uint64_t v)	310	static inline void mmu_secondary_context_write(uint64_t v)
311	{	311	{
312	asi_u64_write(ASI_DMMU, VA_SECONDARY_CONTEXT_REG, v);	312	asi_u64_write(ASI_DMMU, VA_SECONDARY_CONTEXT_REG, v);
313	flush_pipeline();	313	flush_pipeline();
314	}	314	}
315		315
316	#if defined (US)	316	#if defined (US)
317		317
318	/** Read IMMU TLB Data Access Register.	318	/** Read IMMU TLB Data Access Register.
319	*	319	*
320	* @param entry TLB Entry index.	320	* @param entry TLB Entry index.
321	*	321	*
322	* @return Current value of specified IMMU TLB Data Access Register.	322	* @return Current value of specified IMMU TLB Data Access
-		323	* Register.
323	*/	324	*/
324	static inline uint64_t itlb_data_access_read(index_t entry)	325	static inline uint64_t itlb_data_access_read(index_t entry)
325	{	326	{
326	itlb_data_access_addr_t reg;	327	itlb_data_access_addr_t reg;
327		328
328	reg.value = 0;	329	reg.value = 0;
329	reg.tlb_entry = entry;	330	reg.tlb_entry = entry;
330	return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value);	331	return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value);
331	}	332	}
332		333
333	/** Write IMMU TLB Data Access Register.	334	/** Write IMMU TLB Data Access Register.
334	*	335	*
335	* @param entry TLB Entry index.	336	* @param entry TLB Entry index.
336	* @param value Value to be written.	337	* @param value Value to be written.
337	*/	338	*/
338	static inline void itlb_data_access_write(index_t entry, uint64_t value)	339	static inline void itlb_data_access_write(index_t entry, uint64_t value)
339	{	340	{
340	itlb_data_access_addr_t reg;	341	itlb_data_access_addr_t reg;
341		342
342	reg.value = 0;	343	reg.value = 0;
343	reg.tlb_entry = entry;	344	reg.tlb_entry = entry;
344	asi_u64_write(ASI_ITLB_DATA_ACCESS_REG, reg.value, value);	345	asi_u64_write(ASI_ITLB_DATA_ACCESS_REG, reg.value, value);
345	flush_pipeline();	346	flush_pipeline();
346	}	347	}
347		348
348	/** Read DMMU TLB Data Access Register.	349	/** Read DMMU TLB Data Access Register.
349	*	350	*
350	* @param entry TLB Entry index.	351	* @param entry TLB Entry index.
351	*	352	*
352	* @return Current value of specified DMMU TLB Data Access Register.	353	* @return Current value of specified DMMU TLB Data Access
-		354	* Register.
353	*/	355	*/
354	static inline uint64_t dtlb_data_access_read(index_t entry)	356	static inline uint64_t dtlb_data_access_read(index_t entry)
355	{	357	{
356	dtlb_data_access_addr_t reg;	358	dtlb_data_access_addr_t reg;
357		359
358	reg.value = 0;	360	reg.value = 0;
359	reg.tlb_entry = entry;	361	reg.tlb_entry = entry;
360	return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value);	362	return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value);
361	}	363	}
362		364
363	/** Write DMMU TLB Data Access Register.	365	/** Write DMMU TLB Data Access Register.
364	*	366	*
365	* @param entry TLB Entry index.	367	* @param entry TLB Entry index.
366	* @param value Value to be written.	368	* @param value Value to be written.
367	*/	369	*/
368	static inline void dtlb_data_access_write(index_t entry, uint64_t value)	370	static inline void dtlb_data_access_write(index_t entry, uint64_t value)
369	{	371	{
370	dtlb_data_access_addr_t reg;	372	dtlb_data_access_addr_t reg;
371		373
372	reg.value = 0;	374	reg.value = 0;
373	reg.tlb_entry = entry;	375	reg.tlb_entry = entry;
374	asi_u64_write(ASI_DTLB_DATA_ACCESS_REG, reg.value, value);	376	asi_u64_write(ASI_DTLB_DATA_ACCESS_REG, reg.value, value);
375	membar();	377	membar();
376	}	378	}
377		379
378	/** Read IMMU TLB Tag Read Register.	380	/** Read IMMU TLB Tag Read Register.
379	*	381	*
380	* @param entry TLB Entry index.	382	* @param entry TLB Entry index.
381	*	383	*
382	* @return Current value of specified IMMU TLB Tag Read Register.	384	* @return Current value of specified IMMU TLB Tag Read Register.
383	*/	385	*/
384	static inline uint64_t itlb_tag_read_read(index_t entry)	386	static inline uint64_t itlb_tag_read_read(index_t entry)
385	{	387	{
386	itlb_tag_read_addr_t tag;	388	itlb_tag_read_addr_t tag;
387		389
388	tag.value = 0;	390	tag.value = 0;
389	tag.tlb_entry = entry;	391	tag.tlb_entry = entry;
390	return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value);	392	return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value);
391	}	393	}
392		394
393	/** Read DMMU TLB Tag Read Register.	395	/** Read DMMU TLB Tag Read Register.
394	*	396	*
395	* @param entry TLB Entry index.	397	* @param entry TLB Entry index.
396	*	398	*
397	* @return Current value of specified DMMU TLB Tag Read Register.	399	* @return Current value of specified DMMU TLB Tag Read Register.
398	*/	400	*/
399	static inline uint64_t dtlb_tag_read_read(index_t entry)	401	static inline uint64_t dtlb_tag_read_read(index_t entry)
400	{	402	{
401	dtlb_tag_read_addr_t tag;	403	dtlb_tag_read_addr_t tag;
402		404
403	tag.value = 0;	405	tag.value = 0;
404	tag.tlb_entry = entry;	406	tag.tlb_entry = entry;
405	return asi_u64_read(ASI_DTLB_TAG_READ_REG, tag.value);	407	return asi_u64_read(ASI_DTLB_TAG_READ_REG, tag.value);
406	}	408	}
407		409
408	#elif defined (US3)	410	#elif defined (US3)
409		411
410		412
411	/** Read IMMU TLB Data Access Register.	413	/** Read IMMU TLB Data Access Register.
412	*	414	*
413	* @param tlb TLB number (one of TLB_ISMALL or TLB_IBIG)	415	* @param tlb TLB number (one of TLB_ISMALL or TLB_IBIG)
414	* @param entry TLB Entry index.	416	* @param entry TLB Entry index.
415	*	417	*
416	* @return Current value of specified IMMU TLB Data Access Register.	418	* @return Current value of specified IMMU TLB Data Access
-		419	* Register.
417	*/	420	*/
418	static inline uint64_t itlb_data_access_read(int tlb, index_t entry)	421	static inline uint64_t itlb_data_access_read(int tlb, index_t entry)
419	{	422	{
420	itlb_data_access_addr_t reg;	423	itlb_data_access_addr_t reg;
421		424
422	reg.value = 0;	425	reg.value = 0;
423	reg.tlb_number = tlb;	426	reg.tlb_number = tlb;
424	reg.local_tlb_entry = entry;	427	reg.local_tlb_entry = entry;
425	return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value);	428	return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value);
426	}	429	}
427		430
428	/** Write IMMU TLB Data Access Register.	431	/** Write IMMU TLB Data Access Register.
429	* @param tlb TLB number (one of TLB_ISMALL or TLB_IBIG)	432	* @param tlb TLB number (one of TLB_ISMALL or TLB_IBIG)
430	* @param entry TLB Entry index.	433	* @param entry TLB Entry index.
431	* @param value Value to be written.	434	* @param value Value to be written.
432	*/	435	*/
433	static inline void itlb_data_access_write(int tlb, index_t entry,	436	static inline void itlb_data_access_write(int tlb, index_t entry,
434	uint64_t value)	437	uint64_t value)
435	{	438	{
436	itlb_data_access_addr_t reg;	439	itlb_data_access_addr_t reg;
437		440
438	reg.value = 0;	441	reg.value = 0;
439	reg.tlb_number = tlb;	442	reg.tlb_number = tlb;
440	reg.local_tlb_entry = entry;	443	reg.local_tlb_entry = entry;
441	asi_u64_write(ASI_ITLB_DATA_ACCESS_REG, reg.value, value);	444	asi_u64_write(ASI_ITLB_DATA_ACCESS_REG, reg.value, value);
442	flush_pipeline();	445	flush_pipeline();
443	}	446	}
444		447
445	/** Read DMMU TLB Data Access Register.	448	/** Read DMMU TLB Data Access Register.
446	*	449	*
447	* @param tlb TLB number (one of TLB_DSMALL, TLB_DBIG, TLB_DBIG)	450	* @param tlb TLB number (one of TLB_DSMALL, TLB_DBIG, TLB_DBIG)
448	* @param entry TLB Entry index.	451	* @param entry TLB Entry index.
449	*	452	*
450	* @return Current value of specified DMMU TLB Data Access Register.	453	* @return Current value of specified DMMU TLB Data Access
-		454	* Register.
451	*/	455	*/
452	static inline uint64_t dtlb_data_access_read(int tlb, index_t entry)	456	static inline uint64_t dtlb_data_access_read(int tlb, index_t entry)
453	{	457	{
454	dtlb_data_access_addr_t reg;	458	dtlb_data_access_addr_t reg;
455		459
456	reg.value = 0;	460	reg.value = 0;
457	reg.tlb_number = tlb;	461	reg.tlb_number = tlb;
458	reg.local_tlb_entry = entry;	462	reg.local_tlb_entry = entry;
459	return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value);	463	return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value);
460	}	464	}
461		465
462	/** Write DMMU TLB Data Access Register.	466	/** Write DMMU TLB Data Access Register.
463	*	467	*
464	* @param tlb TLB number (one of TLB_DSMALL, TLB_DBIG_0, TLB_DBIG_1)	468	* @param tlb TLB number (one of TLB_DSMALL, TLB_DBIG_0, TLB_DBIG_1)
465	* @param entry TLB Entry index.	469	* @param entry TLB Entry index.
466	* @param value Value to be written.	470	* @param value Value to be written.
467	*/	471	*/
468	static inline void dtlb_data_access_write(int tlb, index_t entry,	472	static inline void dtlb_data_access_write(int tlb, index_t entry,
469	uint64_t value)	473	uint64_t value)
470	{	474	{
471	dtlb_data_access_addr_t reg;	475	dtlb_data_access_addr_t reg;
472		476
473	reg.value = 0;	477	reg.value = 0;
474	reg.tlb_number = tlb;	478	reg.tlb_number = tlb;
475	reg.local_tlb_entry = entry;	479	reg.local_tlb_entry = entry;
476	asi_u64_write(ASI_DTLB_DATA_ACCESS_REG, reg.value, value);	480	asi_u64_write(ASI_DTLB_DATA_ACCESS_REG, reg.value, value);
477	membar();	481	membar();
478	}	482	}
479		483
480	/** Read IMMU TLB Tag Read Register.	484	/** Read IMMU TLB Tag Read Register.
481	*	485	*
482	* @param tlb TLB number (one of TLB_ISMALL or TLB_IBIG)	486	* @param tlb TLB number (one of TLB_ISMALL or TLB_IBIG)
483	* @param entry TLB Entry index.	487	* @param entry TLB Entry index.
484	*	488	*
485	* @return Current value of specified IMMU TLB Tag Read Register.	489	* @return Current value of specified IMMU TLB Tag Read Register.
486	*/	490	*/
487	static inline uint64_t itlb_tag_read_read(int tlb, index_t entry)	491	static inline uint64_t itlb_tag_read_read(int tlb, index_t entry)
488	{	492	{
489	itlb_tag_read_addr_t tag;	493	itlb_tag_read_addr_t tag;
490		494
491	tag.value = 0;	495	tag.value = 0;
492	tag.tlb_number = tlb;	496	tag.tlb_number = tlb;
493	tag.local_tlb_entry = entry;	497	tag.local_tlb_entry = entry;
494	return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value);	498	return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value);
495	}	499	}
496		500

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(root)/branches/sparc/kernel/arch/sparc64/include/mm/tlb.h – Rev 3618 → 3742