WebSVN – HelenOS – Diff – /branches/sparc/kernel/arch/sparc64/include/mm/tlb.h



 
/*
 * In US3, I-MMU and D-MMU have different formats of the data
 * access register virtual address. In the corresponding
 * structures the member variable for the entry number is
 * called "local_tlb_entry" - it contrasts with the "tlb_entry"
 * for the US data access register VA structure. The rationale
 * behind this is to prevent careless mistakes in the code
 * caused by setting only the entry number and not the TLB
 * number in the US3 code (when taking the code from US).
 */

 * Functions for determining the number of entries in TLBs. They either return
 * a constant value or a value based on the CPU autodetection.
 */
 
/**
 * Determine the number of entries in the DMMU's small TLB.
 */
static inline uint16_t tlb_dsmall_size(void)
{
    return 16;
}
 
/**
 * Determine the number of entries in each DMMU's big TLB.
 */
static inline uint16_t tlb_dbig_size(void)
{
    return 512;
}
 
/**
 * Determine the number of entries in the IMMU's small TLB.
 */
static inline uint16_t tlb_ismall_size(void)
{
    return 16;
}
 
/**
 * Determine the number of entries in the IMMU's big TLB.
 */
static inline uint16_t tlb_ibig_size(void)
{
    if (((ver_reg_t) ver_read()).impl == IMPL_ULTRASPARCIV_PLUS)
        return 512;

 
#endif
 
/** Read MMU Primary Context Register.
 *
 * @return      Current value of Primary Context Register.
 */
static inline uint64_t mmu_primary_context_read(void)
{
    return asi_u64_read(ASI_DMMU, VA_PRIMARY_CONTEXT_REG);
}
 
/** Write MMU Primary Context Register.
 *
 * @param v     New value of Primary Context Register.
 */
static inline void mmu_primary_context_write(uint64_t v)
{
    asi_u64_write(ASI_DMMU, VA_PRIMARY_CONTEXT_REG, v);
    flush_pipeline();
}
 
/** Read MMU Secondary Context Register.
 *
 * @return      Current value of Secondary Context Register.
 */
static inline uint64_t mmu_secondary_context_read(void)
{
    return asi_u64_read(ASI_DMMU, VA_SECONDARY_CONTEXT_REG);
}
 
/** Write MMU Primary Context Register.
 *
 * @param v     New value of Primary Context Register.
 */
static inline void mmu_secondary_context_write(uint64_t v)
{
    asi_u64_write(ASI_DMMU, VA_SECONDARY_CONTEXT_REG, v);
    flush_pipeline();

 
#if defined (US)
 
/** Read IMMU TLB Data Access Register.
 *
 * @param entry     TLB Entry index.
 *
 * @return      Current value of specified IMMU TLB Data Access
 *          Register.
 */
static inline uint64_t itlb_data_access_read(index_t entry)
{
    itlb_data_access_addr_t reg;
   

    return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value);
}
 
/** Write IMMU TLB Data Access Register.
 *
 * @param entry     TLB Entry index.
 * @param value     Value to be written.
 */
static inline void itlb_data_access_write(index_t entry, uint64_t value)
{
    itlb_data_access_addr_t reg;
   

    flush_pipeline();
}
 
/** Read DMMU TLB Data Access Register.
 *
 * @param entry     TLB Entry index.
 *
 * @return      Current value of specified DMMU TLB Data Access
 *          Register.
 */
static inline uint64_t dtlb_data_access_read(index_t entry)
{
    dtlb_data_access_addr_t reg;
   

    return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value);
}
 
/** Write DMMU TLB Data Access Register.
 *
 * @param entry     TLB Entry index.
 * @param value     Value to be written.
 */
static inline void dtlb_data_access_write(index_t entry, uint64_t value)
{
    dtlb_data_access_addr_t reg;
   

    membar();
}
 
/** Read IMMU TLB Tag Read Register.
 *
 * @param entry     TLB Entry index.
 *
 * @return      Current value of specified IMMU TLB Tag Read Register.
 */
static inline uint64_t itlb_tag_read_read(index_t entry)
{
    itlb_tag_read_addr_t tag;
 

    return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value);
}
 
/** Read DMMU TLB Tag Read Register.
 *
 * @param entry     TLB Entry index.
 *
 * @return      Current value of specified DMMU TLB Tag Read Register.
 */
static inline uint64_t dtlb_tag_read_read(index_t entry)
{
    dtlb_tag_read_addr_t tag;
 

#elif defined (US3)
 
 
/** Read IMMU TLB Data Access Register.
 *
 * @param tlb       TLB number (one of TLB_ISMALL or TLB_IBIG)
 * @param entry     TLB Entry index.
 *
 * @return      Current value of specified IMMU TLB Data Access
 *          Register.
 */
static inline uint64_t itlb_data_access_read(int tlb, index_t entry)
{
    itlb_data_access_addr_t reg;
   

    reg.local_tlb_entry = entry;
    return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value);
}
 
/** Write IMMU TLB Data Access Register.
 * @param tlb       TLB number (one of TLB_ISMALL or TLB_IBIG)
 * @param entry     TLB Entry index.
 * @param value     Value to be written.
 */
static inline void itlb_data_access_write(int tlb, index_t entry,
    uint64_t value)
{
    itlb_data_access_addr_t reg;

    flush_pipeline();
}
 
/** Read DMMU TLB Data Access Register.
 *
 * @param tlb       TLB number (one of TLB_DSMALL, TLB_DBIG, TLB_DBIG)
 * @param entry     TLB Entry index.
 *
 * @return      Current value of specified DMMU TLB Data Access
 *          Register.
 */
static inline uint64_t dtlb_data_access_read(int tlb, index_t entry)
{
    dtlb_data_access_addr_t reg;
   

    return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value);
}
 
/** Write DMMU TLB Data Access Register.
 *
 * @param tlb       TLB number (one of TLB_DSMALL, TLB_DBIG_0, TLB_DBIG_1)  
 * @param entry     TLB Entry index.
 * @param value     Value to be written.
 */
static inline void dtlb_data_access_write(int tlb, index_t entry,
    uint64_t value)
{
    dtlb_data_access_addr_t reg;

    membar();
}
 
/** Read IMMU TLB Tag Read Register.
 *
 * @param tlb       TLB number (one of TLB_ISMALL or TLB_IBIG)
 * @param entry     TLB Entry index.
 *
 * @return      Current value of specified IMMU TLB Tag Read Register.
 */
static inline uint64_t itlb_tag_read_read(int tlb, index_t entry)
{
    itlb_tag_read_addr_t tag;
 

    return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value);
}
 
/** Read DMMU TLB Tag Read Register.
 *
 * @param tlb       TLB number (one of TLB_DSMALL, TLB_DBIG_0, TLB_DBIG_1)
 * @param entry     TLB Entry index.
 *
 * @return      Current value of specified DMMU TLB Tag Read Register.
 */
static inline uint64_t dtlb_tag_read_read(int tlb, index_t entry)
{
    dtlb_tag_read_addr_t tag;
 

#endif
 
 
/** Write IMMU TLB Tag Access Register.
 *
 * @param v     Value to be written.
 */
static inline void itlb_tag_access_write(uint64_t v)
{
    asi_u64_write(ASI_IMMU, VA_IMMU_TAG_ACCESS, v);
    flush_pipeline();
}
 
/** Read IMMU TLB Tag Access Register.
 *
 * @return      Current value of IMMU TLB Tag Access Register.
 */
static inline uint64_t itlb_tag_access_read(void)
{
    return asi_u64_read(ASI_IMMU, VA_IMMU_TAG_ACCESS);
}
 
/** Write DMMU TLB Tag Access Register.
 *
 * @param v     Value to be written.
 */
static inline void dtlb_tag_access_write(uint64_t v)
{
    asi_u64_write(ASI_DMMU, VA_DMMU_TAG_ACCESS, v);
    membar();
}
 
/** Read DMMU TLB Tag Access Register.
 *
 * @return      Current value of DMMU TLB Tag Access Register.
 */
static inline uint64_t dtlb_tag_access_read(void)
{
    return asi_u64_read(ASI_DMMU, VA_DMMU_TAG_ACCESS);
}
 
 
/** Write IMMU TLB Data in Register.
 *
 * @param v     Value to be written.
 */
static inline void itlb_data_in_write(uint64_t v)
{
    asi_u64_write(ASI_ITLB_DATA_IN_REG, 0, v);
    flush_pipeline();
}
 
/** Write DMMU TLB Data in Register.
 *
 * @param v     Value to be written.
 */
static inline void dtlb_data_in_write(uint64_t v)
{
    asi_u64_write(ASI_DTLB_DATA_IN_REG, 0, v);
    membar();
}
 
/** Read ITLB Synchronous Fault Status Register.
 *
 * @return      Current content of I-SFSR register.
 */
static inline uint64_t itlb_sfsr_read(void)
{
    return asi_u64_read(ASI_IMMU, VA_IMMU_SFSR);
}
 
/** Write ITLB Synchronous Fault Status Register.
 *
 * @param v     New value of I-SFSR register.
 */
static inline void itlb_sfsr_write(uint64_t v)
{
    asi_u64_write(ASI_IMMU, VA_IMMU_SFSR, v);
    flush_pipeline();
}
 
/** Read DTLB Synchronous Fault Status Register.
 *
 * @return      Current content of D-SFSR register.
 */
static inline uint64_t dtlb_sfsr_read(void)
{
    return asi_u64_read(ASI_DMMU, VA_DMMU_SFSR);
}
 
/** Write DTLB Synchronous Fault Status Register.
 *
 * @param v     New value of D-SFSR register.
 */
static inline void dtlb_sfsr_write(uint64_t v)
{
    asi_u64_write(ASI_DMMU, VA_DMMU_SFSR, v);
    membar();
}
 
/** Read DTLB Synchronous Fault Address Register.
 *
 * @return      Current content of D-SFAR register.
 */
static inline uint64_t dtlb_sfar_read(void)
{
    return asi_u64_read(ASI_DMMU, VA_DMMU_SFAR);
}
 
/** Perform IMMU TLB Demap Operation.
 *
 
 * @param type      Selects between context and page demap (and entire MMU
 *          demap on US3).
 * @param context_encoding Specifies which Context register has Context ID for
 *          demap.
 * @param page      Address which is on the page to be demapped.
 */
static inline void itlb_demap(int type, int context_encoding, uintptr_t page)
{
    tlb_demap_addr_t da;
    page_address_t pg;

   
    da.type = type;
    da.context = context_encoding;
    da.vpn = pg.vpn;
   
 
    /* da.value is the address within the ASI */
    asi_u64_write(ASI_IMMU_DEMAP, da.value, 0);
 
    flush_pipeline();
}
 
/** Perform DMMU TLB Demap Operation.
 *
 
 * @param type      Selects between context and page demap (and entire MMU
 *          demap on US3).
 * @param context_encoding Specifies which Context register has Context ID for
 *          demap.
 * @param page      Address which is on the page to be demapped.
 */
static inline void dtlb_demap(int type, int context_encoding, uintptr_t page)
{
    tlb_demap_addr_t da;
    page_address_t pg;

   
    da.type = type;
    da.context = context_encoding;
    da.vpn = pg.vpn;
   
 
    /* da.value is the address within the ASI */
    asi_u64_write(ASI_DMMU_DEMAP, da.value, 0);
 
    membar();
}
 
extern void fast_instruction_access_mmu_miss(unative_t, istate_t *);
extern void fast_data_access_mmu_miss(tlb_tag_access_reg_t, istate_t *);
extern void fast_data_access_protection(tlb_tag_access_reg_t , istate_t *);
 
extern void dtlb_insert_mapping(uintptr_t, uintptr_t, int, bool, bool);
 
extern void dump_sfsr_and_sfar(void);
 
#endif /* !def __ASM__ */
 
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(root)/branches/sparc/kernel/arch/sparc64/include/mm/tlb.h – Rev 3618 → 3742
