WebSVN – HelenOS – Diff – /branches/sparc/kernel/arch/sparc64/include/mm/tlb.h

 #define ITLB_ENTRY_COUNT        64
 #define DTLB_ENTRY_COUNT        64
 #define DTLB_MAX_LOCKED_ENTRIES     DTLB_ENTRY_COUNT
 #endif
-/** DT16 is the only of the three DMMUs that can hold locked entries. */
+/** TLB_DSMALL is the only of the three DMMUs that can hold locked entries. */
 #if defined (US3)
 #define DTLB_MAX_LOCKED_ENTRIES     16
 #endif
 #define MEM_CONTEXT_KERNEL      0
 #define TLB_DEMAP_SECONDARY 1
 #define TLB_DEMAP_NUCLEUS   2
 /* There are more TLBs in one MMU in US3, their codes are defined here. */
 #if defined (US3)
-/* D-MMU: one 16-entry TLB and two 512-entry TLBs */
+/* D-MMU: one small (16-entry) TLB and two big (512-entry) TLBs */
-#define TLB_DT16    0
+#define TLB_DSMALL  0
-#define TLB_DT512_0 2
+#define TLB_DBIG_0  2
-#define TLB_DT512_1 3
+#define TLB_DBIG_1  3
-/* I-MMU: one 16-entry TLB and one 128-entry TLB */
+/* I-MMU: one small (16-entry) TLB and one big TLB */
-#define TLB_IT16    0
+#define TLB_ISMALL  0
-#define TLB_IT128   2
+#define TLB_IBIG    2
 #endif
 #define TLB_DEMAP_CONTEXT_SHIFT 4
 /* TLB Tag Access shifts */
 #include <arch/mm/mmu.h>
 #include <arch/mm/page.h>
 #include <arch/asm.h>
 #include <arch/barrier.h>
 #include <arch/types.h>
+#include <arch/register.h>
+#include <arch/cpu.h>
 union tlb_context_reg {
     uint64_t v;
     struct {
         unsigned long : 51;
         unsigned fv : 1;    /**< Fault Valid bit. */
     } __attribute__ ((packed));
 };
 typedef union tlb_sfsr_reg tlb_sfsr_reg_t;
+#if defined (US3)
+/*
+ * Functions for determining the number of entries in TLBs. They either return
+ * a constant value or a value based on the CPU autodetection.
+ */
+/**
+ * Determine the number od entries in the DMMU's small TLB.
+ */
+static inline uint16_t tlb_dsmall_size(void)
+{
+    return 16;
+}
+/**
+ * Determine the number od entries in each DMMU's big TLB.
+ */
+static inline uint16_t tlb_dbig_size(void)
+{
+    return 512;
+}
+/**
+ * Determine the number od entries in the IMMU's small TLB.
+ */
+static inline uint16_t tlb_ismall_size(void)
+{
+    return 16;
+}
+/**
+ * Determine the number od entries in the IMMU's big TLB.
+ */
+static inline uint16_t tlb_ibig_size(void)
+{
+    if (((ver_reg_t) ver_read()).impl == IMPL_ULTRASPARCIV_PLUS)
+        return 512;
+    else
+        return 128;
+}
+#endif
 /** Read MMU Primary Context Register.
+ *
  * @return Current value of Primary Context Register.
  */
 static inline uint64_t mmu_primary_context_read(void)
 #elif defined (US3)
 /** Read IMMU TLB Data Access Register.
+ *
- * @param tlb TLB number (one of TLB_IT16 or TLB_IT128)
+ * @param tlb TLB number (one of TLB_ISMALL or TLB_IBIG)
  * @param entry TLB Entry index.
+ *
  * @return Current value of specified IMMU TLB Data Access Register.
  */
 static inline uint64_t itlb_data_access_read(int tlb, index_t entry)
     reg.local_tlb_entry = entry;
     return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value);
+}
 /** Write IMMU TLB Data Access Register.
- * @param tlb TLB number (one of TLB_IT16 or TLB_IT128)
+ * @param tlb TLB number (one of TLB_ISMALL or TLB_IBIG)
  * @param entry TLB Entry index.
  * @param value Value to be written.
  */
 static inline void itlb_data_access_write(int tlb, index_t entry, uint64_t value)
+{
     flush_pipeline();
+}
 /** Read DMMU TLB Data Access Register.
+ *
- * @param tlb TLB number (one of TLB_DT16, TLB_DT512_0, TLB_DT512_1)
+ * @param tlb TLB number (one of TLB_DSMALL, TLB_DBIG, TLB_DBIG)
  * @param entry TLB Entry index.
+ *
  * @return Current value of specified DMMU TLB Data Access Register.
  */
 static inline uint64_t dtlb_data_access_read(int tlb, index_t entry)
     return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value);
+}
 /** Write DMMU TLB Data Access Register.
+ *
- * @param tlb TLB number (one of TLB_DT16, TLB_DT512_0, TLB_DT512_1)
+ * @param tlb TLB number (one of TLB_DSMALL, TLB_DBIG_0, TLB_DBIG_1)
  * @param entry TLB Entry index.
  * @param value Value to be written.
  */
 static inline void dtlb_data_access_write(int tlb, index_t entry, uint64_t value)
+{
     membar();
+}
 /** Read IMMU TLB Tag Read Register.
+ *
- * @param tlb TLB number (one of TLB_IT16 or TLB_IT128)
+ * @param tlb TLB number (one of TLB_ISMALL or TLB_IBIG)
  * @param entry TLB Entry index.
+ *
  * @return Current value of specified IMMU TLB Tag Read Register.
  */
 static inline uint64_t itlb_tag_read_read(int tlb, index_t entry)
     return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value);
+}
 /** Read DMMU TLB Tag Read Register.
+ *
- * @param tlb TLB number (one of TLB_DT16, TLB_DT512_0, TLB_DT512_1)
+ * @param tlb TLB number (one of TLB_DSMALL, TLB_DBIG_0, TLB_DBIG_1)
  * @param entry TLB Entry index.
+ *
  * @return Current value of specified DMMU TLB Tag Read Register.
  */
 static inline uint64_t dtlb_tag_read_read(int tlb, index_t entry)

Subversion Repositories HelenOS

(root)/branches/sparc/kernel/arch/sparc64/include/mm/tlb.h – Rev 3493 → 3591