WebSVN – HelenOS – Diff – /branches/sparc/kernel/arch/sparc64/include/mm/tlb.h

  */
 #ifndef KERN_sparc64_TLB_H_
 #define KERN_sparc64_TLB_H_
+#if defined (US)
 #define ITLB_ENTRY_COUNT        64
 #define DTLB_ENTRY_COUNT        64
+#define DTLB_MAX_LOCKED_ENTRIES     DTLB_ENTRY_COUNT
+#endif
+/** DT16 is the only of the three DMMU caches that can hold locked entries. */
+#if defined (US3)
+#define DTLB_MAX_LOCKED_ENTRIES     16
+#endif
 #define MEM_CONTEXT_KERNEL      0
 #define MEM_CONTEXT_TEMP        1
 /** Page sizes. */
 #define KERNEL_PAGE_WIDTH       22  /* 4M */
 /* TLB Demap Operation types. */
 #define TLB_DEMAP_PAGE      0
 #define TLB_DEMAP_CONTEXT   1
+#if defined (US3)
+#define TLB_DEMAP_ALL       2
+#endif
 #define TLB_DEMAP_TYPE_SHIFT    6
 /* TLB Demap Operation Context register encodings. */
 #define TLB_DEMAP_PRIMARY   0
 #define TLB_DEMAP_SECONDARY 1
 #define TLB_DEMAP_NUCLEUS   2
-/* there are more TLBs in one MMU in US3, their codes are defined here */
+/* There are more TLBs in one MMU in US3, their codes are defined here. */
 #if defined (US3)
-    /* D-MMU: one 16-entry TLB and two 512-entry TLBs */
+/* D-MMU: one 16-entry TLB and two 512-entry TLBs */
-    #define TLB_DT16    0
+#define TLB_DT16    0
-    #define TLB_DT512_1 2
+#define TLB_DT512_0 2
-    #define TLB_DT512_2 3
+#define TLB_DT512_1 3
-    /* I-MMU: one 16-entry TLB and one 128-entry TLB */
+/* I-MMU: one 16-entry TLB and one 128-entry TLB */
-    #define TLB_IT16    0
+#define TLB_IT16    0
-    #define TLB_IT128   2
+#define TLB_IT128   2
 #endif
 #define TLB_DEMAP_CONTEXT_SHIFT 4
 /* TLB Tag Access shifts */
 #endif
 /** I-/D-TLB Tag Read Register. */
 union tlb_tag_read_reg {
+    // TODO have a look at how non-8kB pages will be treated
     uint64_t value;
     struct {
         uint64_t vpn : 51;  /**< Virtual Address bits 63:13. */
         unsigned context : 13;  /**< Context identifier. */
     } __attribute__ ((packed));
 /** TLB Demap Operation Address. */
 union tlb_demap_addr {
     uint64_t value;
     struct {
         uint64_t vpn: 51;   /**< Virtual Address bits 63:13. */
+#if defined (US)
         unsigned : 6;       /**< Ignored. */
         unsigned type : 1;  /**< The type of demap operation. */
+#elif defined (US3)
+        unsigned : 5;       /**< Ignored. */
+        unsigned type: 2;   /**< The type of demap operation. */
+#endif
         unsigned context : 2;   /**< Context register selection. */
         unsigned : 4;       /**< Zero. */
     } __attribute__ ((packed));
 };
 typedef union tlb_demap_addr tlb_demap_addr_t;
 /** TLB Synchronous Fault Status Register. */
 union tlb_sfsr_reg {
     uint64_t value;
     struct {
+#if defined (US)
         unsigned long : 40; /**< Implementation dependent. */
         unsigned asi : 8;   /**< ASI. */
         unsigned : 2;
         unsigned ft : 7;    /**< Fault type. */
+#elif defined (US3)
+        unsigned long : 39; /**< Implementation dependent. */
+        unsigned nf : 1;    /**< Non-faulting load. */
+        unsigned asi : 8;   /**< ASI. */
+        unsigned tm : 1;    /**< I-TLB miss. */
+        unsigned : 3;       /**< Reserved. */
+        unsigned ft : 5;    /**< Fault type. */
+#endif
         unsigned e : 1;     /**< Side-effect bit. */
         unsigned ct : 2;    /**< Context Register selection. */
         unsigned pr : 1;    /**< Privilege bit. */
         unsigned w : 1;     /**< Write bit. */
         unsigned ow : 1;    /**< Overwrite bit. */
     flush_pipeline();
+}
 /** Read DMMU TLB Data Access Register.
+ *
- * @param tlb TLB number (one of TLB_DT16, TLB_DT512_1, TLB_DT512_2)
+ * @param tlb TLB number (one of TLB_DT16, TLB_DT512_0, TLB_DT512_1)
  * @param entry TLB Entry index.
+ *
  * @return Current value of specified DMMU TLB Data Access Register.
  */
 static inline uint64_t dtlb_data_access_read(int tlb, index_t entry)
     return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value);
+}
 /** Write DMMU TLB Data Access Register.
+ *
- * @param tlb TLB number (one of TLB_DT16, TLB_DT512_1, TLB_DT512_2)
+ * @param tlb TLB number (one of TLB_DT16, TLB_DT512_0, TLB_DT512_1)
  * @param entry TLB Entry index.
  * @param value Value to be written.
  */
 static inline void dtlb_data_access_write(int tlb, index_t entry, uint64_t value)
+{
     return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value);
+}
 /** Read DMMU TLB Tag Read Register.
+ *
- * @param tlb TLB number (one of TLB_DT16, TLB_DT512_1, TLB_DT512_2)
+ * @param tlb TLB number (one of TLB_DT16, TLB_DT512_0, TLB_DT512_1)
  * @param entry TLB Entry index.
+ *
  * @return Current value of specified DMMU TLB Tag Read Register.
  */
 static inline uint64_t dtlb_tag_read_read(int tlb, index_t entry)
     return asi_u64_read(ASI_DMMU, VA_DMMU_SFAR);
+}
 /** Perform IMMU TLB Demap Operation.
+ *
+ * @param type
- * @param type Selects between context and page demap.
+ *  Selects between context and page demap
+ *  (and entire MMU demap on US-III).
  * @param context_encoding Specifies which Context register has Context ID for
  *  demap.
  * @param page Address which is on the page to be demapped.
  */
 static inline void itlb_demap(int type, int context_encoding, uintptr_t page)
     flush_pipeline();
+}
 /** Perform DMMU TLB Demap Operation.
+ *
+ * @param type
- * @param type Selects between context and page demap.
+ *  Selects between context and page demap
+ *  (and entire MMU demap on US-III).
  * @param context_encoding Specifies which Context register has Context ID for
  *   demap.
  * @param page Address which is on the page to be demapped.
  */
 static inline void dtlb_demap(int type, int context_encoding, uintptr_t page)

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(root)/branches/sparc/kernel/arch/sparc64/include/mm/tlb.h @ 3493 – Rev 3440 → 3450