WebSVN – HelenOS – Diff – /branches/sparc/kernel/arch/sparc64/include/mm/sun4v/tlb.h


/*
 * Copyright (c) 2005 Jakub Jermar
 * Copyright (c) 2008 Pavel Rimsky
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup sparc64mm  
 * @{
 */
/** @file
 */
 
#ifndef KERN_sparc64_sun4v_TLB_H_
#define KERN_sparc64_sun4v_TLB_H_
 
#define MMU_FSA_ALIGNMENT   64
#define MMU_FSA_SIZE        128
 
#ifndef __ASM__
 
#include <arch/mm/sun4v/tte.h>
#include <arch/mm/sun4v/mmu.h>
#include <arch/mm/page.h>
#include <arch/asm.h>
#include <arch/barrier.h>
#include <arch/types.h>
#include <arch/register.h>
#include <arch/cpu.h>
 
/**
 * Structure filled by hypervisor (or directly CPU, if implemented so) when
 * a MMU fault occurs. The structure describes the exact condition which
 * has caused the fault;
 */
typedef struct mmu_fault_status_area {
    uint64_t ift;       /**< Instruction fault type (IFT) */
    uint64_t ifa;       /**< Instruction fault address (IFA) */
    uint64_t ifc;       /**< Instruction fault context (IFC) */
    uint8_t reserved1[0x28];
 
    uint64_t dft;       /**< Data fault type (DFT) */
    uint64_t dfa;       /**< Data fault address (DFA) */
    uint64_t dfc;       /**< Data fault context (DFC) */
    uint8_t reserved2[0x28];
} __attribute__ ((packed)) mmu_fault_status_area_t;
 
#if 0
union tlb_context_reg {
    uint64_t v;
    struct {
        unsigned long : 51;
        unsigned context : 13;      /**< Context/ASID. */
    } __attribute__ ((packed));
};
typedef union tlb_context_reg tlb_context_reg_t;
 
 
/** I-/D-TLB Data In/Access Register type. */
typedef tte_data_t tlb_data_t;
 
/** I-/D-TLB Data Access Address in Alternate Space. */
 
#if defined (US)
 
union tlb_data_access_addr {
    uint64_t value;
    struct {
        uint64_t : 55;
        unsigned tlb_entry : 6;
        unsigned : 3;
    } __attribute__ ((packed));
};
typedef union tlb_data_access_addr dtlb_data_access_addr_t;
typedef union tlb_data_access_addr dtlb_tag_read_addr_t;
typedef union tlb_data_access_addr itlb_data_access_addr_t;
typedef union tlb_data_access_addr itlb_tag_read_addr_t;
 
#elif defined (US3)
 
/*
 * In US3, I-MMU and D-MMU have different formats of the data
 * access register virtual address. In the corresponding
 * structures the member variable for the entry number is
 * called "local_tlb_entry" - it contrasts with the "tlb_entry"
 * for the US data access register VA structure. The rationale
 * behind this is to prevent careless mistakes in the code
 * caused by setting only the entry number and not the TLB
 * number in the US3 code (when taking the code from US).
 */
 
union dtlb_data_access_addr {
    uint64_t value;
    struct {
        uint64_t : 45;
        unsigned : 1;
        unsigned tlb_number : 2;
        unsigned : 4;
        unsigned local_tlb_entry : 9;
        unsigned : 3;
    } __attribute__ ((packed));
};
typedef union dtlb_data_access_addr dtlb_data_access_addr_t;
typedef union dtlb_data_access_addr dtlb_tag_read_addr_t;
 
union itlb_data_access_addr {
    uint64_t value;
    struct {
        uint64_t : 45;
        unsigned : 1;
        unsigned tlb_number : 2;
        unsigned : 6;
        unsigned local_tlb_entry : 7;
        unsigned : 3;
    } __attribute__ ((packed));
};
typedef union itlb_data_access_addr itlb_data_access_addr_t;
typedef union itlb_data_access_addr itlb_tag_read_addr_t;
 
#endif
 
/** I-/D-TLB Tag Read Register. */
union tlb_tag_read_reg {
    uint64_t value;
    struct {
        uint64_t vpn : 51;  /**< Virtual Address bits 63:13. */
        unsigned context : 13;  /**< Context identifier. */
    } __attribute__ ((packed));
};
typedef union tlb_tag_read_reg tlb_tag_read_reg_t;
typedef union tlb_tag_read_reg tlb_tag_access_reg_t;
 
 
/** TLB Demap Operation Address. */
union tlb_demap_addr {
    uint64_t value;
    struct {
        uint64_t vpn: 51;   /**< Virtual Address bits 63:13. */
#if defined (US)
        unsigned : 6;       /**< Ignored. */
        unsigned type : 1;  /**< The type of demap operation. */
#elif defined (US3)
        unsigned : 5;       /**< Ignored. */
        unsigned type: 2;   /**< The type of demap operation. */
#endif
        unsigned context : 2;   /**< Context register selection. */
        unsigned : 4;       /**< Zero. */
    } __attribute__ ((packed));
};
typedef union tlb_demap_addr tlb_demap_addr_t;
 
/** TLB Synchronous Fault Status Register. */
union tlb_sfsr_reg {
    uint64_t value;
    struct {
#if defined (US)
        unsigned long : 40; /**< Implementation dependent. */
        unsigned asi : 8;   /**< ASI. */
        unsigned : 2;
        unsigned ft : 7;    /**< Fault type. */
#elif defined (US3)
        unsigned long : 39; /**< Implementation dependent. */
        unsigned nf : 1;    /**< Non-faulting load. */
        unsigned asi : 8;   /**< ASI. */
        unsigned tm : 1;    /**< I-TLB miss. */
        unsigned : 3;       /**< Reserved. */
        unsigned ft : 5;    /**< Fault type. */
#endif
        unsigned e : 1;     /**< Side-effect bit. */
        unsigned ct : 2;    /**< Context Register selection. */
        unsigned pr : 1;    /**< Privilege bit. */
        unsigned w : 1;     /**< Write bit. */
        unsigned ow : 1;    /**< Overwrite bit. */
        unsigned fv : 1;    /**< Fault Valid bit. */
    } __attribute__ ((packed));
};
typedef union tlb_sfsr_reg tlb_sfsr_reg_t;
 
#if defined (US3)
 
/*
 * Functions for determining the number of entries in TLBs. They either return
 * a constant value or a value based on the CPU autodetection.
 */
 
/**
 * Determine the number of entries in the DMMU's small TLB.
 */
static inline uint16_t tlb_dsmall_size(void)
{
    return 16;
}
 
/**
 * Determine the number of entries in each DMMU's big TLB.
 */
static inline uint16_t tlb_dbig_size(void)
{
    return 512;
}
 
/**
 * Determine the number of entries in the IMMU's small TLB.
 */
static inline uint16_t tlb_ismall_size(void)
{
    return 16;
}
 
/**
 * Determine the number of entries in the IMMU's big TLB.
 */
static inline uint16_t tlb_ibig_size(void)
{
    if (((ver_reg_t) ver_read()).impl == IMPL_ULTRASPARCIV_PLUS)
        return 512;
    else
        return 128;
}
 
#endif
 
/** Read MMU Primary Context Register.
 *
 * @return      Current value of Primary Context Register.
 */
static inline uint64_t mmu_primary_context_read(void)
{
    return asi_u64_read(ASI_DMMU, VA_PRIMARY_CONTEXT_REG);
}
 
/** Write MMU Primary Context Register.
 *
 * @param v     New value of Primary Context Register.
 */
static inline void mmu_primary_context_write(uint64_t v)
{
    asi_u64_write(ASI_DMMU, VA_PRIMARY_CONTEXT_REG, v);
    flush_pipeline();
}
 
/** Read MMU Secondary Context Register.
 *
 * @return      Current value of Secondary Context Register.
 */
static inline uint64_t mmu_secondary_context_read(void)
{
    return asi_u64_read(ASI_DMMU, VA_SECONDARY_CONTEXT_REG);
}
 
/** Write MMU Primary Context Register.
 *
 * @param v     New value of Primary Context Register.
 */
static inline void mmu_secondary_context_write(uint64_t v)
{
    asi_u64_write(ASI_DMMU, VA_SECONDARY_CONTEXT_REG, v);
    flush_pipeline();
}
 
#if defined (US)
 
/** Read IMMU TLB Data Access Register.
 *
 * @param entry     TLB Entry index.
 *
 * @return      Current value of specified IMMU TLB Data Access
 *          Register.
 */
static inline uint64_t itlb_data_access_read(index_t entry)
{
    itlb_data_access_addr_t reg;
   
    reg.value = 0;
    reg.tlb_entry = entry;
    return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value);
}
 
/** Write IMMU TLB Data Access Register.
 *
 * @param entry     TLB Entry index.
 * @param value     Value to be written.
 */
static inline void itlb_data_access_write(index_t entry, uint64_t value)
{
    itlb_data_access_addr_t reg;
   
    reg.value = 0;
    reg.tlb_entry = entry;
    asi_u64_write(ASI_ITLB_DATA_ACCESS_REG, reg.value, value);
    flush_pipeline();
}
 
/** Read DMMU TLB Data Access Register.
 *
 * @param entry     TLB Entry index.
 *
 * @return      Current value of specified DMMU TLB Data Access
 *          Register.
 */
static inline uint64_t dtlb_data_access_read(index_t entry)
{
    dtlb_data_access_addr_t reg;
   
    reg.value = 0;
    reg.tlb_entry = entry;
    return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value);
}
 
/** Write DMMU TLB Data Access Register.
 *
 * @param entry     TLB Entry index.
 * @param value     Value to be written.
 */
static inline void dtlb_data_access_write(index_t entry, uint64_t value)
{
    dtlb_data_access_addr_t reg;
   
    reg.value = 0;
    reg.tlb_entry = entry;
    asi_u64_write(ASI_DTLB_DATA_ACCESS_REG, reg.value, value);
    membar();
}
 
/** Read IMMU TLB Tag Read Register.
 *
 * @param entry     TLB Entry index.
 *
 * @return      Current value of specified IMMU TLB Tag Read Register.
 */
static inline uint64_t itlb_tag_read_read(index_t entry)
{
    itlb_tag_read_addr_t tag;
 
    tag.value = 0;
    tag.tlb_entry = entry;
    return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value);
}
 
/** Read DMMU TLB Tag Read Register.
 *
 * @param entry     TLB Entry index.
 *
 * @return      Current value of specified DMMU TLB Tag Read Register.
 */
static inline uint64_t dtlb_tag_read_read(index_t entry)
{
    dtlb_tag_read_addr_t tag;
 
    tag.value = 0;
    tag.tlb_entry = entry;
    return asi_u64_read(ASI_DTLB_TAG_READ_REG, tag.value);
}
 
#elif defined (US3)
 
 
/** Read IMMU TLB Data Access Register.
 *
 * @param tlb       TLB number (one of TLB_ISMALL or TLB_IBIG)
 * @param entry     TLB Entry index.
 *
 * @return      Current value of specified IMMU TLB Data Access
 *          Register.
 */
static inline uint64_t itlb_data_access_read(int tlb, index_t entry)
{
    itlb_data_access_addr_t reg;
   
    reg.value = 0;
    reg.tlb_number = tlb;
    reg.local_tlb_entry = entry;
    return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value);
}
 
/** Write IMMU TLB Data Access Register.
 * @param tlb       TLB number (one of TLB_ISMALL or TLB_IBIG)
 * @param entry     TLB Entry index.
 * @param value     Value to be written.
 */
static inline void itlb_data_access_write(int tlb, index_t entry,
    uint64_t value)
{
    itlb_data_access_addr_t reg;
   
    reg.value = 0;
    reg.tlb_number = tlb;
    reg.local_tlb_entry = entry;
    asi_u64_write(ASI_ITLB_DATA_ACCESS_REG, reg.value, value);
    flush_pipeline();
}
 
/** Read DMMU TLB Data Access Register.
 *
 * @param tlb       TLB number (one of TLB_DSMALL, TLB_DBIG, TLB_DBIG)
 * @param entry     TLB Entry index.
 *
 * @return      Current value of specified DMMU TLB Data Access
 *          Register.
 */
static inline uint64_t dtlb_data_access_read(int tlb, index_t entry)
{
    dtlb_data_access_addr_t reg;
   
    reg.value = 0;
    reg.tlb_number = tlb;
    reg.local_tlb_entry = entry;
    return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value);
}
 
/** Write DMMU TLB Data Access Register.
 *
 * @param tlb       TLB number (one of TLB_DSMALL, TLB_DBIG_0, TLB_DBIG_1)  
 * @param entry     TLB Entry index.
 * @param value     Value to be written.
 */
static inline void dtlb_data_access_write(int tlb, index_t entry,
    uint64_t value)
{
    dtlb_data_access_addr_t reg;
   
    reg.value = 0;
    reg.tlb_number = tlb;
    reg.local_tlb_entry = entry;
    asi_u64_write(ASI_DTLB_DATA_ACCESS_REG, reg.value, value);
    membar();
}
 
/** Read IMMU TLB Tag Read Register.
 *
 * @param tlb       TLB number (one of TLB_ISMALL or TLB_IBIG)
 * @param entry     TLB Entry index.
 *
 * @return      Current value of specified IMMU TLB Tag Read Register.
 */
static inline uint64_t itlb_tag_read_read(int tlb, index_t entry)
{
    itlb_tag_read_addr_t tag;
 
    tag.value = 0;
    tag.tlb_number = tlb;
    tag.local_tlb_entry = entry;
    return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value);
}
 
/** Read DMMU TLB Tag Read Register.
 *
 * @param tlb       TLB number (one of TLB_DSMALL, TLB_DBIG_0, TLB_DBIG_1)
 * @param entry     TLB Entry index.
 *
 * @return      Current value of specified DMMU TLB Tag Read Register.
 */
static inline uint64_t dtlb_tag_read_read(int tlb, index_t entry)
{
    dtlb_tag_read_addr_t tag;
 
    tag.value = 0;
    tag.tlb_number = tlb;
    tag.local_tlb_entry = entry;
    return asi_u64_read(ASI_DTLB_TAG_READ_REG, tag.value);
}
 
#endif
 
 
/** Write IMMU TLB Tag Access Register.
 *
 * @param v     Value to be written.
 */
static inline void itlb_tag_access_write(uint64_t v)
{
    asi_u64_write(ASI_IMMU, VA_IMMU_TAG_ACCESS, v);
    flush_pipeline();
}
 
/** Read IMMU TLB Tag Access Register.
 *
 * @return      Current value of IMMU TLB Tag Access Register.
 */
static inline uint64_t itlb_tag_access_read(void)
{
    return asi_u64_read(ASI_IMMU, VA_IMMU_TAG_ACCESS);
}
 
/** Write DMMU TLB Tag Access Register.
 *
 * @param v     Value to be written.
 */
static inline void dtlb_tag_access_write(uint64_t v)
{
    asi_u64_write(ASI_DMMU, VA_DMMU_TAG_ACCESS, v);
    membar();
}
 
/** Read DMMU TLB Tag Access Register.
 *
 * @return      Current value of DMMU TLB Tag Access Register.
 */
static inline uint64_t dtlb_tag_access_read(void)
{
    return asi_u64_read(ASI_DMMU, VA_DMMU_TAG_ACCESS);
}
 
 
/** Write IMMU TLB Data in Register.
 *
 * @param v     Value to be written.
 */
static inline void itlb_data_in_write(uint64_t v)
{
    asi_u64_write(ASI_ITLB_DATA_IN_REG, 0, v);
    flush_pipeline();
}
 
/** Write DMMU TLB Data in Register.
 *
 * @param v     Value to be written.
 */
static inline void dtlb_data_in_write(uint64_t v)
{
    asi_u64_write(ASI_DTLB_DATA_IN_REG, 0, v);
    membar();
}
 
/** Read ITLB Synchronous Fault Status Register.
 *
 * @return      Current content of I-SFSR register.
 */
static inline uint64_t itlb_sfsr_read(void)
{
    return asi_u64_read(ASI_IMMU, VA_IMMU_SFSR);
}
 
/** Write ITLB Synchronous Fault Status Register.
 *
 * @param v     New value of I-SFSR register.
 */
static inline void itlb_sfsr_write(uint64_t v)
{
    asi_u64_write(ASI_IMMU, VA_IMMU_SFSR, v);
    flush_pipeline();
}
 
/** Read DTLB Synchronous Fault Status Register.
 *
 * @return      Current content of D-SFSR register.
 */
static inline uint64_t dtlb_sfsr_read(void)
{
    return asi_u64_read(ASI_DMMU, VA_DMMU_SFSR);
}
 
/** Write DTLB Synchronous Fault Status Register.
 *
 * @param v     New value of D-SFSR register.
 */
static inline void dtlb_sfsr_write(uint64_t v)
{
    asi_u64_write(ASI_DMMU, VA_DMMU_SFSR, v);
    membar();
}
 
/** Read DTLB Synchronous Fault Address Register.
 *
 * @return      Current content of D-SFAR register.
 */
static inline uint64_t dtlb_sfar_read(void)
{
    return asi_u64_read(ASI_DMMU, VA_DMMU_SFAR);
}
 
/** Perform IMMU TLB Demap Operation.
 *
 * @param type      Selects between context and page demap (and entire MMU
 *          demap on US3).
 * @param context_encoding Specifies which Context register has Context ID for
 *          demap.
 * @param page      Address which is on the page to be demapped.
 */
static inline void itlb_demap(int type, int context_encoding, uintptr_t page)
{
    tlb_demap_addr_t da;
    page_address_t pg;
   
    da.value = 0;
    pg.address = page;
   
    da.type = type;
    da.context = context_encoding;
    da.vpn = pg.vpn;
   
    /* da.value is the address within the ASI */
    asi_u64_write(ASI_IMMU_DEMAP, da.value, 0);
 
    flush_pipeline();
}
 
/** Perform DMMU TLB Demap Operation.
 *
 * @param type      Selects between context and page demap (and entire MMU
 *          demap on US3).
 * @param context_encoding Specifies which Context register has Context ID for
 *          demap.
 * @param page      Address which is on the page to be demapped.
 */
static inline void dtlb_demap(int type, int context_encoding, uintptr_t page)
{
    tlb_demap_addr_t da;
    page_address_t pg;
   
    da.value = 0;
    pg.address = page;
   
    da.type = type;
    da.context = context_encoding;
    da.vpn = pg.vpn;
   
    /* da.value is the address within the ASI */
    asi_u64_write(ASI_DMMU_DEMAP, da.value, 0);
 
    membar();
}
 
#endif
extern void fast_instruction_access_mmu_miss(unative_t, istate_t *);
//extern void fast_data_access_mmu_miss(tlb_tag_access_reg_t, istate_t *);
//extern void fast_data_access_protection(tlb_tag_access_reg_t , istate_t *);
 
extern void dtlb_insert_mapping(uintptr_t, uintptr_t, int, bool, bool);
 
extern void describe_mmu_fault(void);
 
#endif /* !def __ASM__ */
 
#endif
 
/** @}
 */
 

Rev 3771	Rev 3835
1	/*	1	/*
2	* Copyright (c) 2005 Jakub Jermar	2	* Copyright (c) 2005 Jakub Jermar
3	* Copyright (c) 2008 Pavel Rimsky	3	* Copyright (c) 2008 Pavel Rimsky
4	* All rights reserved.	4	* All rights reserved.
5	*	5	*
6	* Redistribution and use in source and binary forms, with or without	6	* Redistribution and use in source and binary forms, with or without
7	* modification, are permitted provided that the following conditions	7	* modification, are permitted provided that the following conditions
8	* are met:	8	* are met:
9	*	9	*
10	* - Redistributions of source code must retain the above copyright	10	* - Redistributions of source code must retain the above copyright
11	* notice, this list of conditions and the following disclaimer.	11	* notice, this list of conditions and the following disclaimer.
12	* - Redistributions in binary form must reproduce the above copyright	12	* - Redistributions in binary form must reproduce the above copyright
13	* notice, this list of conditions and the following disclaimer in the	13	* notice, this list of conditions and the following disclaimer in the
14	* documentation and/or other materials provided with the distribution.	14	* documentation and/or other materials provided with the distribution.
15	* - The name of the author may not be used to endorse or promote products	15	* - The name of the author may not be used to endorse or promote products
16	* derived from this software without specific prior written permission.	16	* derived from this software without specific prior written permission.
17	*	17	*
18	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	18	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	19	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	20	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	21	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	22	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	23	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	24	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	25	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	26	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	27	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28	*/	28	*/
29		29
30	/** @addtogroup sparc64mm	30	/** @addtogroup sparc64mm
31	* @{	31	* @{
32	*/	32	*/
33	/** @file	33	/** @file
34	*/	34	*/
35		35
36	#ifndef KERN_sparc64_sun4v_TLB_H_	36	#ifndef KERN_sparc64_sun4v_TLB_H_
37	#define KERN_sparc64_sun4v_TLB_H_	37	#define KERN_sparc64_sun4v_TLB_H_
38		38
-		39	#define MMU_FSA_ALIGNMENT 64
-		40	#define MMU_FSA_SIZE 128
-		41
39	#ifndef __ASM__	42	#ifndef __ASM__
40		43
41	#include <arch/mm/sun4v/tte.h>	44	#include <arch/mm/sun4v/tte.h>
42	#include <arch/mm/sun4v/mmu.h>	45	#include <arch/mm/sun4v/mmu.h>
43	#include <arch/mm/page.h>	46	#include <arch/mm/page.h>
44	#include <arch/asm.h>	47	#include <arch/asm.h>
45	#include <arch/barrier.h>	48	#include <arch/barrier.h>
46	#include <arch/types.h>	49	#include <arch/types.h>
47	#include <arch/register.h>	50	#include <arch/register.h>
48	#include <arch/cpu.h>	51	#include <arch/cpu.h>
49		52
50	/**	53	/**
51	* Structure filled by hypervisor (or directly CPU, if implemented so) when	54	* Structure filled by hypervisor (or directly CPU, if implemented so) when
52	* a MMU fault occurs. The structure describes the exact condition which	55	* a MMU fault occurs. The structure describes the exact condition which
53	* has caused the fault;	56	* has caused the fault;
54	*/	57	*/
55	typedef struct mmu_fault_status_area {	58	typedef struct mmu_fault_status_area {
56	uint64_t ift; /*< Instruction fault type (IFT) /	59	uint64_t ift; /*< Instruction fault type (IFT) /
57	uint64_t ifa; /*< Instruction fault address (IFA) /	60	uint64_t ifa; /*< Instruction fault address (IFA) /
58	uint64_t ifc; /*< Instruction fault context (IFC) /	61	uint64_t ifc; /*< Instruction fault context (IFC) /
59	uint8_t reserved1[0x28];	62	uint8_t reserved1[0x28];
60		63
61	uint64_t dft; /*< Data fault type (DFT) /	64	uint64_t dft; /*< Data fault type (DFT) /
62	uint64_t dfa; /*< Data fault address (DFA) /	65	uint64_t dfa; /*< Data fault address (DFA) /
63	uint64_t dfc; /*< Data fault context (DFC) /	66	uint64_t dfc; /*< Data fault context (DFC) /
64	uint8_t reserved2[0x28];	67	uint8_t reserved2[0x28];
65	} __attribute__ ((packed)) mmu_fault_status_area_t;	68	} __attribute__ ((packed)) mmu_fault_status_area_t;
66		69
67	#if 0	70	#if 0
68	union tlb_context_reg {	71	union tlb_context_reg {
69	uint64_t v;	72	uint64_t v;
70	struct {	73	struct {
71	unsigned long : 51;	74	unsigned long : 51;
72	unsigned context : 13; /*< Context/ASID. /	75	unsigned context : 13; /*< Context/ASID. /
73	} __attribute__ ((packed));	76	} __attribute__ ((packed));
74	};	77	};
75	typedef union tlb_context_reg tlb_context_reg_t;	78	typedef union tlb_context_reg tlb_context_reg_t;
76		79
77		80
78	/** I-/D-TLB Data In/Access Register type. */	81	/** I-/D-TLB Data In/Access Register type. */
79	typedef tte_data_t tlb_data_t;	82	typedef tte_data_t tlb_data_t;
80		83
81	/** I-/D-TLB Data Access Address in Alternate Space. */	84	/** I-/D-TLB Data Access Address in Alternate Space. */
82		85
83	#if defined (US)	86	#if defined (US)
84		87
85	union tlb_data_access_addr {	88	union tlb_data_access_addr {
86	uint64_t value;	89	uint64_t value;
87	struct {	90	struct {
88	uint64_t : 55;	91	uint64_t : 55;
89	unsigned tlb_entry : 6;	92	unsigned tlb_entry : 6;
90	unsigned : 3;	93	unsigned : 3;
91	} __attribute__ ((packed));	94	} __attribute__ ((packed));
92	};	95	};
93	typedef union tlb_data_access_addr dtlb_data_access_addr_t;	96	typedef union tlb_data_access_addr dtlb_data_access_addr_t;
94	typedef union tlb_data_access_addr dtlb_tag_read_addr_t;	97	typedef union tlb_data_access_addr dtlb_tag_read_addr_t;
95	typedef union tlb_data_access_addr itlb_data_access_addr_t;	98	typedef union tlb_data_access_addr itlb_data_access_addr_t;
96	typedef union tlb_data_access_addr itlb_tag_read_addr_t;	99	typedef union tlb_data_access_addr itlb_tag_read_addr_t;
97		100
98	#elif defined (US3)	101	#elif defined (US3)
99		102
100	/*	103	/*
101	* In US3, I-MMU and D-MMU have different formats of the data	104	* In US3, I-MMU and D-MMU have different formats of the data
102	* access register virtual address. In the corresponding	105	* access register virtual address. In the corresponding
103	* structures the member variable for the entry number is	106	* structures the member variable for the entry number is
104	* called "local_tlb_entry" - it contrasts with the "tlb_entry"	107	* called "local_tlb_entry" - it contrasts with the "tlb_entry"
105	* for the US data access register VA structure. The rationale	108	* for the US data access register VA structure. The rationale
106	* behind this is to prevent careless mistakes in the code	109	* behind this is to prevent careless mistakes in the code
107	* caused by setting only the entry number and not the TLB	110	* caused by setting only the entry number and not the TLB
108	* number in the US3 code (when taking the code from US).	111	* number in the US3 code (when taking the code from US).
109	*/	112	*/
110		113
111	union dtlb_data_access_addr {	114	union dtlb_data_access_addr {
112	uint64_t value;	115	uint64_t value;
113	struct {	116	struct {
114	uint64_t : 45;	117	uint64_t : 45;
115	unsigned : 1;	118	unsigned : 1;
116	unsigned tlb_number : 2;	119	unsigned tlb_number : 2;
117	unsigned : 4;	120	unsigned : 4;
118	unsigned local_tlb_entry : 9;	121	unsigned local_tlb_entry : 9;
119	unsigned : 3;	122	unsigned : 3;
120	} __attribute__ ((packed));	123	} __attribute__ ((packed));
121	};	124	};
122	typedef union dtlb_data_access_addr dtlb_data_access_addr_t;	125	typedef union dtlb_data_access_addr dtlb_data_access_addr_t;
123	typedef union dtlb_data_access_addr dtlb_tag_read_addr_t;	126	typedef union dtlb_data_access_addr dtlb_tag_read_addr_t;
124		127
125	union itlb_data_access_addr {	128	union itlb_data_access_addr {
126	uint64_t value;	129	uint64_t value;
127	struct {	130	struct {
128	uint64_t : 45;	131	uint64_t : 45;
129	unsigned : 1;	132	unsigned : 1;
130	unsigned tlb_number : 2;	133	unsigned tlb_number : 2;
131	unsigned : 6;	134	unsigned : 6;
132	unsigned local_tlb_entry : 7;	135	unsigned local_tlb_entry : 7;
133	unsigned : 3;	136	unsigned : 3;
134	} __attribute__ ((packed));	137	} __attribute__ ((packed));
135	};	138	};
136	typedef union itlb_data_access_addr itlb_data_access_addr_t;	139	typedef union itlb_data_access_addr itlb_data_access_addr_t;
137	typedef union itlb_data_access_addr itlb_tag_read_addr_t;	140	typedef union itlb_data_access_addr itlb_tag_read_addr_t;
138		141
139	#endif	142	#endif
140		143
141	/** I-/D-TLB Tag Read Register. */	144	/** I-/D-TLB Tag Read Register. */
142	union tlb_tag_read_reg {	145	union tlb_tag_read_reg {
143	uint64_t value;	146	uint64_t value;
144	struct {	147	struct {
145	uint64_t vpn : 51; /*< Virtual Address bits 63:13. /	148	uint64_t vpn : 51; /*< Virtual Address bits 63:13. /
146	unsigned context : 13; /*< Context identifier. /	149	unsigned context : 13; /*< Context identifier. /
147	} __attribute__ ((packed));	150	} __attribute__ ((packed));
148	};	151	};
149	typedef union tlb_tag_read_reg tlb_tag_read_reg_t;	152	typedef union tlb_tag_read_reg tlb_tag_read_reg_t;
150	typedef union tlb_tag_read_reg tlb_tag_access_reg_t;	153	typedef union tlb_tag_read_reg tlb_tag_access_reg_t;
151		154
152		155
153	/** TLB Demap Operation Address. */	156	/** TLB Demap Operation Address. */
154	union tlb_demap_addr {	157	union tlb_demap_addr {
155	uint64_t value;	158	uint64_t value;
156	struct {	159	struct {
157	uint64_t vpn: 51; /*< Virtual Address bits 63:13. /	160	uint64_t vpn: 51; /*< Virtual Address bits 63:13. /
158	#if defined (US)	161	#if defined (US)
159	unsigned : 6; /*< Ignored. /	162	unsigned : 6; /*< Ignored. /
160	unsigned type : 1; /*< The type of demap operation. /	163	unsigned type : 1; /*< The type of demap operation. /
161	#elif defined (US3)	164	#elif defined (US3)
162	unsigned : 5; /*< Ignored. /	165	unsigned : 5; /*< Ignored. /
163	unsigned type: 2; /*< The type of demap operation. /	166	unsigned type: 2; /*< The type of demap operation. /
164	#endif	167	#endif
165	unsigned context : 2; /*< Context register selection. /	168	unsigned context : 2; /*< Context register selection. /
166	unsigned : 4; /*< Zero. /	169	unsigned : 4; /*< Zero. /
167	} __attribute__ ((packed));	170	} __attribute__ ((packed));
168	};	171	};
169	typedef union tlb_demap_addr tlb_demap_addr_t;	172	typedef union tlb_demap_addr tlb_demap_addr_t;
170		173
171	/** TLB Synchronous Fault Status Register. */	174	/** TLB Synchronous Fault Status Register. */
172	union tlb_sfsr_reg {	175	union tlb_sfsr_reg {
173	uint64_t value;	176	uint64_t value;
174	struct {	177	struct {
175	#if defined (US)	178	#if defined (US)
176	unsigned long : 40; /*< Implementation dependent. /	179	unsigned long : 40; /*< Implementation dependent. /
177	unsigned asi : 8; /*< ASI. /	180	unsigned asi : 8; /*< ASI. /
178	unsigned : 2;	181	unsigned : 2;
179	unsigned ft : 7; /*< Fault type. /	182	unsigned ft : 7; /*< Fault type. /
180	#elif defined (US3)	183	#elif defined (US3)
181	unsigned long : 39; /*< Implementation dependent. /	184	unsigned long : 39; /*< Implementation dependent. /
182	unsigned nf : 1; /*< Non-faulting load. /	185	unsigned nf : 1; /*< Non-faulting load. /
183	unsigned asi : 8; /*< ASI. /	186	unsigned asi : 8; /*< ASI. /
184	unsigned tm : 1; /*< I-TLB miss. /	187	unsigned tm : 1; /*< I-TLB miss. /
185	unsigned : 3; /*< Reserved. /	188	unsigned : 3; /*< Reserved. /
186	unsigned ft : 5; /*< Fault type. /	189	unsigned ft : 5; /*< Fault type. /
187	#endif	190	#endif
188	unsigned e : 1; /*< Side-effect bit. /	191	unsigned e : 1; /*< Side-effect bit. /
189	unsigned ct : 2; /*< Context Register selection. /	192	unsigned ct : 2; /*< Context Register selection. /
190	unsigned pr : 1; /*< Privilege bit. /	193	unsigned pr : 1; /*< Privilege bit. /
191	unsigned w : 1; /*< Write bit. /	194	unsigned w : 1; /*< Write bit. /
192	unsigned ow : 1; /*< Overwrite bit. /	195	unsigned ow : 1; /*< Overwrite bit. /
193	unsigned fv : 1; /*< Fault Valid bit. /	196	unsigned fv : 1; /*< Fault Valid bit. /
194	} __attribute__ ((packed));	197	} __attribute__ ((packed));
195	};	198	};
196	typedef union tlb_sfsr_reg tlb_sfsr_reg_t;	199	typedef union tlb_sfsr_reg tlb_sfsr_reg_t;
197		200
198	#if defined (US3)	201	#if defined (US3)
199		202
200	/*	203	/*
201	* Functions for determining the number of entries in TLBs. They either return	204	* Functions for determining the number of entries in TLBs. They either return
202	* a constant value or a value based on the CPU autodetection.	205	* a constant value or a value based on the CPU autodetection.
203	*/	206	*/
204		207
205	/**	208	/**
206	* Determine the number of entries in the DMMU's small TLB.	209	* Determine the number of entries in the DMMU's small TLB.
207	*/	210	*/
208	static inline uint16_t tlb_dsmall_size(void)	211	static inline uint16_t tlb_dsmall_size(void)
209	{	212	{
210	return 16;	213	return 16;
211	}	214	}
212		215
213	/**	216	/**
214	* Determine the number of entries in each DMMU's big TLB.	217	* Determine the number of entries in each DMMU's big TLB.
215	*/	218	*/
216	static inline uint16_t tlb_dbig_size(void)	219	static inline uint16_t tlb_dbig_size(void)
217	{	220	{
218	return 512;	221	return 512;
219	}	222	}
220		223
221	/**	224	/**
222	* Determine the number of entries in the IMMU's small TLB.	225	* Determine the number of entries in the IMMU's small TLB.
223	*/	226	*/
224	static inline uint16_t tlb_ismall_size(void)	227	static inline uint16_t tlb_ismall_size(void)
225	{	228	{
226	return 16;	229	return 16;
227	}	230	}
228		231
229	/**	232	/**
230	* Determine the number of entries in the IMMU's big TLB.	233	* Determine the number of entries in the IMMU's big TLB.
231	*/	234	*/
232	static inline uint16_t tlb_ibig_size(void)	235	static inline uint16_t tlb_ibig_size(void)
233	{	236	{
234	if (((ver_reg_t) ver_read()).impl == IMPL_ULTRASPARCIV_PLUS)	237	if (((ver_reg_t) ver_read()).impl == IMPL_ULTRASPARCIV_PLUS)
235	return 512;	238	return 512;
236	else	239	else
237	return 128;	240	return 128;
238	}	241	}
239		242
240	#endif	243	#endif
241		244
242	/** Read MMU Primary Context Register.	245	/** Read MMU Primary Context Register.
243	*	246	*
244	* @return Current value of Primary Context Register.	247	* @return Current value of Primary Context Register.
245	*/	248	*/
246	static inline uint64_t mmu_primary_context_read(void)	249	static inline uint64_t mmu_primary_context_read(void)
247	{	250	{
248	return asi_u64_read(ASI_DMMU, VA_PRIMARY_CONTEXT_REG);	251	return asi_u64_read(ASI_DMMU, VA_PRIMARY_CONTEXT_REG);
249	}	252	}
250		253
251	/** Write MMU Primary Context Register.	254	/** Write MMU Primary Context Register.
252	*	255	*
253	* @param v New value of Primary Context Register.	256	* @param v New value of Primary Context Register.
254	*/	257	*/
255	static inline void mmu_primary_context_write(uint64_t v)	258	static inline void mmu_primary_context_write(uint64_t v)
256	{	259	{
257	asi_u64_write(ASI_DMMU, VA_PRIMARY_CONTEXT_REG, v);	260	asi_u64_write(ASI_DMMU, VA_PRIMARY_CONTEXT_REG, v);
258	flush_pipeline();	261	flush_pipeline();
259	}	262	}
260		263
261	/** Read MMU Secondary Context Register.	264	/** Read MMU Secondary Context Register.
262	*	265	*
263	* @return Current value of Secondary Context Register.	266	* @return Current value of Secondary Context Register.
264	*/	267	*/
265	static inline uint64_t mmu_secondary_context_read(void)	268	static inline uint64_t mmu_secondary_context_read(void)
266	{	269	{
267	return asi_u64_read(ASI_DMMU, VA_SECONDARY_CONTEXT_REG);	270	return asi_u64_read(ASI_DMMU, VA_SECONDARY_CONTEXT_REG);
268	}	271	}
269		272
270	/** Write MMU Primary Context Register.	273	/** Write MMU Primary Context Register.
271	*	274	*
272	* @param v New value of Primary Context Register.	275	* @param v New value of Primary Context Register.
273	*/	276	*/
274	static inline void mmu_secondary_context_write(uint64_t v)	277	static inline void mmu_secondary_context_write(uint64_t v)
275	{	278	{
276	asi_u64_write(ASI_DMMU, VA_SECONDARY_CONTEXT_REG, v);	279	asi_u64_write(ASI_DMMU, VA_SECONDARY_CONTEXT_REG, v);
277	flush_pipeline();	280	flush_pipeline();
278	}	281	}
279		282
280	#if defined (US)	283	#if defined (US)
281		284
282	/** Read IMMU TLB Data Access Register.	285	/** Read IMMU TLB Data Access Register.
283	*	286	*
284	* @param entry TLB Entry index.	287	* @param entry TLB Entry index.
285	*	288	*
286	* @return Current value of specified IMMU TLB Data Access	289	* @return Current value of specified IMMU TLB Data Access
287	* Register.	290	* Register.
288	*/	291	*/
289	static inline uint64_t itlb_data_access_read(index_t entry)	292	static inline uint64_t itlb_data_access_read(index_t entry)
290	{	293	{
291	itlb_data_access_addr_t reg;	294	itlb_data_access_addr_t reg;
292		295
293	reg.value = 0;	296	reg.value = 0;
294	reg.tlb_entry = entry;	297	reg.tlb_entry = entry;
295	return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value);	298	return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value);
296	}	299	}
297		300
298	/** Write IMMU TLB Data Access Register.	301	/** Write IMMU TLB Data Access Register.
299	*	302	*
300	* @param entry TLB Entry index.	303	* @param entry TLB Entry index.
301	* @param value Value to be written.	304	* @param value Value to be written.
302	*/	305	*/
303	static inline void itlb_data_access_write(index_t entry, uint64_t value)	306	static inline void itlb_data_access_write(index_t entry, uint64_t value)
304	{	307	{
305	itlb_data_access_addr_t reg;	308	itlb_data_access_addr_t reg;
306		309
307	reg.value = 0;	310	reg.value = 0;
308	reg.tlb_entry = entry;	311	reg.tlb_entry = entry;
309	asi_u64_write(ASI_ITLB_DATA_ACCESS_REG, reg.value, value);	312	asi_u64_write(ASI_ITLB_DATA_ACCESS_REG, reg.value, value);
310	flush_pipeline();	313	flush_pipeline();
311	}	314	}
312		315
313	/** Read DMMU TLB Data Access Register.	316	/** Read DMMU TLB Data Access Register.
314	*	317	*
315	* @param entry TLB Entry index.	318	* @param entry TLB Entry index.
316	*	319	*
317	* @return Current value of specified DMMU TLB Data Access	320	* @return Current value of specified DMMU TLB Data Access
318	* Register.	321	* Register.
319	*/	322	*/
320	static inline uint64_t dtlb_data_access_read(index_t entry)	323	static inline uint64_t dtlb_data_access_read(index_t entry)
321	{	324	{
322	dtlb_data_access_addr_t reg;	325	dtlb_data_access_addr_t reg;
323		326
324	reg.value = 0;	327	reg.value = 0;
325	reg.tlb_entry = entry;	328	reg.tlb_entry = entry;
326	return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value);	329	return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value);
327	}	330	}
328		331
329	/** Write DMMU TLB Data Access Register.	332	/** Write DMMU TLB Data Access Register.
330	*	333	*
331	* @param entry TLB Entry index.	334	* @param entry TLB Entry index.
332	* @param value Value to be written.	335	* @param value Value to be written.
333	*/	336	*/
334	static inline void dtlb_data_access_write(index_t entry, uint64_t value)	337	static inline void dtlb_data_access_write(index_t entry, uint64_t value)
335	{	338	{
336	dtlb_data_access_addr_t reg;	339	dtlb_data_access_addr_t reg;
337		340
338	reg.value = 0;	341	reg.value = 0;
339	reg.tlb_entry = entry;	342	reg.tlb_entry = entry;
340	asi_u64_write(ASI_DTLB_DATA_ACCESS_REG, reg.value, value);	343	asi_u64_write(ASI_DTLB_DATA_ACCESS_REG, reg.value, value);
341	membar();	344	membar();
342	}	345	}
343		346
344	/** Read IMMU TLB Tag Read Register.	347	/** Read IMMU TLB Tag Read Register.
345	*	348	*
346	* @param entry TLB Entry index.	349	* @param entry TLB Entry index.
347	*	350	*
348	* @return Current value of specified IMMU TLB Tag Read Register.	351	* @return Current value of specified IMMU TLB Tag Read Register.
349	*/	352	*/
350	static inline uint64_t itlb_tag_read_read(index_t entry)	353	static inline uint64_t itlb_tag_read_read(index_t entry)
351	{	354	{
352	itlb_tag_read_addr_t tag;	355	itlb_tag_read_addr_t tag;
353		356
354	tag.value = 0;	357	tag.value = 0;
355	tag.tlb_entry = entry;	358	tag.tlb_entry = entry;
356	return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value);	359	return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value);
357	}	360	}
358		361
359	/** Read DMMU TLB Tag Read Register.	362	/** Read DMMU TLB Tag Read Register.
360	*	363	*
361	* @param entry TLB Entry index.	364	* @param entry TLB Entry index.
362	*	365	*
363	* @return Current value of specified DMMU TLB Tag Read Register.	366	* @return Current value of specified DMMU TLB Tag Read Register.
364	*/	367	*/
365	static inline uint64_t dtlb_tag_read_read(index_t entry)	368	static inline uint64_t dtlb_tag_read_read(index_t entry)
366	{	369	{
367	dtlb_tag_read_addr_t tag;	370	dtlb_tag_read_addr_t tag;
368		371
369	tag.value = 0;	372	tag.value = 0;
370	tag.tlb_entry = entry;	373	tag.tlb_entry = entry;
371	return asi_u64_read(ASI_DTLB_TAG_READ_REG, tag.value);	374	return asi_u64_read(ASI_DTLB_TAG_READ_REG, tag.value);
372	}	375	}
373		376
374	#elif defined (US3)	377	#elif defined (US3)
375		378
376		379
377	/** Read IMMU TLB Data Access Register.	380	/** Read IMMU TLB Data Access Register.
378	*	381	*
379	* @param tlb TLB number (one of TLB_ISMALL or TLB_IBIG)	382	* @param tlb TLB number (one of TLB_ISMALL or TLB_IBIG)
380	* @param entry TLB Entry index.	383	* @param entry TLB Entry index.
381	*	384	*
382	* @return Current value of specified IMMU TLB Data Access	385	* @return Current value of specified IMMU TLB Data Access
383	* Register.	386	* Register.
384	*/	387	*/
385	static inline uint64_t itlb_data_access_read(int tlb, index_t entry)	388	static inline uint64_t itlb_data_access_read(int tlb, index_t entry)
386	{	389	{
387	itlb_data_access_addr_t reg;	390	itlb_data_access_addr_t reg;
388		391
389	reg.value = 0;	392	reg.value = 0;
390	reg.tlb_number = tlb;	393	reg.tlb_number = tlb;
391	reg.local_tlb_entry = entry;	394	reg.local_tlb_entry = entry;
392	return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value);	395	return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value);
393	}	396	}
394		397
395	/** Write IMMU TLB Data Access Register.	398	/** Write IMMU TLB Data Access Register.
396	* @param tlb TLB number (one of TLB_ISMALL or TLB_IBIG)	399	* @param tlb TLB number (one of TLB_ISMALL or TLB_IBIG)
397	* @param entry TLB Entry index.	400	* @param entry TLB Entry index.
398	* @param value Value to be written.	401	* @param value Value to be written.
399	*/	402	*/
400	static inline void itlb_data_access_write(int tlb, index_t entry,	403	static inline void itlb_data_access_write(int tlb, index_t entry,
401	uint64_t value)	404	uint64_t value)
402	{	405	{
403	itlb_data_access_addr_t reg;	406	itlb_data_access_addr_t reg;
404		407
405	reg.value = 0;	408	reg.value = 0;
406	reg.tlb_number = tlb;	409	reg.tlb_number = tlb;
407	reg.local_tlb_entry = entry;	410	reg.local_tlb_entry = entry;
408	asi_u64_write(ASI_ITLB_DATA_ACCESS_REG, reg.value, value);	411	asi_u64_write(ASI_ITLB_DATA_ACCESS_REG, reg.value, value);
409	flush_pipeline();	412	flush_pipeline();
410	}	413	}
411		414
412	/** Read DMMU TLB Data Access Register.	415	/** Read DMMU TLB Data Access Register.
413	*	416	*
414	* @param tlb TLB number (one of TLB_DSMALL, TLB_DBIG, TLB_DBIG)	417	* @param tlb TLB number (one of TLB_DSMALL, TLB_DBIG, TLB_DBIG)
415	* @param entry TLB Entry index.	418	* @param entry TLB Entry index.
416	*	419	*
417	* @return Current value of specified DMMU TLB Data Access	420	* @return Current value of specified DMMU TLB Data Access
418	* Register.	421	* Register.
419	*/	422	*/
420	static inline uint64_t dtlb_data_access_read(int tlb, index_t entry)	423	static inline uint64_t dtlb_data_access_read(int tlb, index_t entry)
421	{	424	{
422	dtlb_data_access_addr_t reg;	425	dtlb_data_access_addr_t reg;
423		426
424	reg.value = 0;	427	reg.value = 0;
425	reg.tlb_number = tlb;	428	reg.tlb_number = tlb;
426	reg.local_tlb_entry = entry;	429	reg.local_tlb_entry = entry;
427	return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value);	430	return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value);
428	}	431	}
429		432
430	/** Write DMMU TLB Data Access Register.	433	/** Write DMMU TLB Data Access Register.
431	*	434	*
432	* @param tlb TLB number (one of TLB_DSMALL, TLB_DBIG_0, TLB_DBIG_1)	435	* @param tlb TLB number (one of TLB_DSMALL, TLB_DBIG_0, TLB_DBIG_1)
433	* @param entry TLB Entry index.	436	* @param entry TLB Entry index.
434	* @param value Value to be written.	437	* @param value Value to be written.
435	*/	438	*/
436	static inline void dtlb_data_access_write(int tlb, index_t entry,	439	static inline void dtlb_data_access_write(int tlb, index_t entry,
437	uint64_t value)	440	uint64_t value)
438	{	441	{
439	dtlb_data_access_addr_t reg;	442	dtlb_data_access_addr_t reg;
440		443
441	reg.value = 0;	444	reg.value = 0;
442	reg.tlb_number = tlb;	445	reg.tlb_number = tlb;
443	reg.local_tlb_entry = entry;	446	reg.local_tlb_entry = entry;
444	asi_u64_write(ASI_DTLB_DATA_ACCESS_REG, reg.value, value);	447	asi_u64_write(ASI_DTLB_DATA_ACCESS_REG, reg.value, value);
445	membar();	448	membar();
446	}	449	}
447		450
448	/** Read IMMU TLB Tag Read Register.	451	/** Read IMMU TLB Tag Read Register.
449	*	452	*
450	* @param tlb TLB number (one of TLB_ISMALL or TLB_IBIG)	453	* @param tlb TLB number (one of TLB_ISMALL or TLB_IBIG)
451	* @param entry TLB Entry index.	454	* @param entry TLB Entry index.
452	*	455	*
453	* @return Current value of specified IMMU TLB Tag Read Register.	456	* @return Current value of specified IMMU TLB Tag Read Register.
454	*/	457	*/
455	static inline uint64_t itlb_tag_read_read(int tlb, index_t entry)	458	static inline uint64_t itlb_tag_read_read(int tlb, index_t entry)
456	{	459	{
457	itlb_tag_read_addr_t tag;	460	itlb_tag_read_addr_t tag;
458		461
459	tag.value = 0;	462	tag.value = 0;
460	tag.tlb_number = tlb;	463	tag.tlb_number = tlb;
461	tag.local_tlb_entry = entry;	464	tag.local_tlb_entry = entry;
462	return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value);	465	return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value);
463	}	466	}
464		467
465	/** Read DMMU TLB Tag Read Register.	468	/** Read DMMU TLB Tag Read Register.
466	*	469	*
467	* @param tlb TLB number (one of TLB_DSMALL, TLB_DBIG_0, TLB_DBIG_1)	470	* @param tlb TLB number (one of TLB_DSMALL, TLB_DBIG_0, TLB_DBIG_1)
468	* @param entry TLB Entry index.	471	* @param entry TLB Entry index.
469	*	472	*
470	* @return Current value of specified DMMU TLB Tag Read Register.	473	* @return Current value of specified DMMU TLB Tag Read Register.
471	*/	474	*/
472	static inline uint64_t dtlb_tag_read_read(int tlb, index_t entry)	475	static inline uint64_t dtlb_tag_read_read(int tlb, index_t entry)
473	{	476	{
474	dtlb_tag_read_addr_t tag;	477	dtlb_tag_read_addr_t tag;
475		478
476	tag.value = 0;	479	tag.value = 0;
477	tag.tlb_number = tlb;	480	tag.tlb_number = tlb;
478	tag.local_tlb_entry = entry;	481	tag.local_tlb_entry = entry;
479	return asi_u64_read(ASI_DTLB_TAG_READ_REG, tag.value);	482	return asi_u64_read(ASI_DTLB_TAG_READ_REG, tag.value);
480	}	483	}
481		484
482	#endif	485	#endif
483		486
484		487
485	/** Write IMMU TLB Tag Access Register.	488	/** Write IMMU TLB Tag Access Register.
486	*	489	*
487	* @param v Value to be written.	490	* @param v Value to be written.
488	*/	491	*/
489	static inline void itlb_tag_access_write(uint64_t v)	492	static inline void itlb_tag_access_write(uint64_t v)
490	{	493	{
491	asi_u64_write(ASI_IMMU, VA_IMMU_TAG_ACCESS, v);	494	asi_u64_write(ASI_IMMU, VA_IMMU_TAG_ACCESS, v);
492	flush_pipeline();	495	flush_pipeline();
493	}	496	}
494		497
495	/** Read IMMU TLB Tag Access Register.	498	/** Read IMMU TLB Tag Access Register.
496	*	499	*
497	* @return Current value of IMMU TLB Tag Access Register.	500	* @return Current value of IMMU TLB Tag Access Register.

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(root)/branches/sparc/kernel/arch/sparc64/include/mm/sun4v/tlb.h – Rev 3771 → 3835