WebSVN – HelenOS – Diff – /branches/sparc/kernel/arch/sparc64/include/mm/sun4u/tlb.h


/*
 * Copyright (c) 2005 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup sparc64mm  
 * @{
 */
/** @file
 */
 
#ifndef KERN_sparc64_sun4u_TLB_H_
#define KERN_sparc64_sun4u_TLB_H_
 
#if defined (US)
#define ITLB_ENTRY_COUNT        64
#define DTLB_ENTRY_COUNT        64
#define DTLB_MAX_LOCKED_ENTRIES     DTLB_ENTRY_COUNT
#endif
 
/** TLB_DSMALL is the only of the three DMMUs that can hold locked entries. */
#if defined (US3)
#define DTLB_MAX_LOCKED_ENTRIES     16
#endif
 
#define MEM_CONTEXT_KERNEL      0
#define MEM_CONTEXT_TEMP        1
 
/** Bit width of the TLB-locked portion of kernel address space. */
#define KERNEL_PAGE_WIDTH       22  /* 4M */
 
/* TLB Demap Operation types. */
#define TLB_DEMAP_PAGE      0
#define TLB_DEMAP_CONTEXT   1
#if defined (US3)
#define TLB_DEMAP_ALL       2
#endif
 
#define TLB_DEMAP_TYPE_SHIFT    6
 
/* TLB Demap Operation Context register encodings. */
#define TLB_DEMAP_PRIMARY   0
#define TLB_DEMAP_SECONDARY 1
#define TLB_DEMAP_NUCLEUS   2
 
/* There are more TLBs in one MMU in US3, their codes are defined here. */
#if defined (US3)
/* D-MMU: one small (16-entry) TLB and two big (512-entry) TLBs */
#define TLB_DSMALL  0
#define TLB_DBIG_0  2
#define TLB_DBIG_1  3
   
/* I-MMU: one small (16-entry) TLB and one big TLB */
#define TLB_ISMALL  0
#define TLB_IBIG    2
#endif
 
#define TLB_DEMAP_CONTEXT_SHIFT 4
 
/* TLB Tag Access shifts */
#define TLB_TAG_ACCESS_CONTEXT_SHIFT    0
#define TLB_TAG_ACCESS_CONTEXT_MASK ((1 << 13) - 1)
#define TLB_TAG_ACCESS_VPN_SHIFT    13
 
#ifndef __ASM__
 
#include <arch/mm/tte.h>
#include <arch/mm/mmu.h>
#include <arch/mm/page.h>
#include <arch/asm.h>
#include <arch/barrier.h>
#include <arch/types.h>
#include <arch/register.h>
#include <arch/cpu.h>
 
union tlb_context_reg {
    uint64_t v;
    struct {
        unsigned long : 51;
        unsigned context : 13;      /**< Context/ASID. */
    } __attribute__ ((packed));
};
typedef union tlb_context_reg tlb_context_reg_t;
 
/** I-/D-TLB Data In/Access Register type. */
typedef tte_data_t tlb_data_t;
 
/** I-/D-TLB Data Access Address in Alternate Space. */
 
#if defined (US)
 
union tlb_data_access_addr {
    uint64_t value;
    struct {
        uint64_t : 55;
        unsigned tlb_entry : 6;
        unsigned : 3;
    } __attribute__ ((packed));
};
typedef union tlb_data_access_addr dtlb_data_access_addr_t;
typedef union tlb_data_access_addr dtlb_tag_read_addr_t;
typedef union tlb_data_access_addr itlb_data_access_addr_t;
typedef union tlb_data_access_addr itlb_tag_read_addr_t;
 
#elif defined (US3)
 
/*
 * In US3, I-MMU and D-MMU have different formats of the data
 * access register virtual address. In the corresponding
 * structures the member variable for the entry number is
 * called "local_tlb_entry" - it contrasts with the "tlb_entry"
 * for the US data access register VA structure. The rationale
 * behind this is to prevent careless mistakes in the code
 * caused by setting only the entry number and not the TLB
 * number in the US3 code (when taking the code from US).
 */
 
union dtlb_data_access_addr {
    uint64_t value;
    struct {
        uint64_t : 45;
        unsigned : 1;
        unsigned tlb_number : 2;
        unsigned : 4;
        unsigned local_tlb_entry : 9;
        unsigned : 3;
    } __attribute__ ((packed));
};
typedef union dtlb_data_access_addr dtlb_data_access_addr_t;
typedef union dtlb_data_access_addr dtlb_tag_read_addr_t;
 
union itlb_data_access_addr {
    uint64_t value;
    struct {
        uint64_t : 45;
        unsigned : 1;
        unsigned tlb_number : 2;
        unsigned : 6;
        unsigned local_tlb_entry : 7;
        unsigned : 3;
    } __attribute__ ((packed));
};
typedef union itlb_data_access_addr itlb_data_access_addr_t;
typedef union itlb_data_access_addr itlb_tag_read_addr_t;
 
#endif
 
/** I-/D-TLB Tag Read Register. */
union tlb_tag_read_reg {
    uint64_t value;
    struct {
        uint64_t vpn : 51;  /**< Virtual Address bits 63:13. */
        unsigned context : 13;  /**< Context identifier. */
    } __attribute__ ((packed));
};
typedef union tlb_tag_read_reg tlb_tag_read_reg_t;
typedef union tlb_tag_read_reg tlb_tag_access_reg_t;
 
 
/** TLB Demap Operation Address. */
union tlb_demap_addr {
    uint64_t value;
    struct {
        uint64_t vpn: 51;   /**< Virtual Address bits 63:13. */
#if defined (US)
        unsigned : 6;       /**< Ignored. */
        unsigned type : 1;  /**< The type of demap operation. */
#elif defined (US3)
        unsigned : 5;       /**< Ignored. */
        unsigned type: 2;   /**< The type of demap operation. */
#endif
        unsigned context : 2;   /**< Context register selection. */
        unsigned : 4;       /**< Zero. */
    } __attribute__ ((packed));
};
typedef union tlb_demap_addr tlb_demap_addr_t;
 
/** TLB Synchronous Fault Status Register. */
union tlb_sfsr_reg {
    uint64_t value;
    struct {
#if defined (US)
        unsigned long : 40; /**< Implementation dependent. */
        unsigned asi : 8;   /**< ASI. */
        unsigned : 2;
        unsigned ft : 7;    /**< Fault type. */
#elif defined (US3)
        unsigned long : 39; /**< Implementation dependent. */
        unsigned nf : 1;    /**< Non-faulting load. */
        unsigned asi : 8;   /**< ASI. */
        unsigned tm : 1;    /**< I-TLB miss. */
        unsigned : 3;       /**< Reserved. */
        unsigned ft : 5;    /**< Fault type. */
#endif
        unsigned e : 1;     /**< Side-effect bit. */
        unsigned ct : 2;    /**< Context Register selection. */
        unsigned pr : 1;    /**< Privilege bit. */
        unsigned w : 1;     /**< Write bit. */
        unsigned ow : 1;    /**< Overwrite bit. */
        unsigned fv : 1;    /**< Fault Valid bit. */
    } __attribute__ ((packed));
};
typedef union tlb_sfsr_reg tlb_sfsr_reg_t;
 
#if defined (US3)
 
/*
 * Functions for determining the number of entries in TLBs. They either return
 * a constant value or a value based on the CPU autodetection.
 */
 
/**
 * Determine the number of entries in the DMMU's small TLB.
 */
static inline uint16_t tlb_dsmall_size(void)
{
    return 16;
}
 
/**
 * Determine the number of entries in each DMMU's big TLB.
 */
static inline uint16_t tlb_dbig_size(void)
{
    return 512;
}
 
/**
 * Determine the number of entries in the IMMU's small TLB.
 */
static inline uint16_t tlb_ismall_size(void)
{
    return 16;
}
 
/**
 * Determine the number of entries in the IMMU's big TLB.
 */
static inline uint16_t tlb_ibig_size(void)
{
    if (((ver_reg_t) ver_read()).impl == IMPL_ULTRASPARCIV_PLUS)
        return 512;
    else
        return 128;
}
 
#endif
 
/** Read MMU Primary Context Register.
 *
 * @return      Current value of Primary Context Register.
 */
static inline uint64_t mmu_primary_context_read(void)
{
    return asi_u64_read(ASI_DMMU, VA_PRIMARY_CONTEXT_REG);
}
 
/** Write MMU Primary Context Register.
 *
 * @param v     New value of Primary Context Register.
 */
static inline void mmu_primary_context_write(uint64_t v)
{
    asi_u64_write(ASI_DMMU, VA_PRIMARY_CONTEXT_REG, v);
    flush_pipeline();
}
 
/** Read MMU Secondary Context Register.
 *
 * @return      Current value of Secondary Context Register.
 */
static inline uint64_t mmu_secondary_context_read(void)
{
    return asi_u64_read(ASI_DMMU, VA_SECONDARY_CONTEXT_REG);
}
 
/** Write MMU Primary Context Register.
 *
 * @param v     New value of Primary Context Register.
 */
static inline void mmu_secondary_context_write(uint64_t v)
{
    asi_u64_write(ASI_DMMU, VA_SECONDARY_CONTEXT_REG, v);
    flush_pipeline();
}
 
#if defined (US)
 
/** Read IMMU TLB Data Access Register.
 *
 * @param entry     TLB Entry index.
 *
 * @return      Current value of specified IMMU TLB Data Access
 *          Register.
 */
static inline uint64_t itlb_data_access_read(index_t entry)
{
    itlb_data_access_addr_t reg;
   
    reg.value = 0;
    reg.tlb_entry = entry;
    return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value);
}
 
/** Write IMMU TLB Data Access Register.
 *
 * @param entry     TLB Entry index.
 * @param value     Value to be written.
 */
static inline void itlb_data_access_write(index_t entry, uint64_t value)
{
    itlb_data_access_addr_t reg;
   
    reg.value = 0;
    reg.tlb_entry = entry;
    asi_u64_write(ASI_ITLB_DATA_ACCESS_REG, reg.value, value);
    flush_pipeline();
}
 
/** Read DMMU TLB Data Access Register.
 *
 * @param entry     TLB Entry index.
 *
 * @return      Current value of specified DMMU TLB Data Access
 *          Register.
 */
static inline uint64_t dtlb_data_access_read(index_t entry)
{
    dtlb_data_access_addr_t reg;
   
    reg.value = 0;
    reg.tlb_entry = entry;
    return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value);
}
 
/** Write DMMU TLB Data Access Register.
 *
 * @param entry     TLB Entry index.
 * @param value     Value to be written.
 */
static inline void dtlb_data_access_write(index_t entry, uint64_t value)
{
    dtlb_data_access_addr_t reg;
   
    reg.value = 0;
    reg.tlb_entry = entry;
    asi_u64_write(ASI_DTLB_DATA_ACCESS_REG, reg.value, value);
    membar();
}
 
/** Read IMMU TLB Tag Read Register.
 *
 * @param entry     TLB Entry index.
 *
 * @return      Current value of specified IMMU TLB Tag Read Register.
 */
static inline uint64_t itlb_tag_read_read(index_t entry)
{
    itlb_tag_read_addr_t tag;
 
    tag.value = 0;
    tag.tlb_entry = entry;
    return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value);
}
 
/** Read DMMU TLB Tag Read Register.
 *
 * @param entry     TLB Entry index.
 *
 * @return      Current value of specified DMMU TLB Tag Read Register.
 */
static inline uint64_t dtlb_tag_read_read(index_t entry)
{
    dtlb_tag_read_addr_t tag;
 
    tag.value = 0;
    tag.tlb_entry = entry;
    return asi_u64_read(ASI_DTLB_TAG_READ_REG, tag.value);
}
 
#elif defined (US3)
 
 
/** Read IMMU TLB Data Access Register.
 *
 * @param tlb       TLB number (one of TLB_ISMALL or TLB_IBIG)
 * @param entry     TLB Entry index.
 *
 * @return      Current value of specified IMMU TLB Data Access
 *          Register.
 */
static inline uint64_t itlb_data_access_read(int tlb, index_t entry)
{
    itlb_data_access_addr_t reg;
   
    reg.value = 0;
    reg.tlb_number = tlb;
    reg.local_tlb_entry = entry;
    return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value);
}
 
/** Write IMMU TLB Data Access Register.
 * @param tlb       TLB number (one of TLB_ISMALL or TLB_IBIG)
 * @param entry     TLB Entry index.
 * @param value     Value to be written.
 */
static inline void itlb_data_access_write(int tlb, index_t entry,
    uint64_t value)
{
    itlb_data_access_addr_t reg;
   
    reg.value = 0;
    reg.tlb_number = tlb;
    reg.local_tlb_entry = entry;
    asi_u64_write(ASI_ITLB_DATA_ACCESS_REG, reg.value, value);
    flush_pipeline();
}
 
/** Read DMMU TLB Data Access Register.
 *
 * @param tlb       TLB number (one of TLB_DSMALL, TLB_DBIG, TLB_DBIG)
 * @param entry     TLB Entry index.
 *
 * @return      Current value of specified DMMU TLB Data Access
 *          Register.
 */
static inline uint64_t dtlb_data_access_read(int tlb, index_t entry)
{
    dtlb_data_access_addr_t reg;
   
    reg.value = 0;
    reg.tlb_number = tlb;
    reg.local_tlb_entry = entry;
    return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value);
}
 
/** Write DMMU TLB Data Access Register.
 *
 * @param tlb       TLB number (one of TLB_DSMALL, TLB_DBIG_0, TLB_DBIG_1)  
 * @param entry     TLB Entry index.
 * @param value     Value to be written.
 */
static inline void dtlb_data_access_write(int tlb, index_t entry,
    uint64_t value)
{
    dtlb_data_access_addr_t reg;
   
    reg.value = 0;
    reg.tlb_number = tlb;
    reg.local_tlb_entry = entry;
    asi_u64_write(ASI_DTLB_DATA_ACCESS_REG, reg.value, value);
    membar();
}
 
/** Read IMMU TLB Tag Read Register.
 *
 * @param tlb       TLB number (one of TLB_ISMALL or TLB_IBIG)
 * @param entry     TLB Entry index.
 *
 * @return      Current value of specified IMMU TLB Tag Read Register.
 */
static inline uint64_t itlb_tag_read_read(int tlb, index_t entry)
{
    itlb_tag_read_addr_t tag;
 
    tag.value = 0;
    tag.tlb_number = tlb;
    tag.local_tlb_entry = entry;
    return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value);
}
 
/** Read DMMU TLB Tag Read Register.
 *
 * @param tlb       TLB number (one of TLB_DSMALL, TLB_DBIG_0, TLB_DBIG_1)
 * @param entry     TLB Entry index.
 *
 * @return      Current value of specified DMMU TLB Tag Read Register.
 */
static inline uint64_t dtlb_tag_read_read(int tlb, index_t entry)
{
    dtlb_tag_read_addr_t tag;
 
    tag.value = 0;
    tag.tlb_number = tlb;
    tag.local_tlb_entry = entry;
    return asi_u64_read(ASI_DTLB_TAG_READ_REG, tag.value);
}
 
#endif
 
 
/** Write IMMU TLB Tag Access Register.
 *
 * @param v     Value to be written.
 */
static inline void itlb_tag_access_write(uint64_t v)
{
    asi_u64_write(ASI_IMMU, VA_IMMU_TAG_ACCESS, v);
    flush_pipeline();
}
 
/** Read IMMU TLB Tag Access Register.
 *
 * @return      Current value of IMMU TLB Tag Access Register.
 */
static inline uint64_t itlb_tag_access_read(void)
{
    return asi_u64_read(ASI_IMMU, VA_IMMU_TAG_ACCESS);
}
 
/** Write DMMU TLB Tag Access Register.
 *
 * @param v     Value to be written.
 */
static inline void dtlb_tag_access_write(uint64_t v)
{
    asi_u64_write(ASI_DMMU, VA_DMMU_TAG_ACCESS, v);
    membar();
}
 
/** Read DMMU TLB Tag Access Register.
 *
 * @return      Current value of DMMU TLB Tag Access Register.
 */
static inline uint64_t dtlb_tag_access_read(void)
{
    return asi_u64_read(ASI_DMMU, VA_DMMU_TAG_ACCESS);
}
 
 
/** Write IMMU TLB Data in Register.
 *
 * @param v     Value to be written.
 */
static inline void itlb_data_in_write(uint64_t v)
{
    asi_u64_write(ASI_ITLB_DATA_IN_REG, 0, v);
    flush_pipeline();
}
 
/** Write DMMU TLB Data in Register.
 *
 * @param v     Value to be written.
 */
static inline void dtlb_data_in_write(uint64_t v)
{
    asi_u64_write(ASI_DTLB_DATA_IN_REG, 0, v);
    membar();
}
 
/** Read ITLB Synchronous Fault Status Register.
 *
 * @return      Current content of I-SFSR register.
 */
static inline uint64_t itlb_sfsr_read(void)
{
    return asi_u64_read(ASI_IMMU, VA_IMMU_SFSR);
}
 
/** Write ITLB Synchronous Fault Status Register.
 *
 * @param v     New value of I-SFSR register.
 */
static inline void itlb_sfsr_write(uint64_t v)
{
    asi_u64_write(ASI_IMMU, VA_IMMU_SFSR, v);
    flush_pipeline();
}
 
/** Read DTLB Synchronous Fault Status Register.
 *
 * @return      Current content of D-SFSR register.
 */
static inline uint64_t dtlb_sfsr_read(void)
{
    return asi_u64_read(ASI_DMMU, VA_DMMU_SFSR);
}
 
/** Write DTLB Synchronous Fault Status Register.
 *
 * @param v     New value of D-SFSR register.
 */
static inline void dtlb_sfsr_write(uint64_t v)
{
    asi_u64_write(ASI_DMMU, VA_DMMU_SFSR, v);
    membar();
}
 
/** Read DTLB Synchronous Fault Address Register.
 *
 * @return      Current content of D-SFAR register.
 */
static inline uint64_t dtlb_sfar_read(void)
{
    return asi_u64_read(ASI_DMMU, VA_DMMU_SFAR);
}
 
/** Perform IMMU TLB Demap Operation.
 *
 * @param type      Selects between context and page demap (and entire MMU
 *          demap on US3).
 * @param context_encoding Specifies which Context register has Context ID for
 *          demap.
 * @param page      Address which is on the page to be demapped.
 */
static inline void itlb_demap(int type, int context_encoding, uintptr_t page)
{
    tlb_demap_addr_t da;
    page_address_t pg;
   
    da.value = 0;
    pg.address = page;
   
    da.type = type;
    da.context = context_encoding;
    da.vpn = pg.vpn;
   
    /* da.value is the address within the ASI */
    asi_u64_write(ASI_IMMU_DEMAP, da.value, 0);
 
    flush_pipeline();
}
 
/** Perform DMMU TLB Demap Operation.
 *
 * @param type      Selects between context and page demap (and entire MMU
 *          demap on US3).
 * @param context_encoding Specifies which Context register has Context ID for
 *          demap.
 * @param page      Address which is on the page to be demapped.
 */
static inline void dtlb_demap(int type, int context_encoding, uintptr_t page)
{
    tlb_demap_addr_t da;
    page_address_t pg;
   
    da.value = 0;
    pg.address = page;
   
    da.type = type;
    da.context = context_encoding;
    da.vpn = pg.vpn;
   
    /* da.value is the address within the ASI */
    asi_u64_write(ASI_DMMU_DEMAP, da.value, 0);
 
    membar();
}
 
extern void fast_instruction_access_mmu_miss(unative_t, istate_t *);
extern void fast_data_access_mmu_miss(tlb_tag_access_reg_t, istate_t *);
extern void fast_data_access_protection(tlb_tag_access_reg_t , istate_t *);
 
extern void dtlb_insert_mapping(uintptr_t, uintptr_t, int, bool, bool);
 
extern void describe_mmu_fault(void);
 
#endif /* !def __ASM__ */
 
#endif
 
/** @}
 */
 

Rev 3770	Rev 3862
1	/*	1	/*
2	* Copyright (c) 2005 Jakub Jermar	2	* Copyright (c) 2005 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	/** @addtogroup sparc64mm	29	/** @addtogroup sparc64mm
30	* @{	30	* @{
31	*/	31	*/
32	/** @file	32	/** @file
33	*/	33	*/
34		34
35	#ifndef KERN_sparc64_sun4u_TLB_H_	35	#ifndef KERN_sparc64_sun4u_TLB_H_
36	#define KERN_sparc64_sun4u_TLB_H_	36	#define KERN_sparc64_sun4u_TLB_H_
37		37
38	#if defined (US)	38	#if defined (US)
39	#define ITLB_ENTRY_COUNT 64	39	#define ITLB_ENTRY_COUNT 64
40	#define DTLB_ENTRY_COUNT 64	40	#define DTLB_ENTRY_COUNT 64
41	#define DTLB_MAX_LOCKED_ENTRIES DTLB_ENTRY_COUNT	41	#define DTLB_MAX_LOCKED_ENTRIES DTLB_ENTRY_COUNT
42	#endif	42	#endif
43		43
44	/** TLB_DSMALL is the only of the three DMMUs that can hold locked entries. */	44	/** TLB_DSMALL is the only of the three DMMUs that can hold locked entries. */
45	#if defined (US3)	45	#if defined (US3)
46	#define DTLB_MAX_LOCKED_ENTRIES 16	46	#define DTLB_MAX_LOCKED_ENTRIES 16
47	#endif	47	#endif
48		48
49	#define MEM_CONTEXT_KERNEL 0	49	#define MEM_CONTEXT_KERNEL 0
50	#define MEM_CONTEXT_TEMP 1	50	#define MEM_CONTEXT_TEMP 1
51		51
52	/** Bit width of the TLB-locked portion of kernel address space. */	52	/** Bit width of the TLB-locked portion of kernel address space. */
53	#define KERNEL_PAGE_WIDTH 22 /* 4M */	53	#define KERNEL_PAGE_WIDTH 22 /* 4M */
54		54
55	/* TLB Demap Operation types. */	55	/* TLB Demap Operation types. */
56	#define TLB_DEMAP_PAGE 0	56	#define TLB_DEMAP_PAGE 0
57	#define TLB_DEMAP_CONTEXT 1	57	#define TLB_DEMAP_CONTEXT 1
58	#if defined (US3)	58	#if defined (US3)
59	#define TLB_DEMAP_ALL 2	59	#define TLB_DEMAP_ALL 2
60	#endif	60	#endif
61		61
62	#define TLB_DEMAP_TYPE_SHIFT 6	62	#define TLB_DEMAP_TYPE_SHIFT 6
63		63
64	/* TLB Demap Operation Context register encodings. */	64	/* TLB Demap Operation Context register encodings. */
65	#define TLB_DEMAP_PRIMARY 0	65	#define TLB_DEMAP_PRIMARY 0
66	#define TLB_DEMAP_SECONDARY 1	66	#define TLB_DEMAP_SECONDARY 1
67	#define TLB_DEMAP_NUCLEUS 2	67	#define TLB_DEMAP_NUCLEUS 2
68		68
69	/* There are more TLBs in one MMU in US3, their codes are defined here. */	69	/* There are more TLBs in one MMU in US3, their codes are defined here. */
70	#if defined (US3)	70	#if defined (US3)
71	/* D-MMU: one small (16-entry) TLB and two big (512-entry) TLBs */	71	/* D-MMU: one small (16-entry) TLB and two big (512-entry) TLBs */
72	#define TLB_DSMALL 0	72	#define TLB_DSMALL 0
73	#define TLB_DBIG_0 2	73	#define TLB_DBIG_0 2
74	#define TLB_DBIG_1 3	74	#define TLB_DBIG_1 3
75		75
76	/* I-MMU: one small (16-entry) TLB and one big TLB */	76	/* I-MMU: one small (16-entry) TLB and one big TLB */
77	#define TLB_ISMALL 0	77	#define TLB_ISMALL 0
78	#define TLB_IBIG 2	78	#define TLB_IBIG 2
79	#endif	79	#endif
80		80
81	#define TLB_DEMAP_CONTEXT_SHIFT 4	81	#define TLB_DEMAP_CONTEXT_SHIFT 4
82		82
83	/* TLB Tag Access shifts */	83	/* TLB Tag Access shifts */
84	#define TLB_TAG_ACCESS_CONTEXT_SHIFT 0	84	#define TLB_TAG_ACCESS_CONTEXT_SHIFT 0
85	#define TLB_TAG_ACCESS_CONTEXT_MASK ((1 << 13) - 1)	85	#define TLB_TAG_ACCESS_CONTEXT_MASK ((1 << 13) - 1)
86	#define TLB_TAG_ACCESS_VPN_SHIFT 13	86	#define TLB_TAG_ACCESS_VPN_SHIFT 13
87		87
88	#ifndef __ASM__	88	#ifndef __ASM__
89		89
90	#include <arch/mm/sun4u/tte.h>	90	#include <arch/mm/tte.h>
91	#include <arch/mm/sun4u/mmu.h>	91	#include <arch/mm/mmu.h>
92	#include <arch/mm/page.h>	92	#include <arch/mm/page.h>
93	#include <arch/asm.h>	93	#include <arch/asm.h>
94	#include <arch/barrier.h>	94	#include <arch/barrier.h>
95	#include <arch/types.h>	95	#include <arch/types.h>
96	#include <arch/register.h>	96	#include <arch/register.h>
97	#include <arch/sun4u/cpu.h>	97	#include <arch/cpu.h>
98		98
99	union tlb_context_reg {	99	union tlb_context_reg {
100	uint64_t v;	100	uint64_t v;
101	struct {	101	struct {
102	unsigned long : 51;	102	unsigned long : 51;
103	unsigned context : 13; /*< Context/ASID. /	103	unsigned context : 13; /*< Context/ASID. /
104	} __attribute__ ((packed));	104	} __attribute__ ((packed));
105	};	105	};
106	typedef union tlb_context_reg tlb_context_reg_t;	106	typedef union tlb_context_reg tlb_context_reg_t;
107		107
108	/** I-/D-TLB Data In/Access Register type. */	108	/** I-/D-TLB Data In/Access Register type. */
109	typedef tte_data_t tlb_data_t;	109	typedef tte_data_t tlb_data_t;
110		110
111	/** I-/D-TLB Data Access Address in Alternate Space. */	111	/** I-/D-TLB Data Access Address in Alternate Space. */
112		112
113	#if defined (US)	113	#if defined (US)
114		114
115	union tlb_data_access_addr {	115	union tlb_data_access_addr {
116	uint64_t value;	116	uint64_t value;
117	struct {	117	struct {
118	uint64_t : 55;	118	uint64_t : 55;
119	unsigned tlb_entry : 6;	119	unsigned tlb_entry : 6;
120	unsigned : 3;	120	unsigned : 3;
121	} __attribute__ ((packed));	121	} __attribute__ ((packed));
122	};	122	};
123	typedef union tlb_data_access_addr dtlb_data_access_addr_t;	123	typedef union tlb_data_access_addr dtlb_data_access_addr_t;
124	typedef union tlb_data_access_addr dtlb_tag_read_addr_t;	124	typedef union tlb_data_access_addr dtlb_tag_read_addr_t;
125	typedef union tlb_data_access_addr itlb_data_access_addr_t;	125	typedef union tlb_data_access_addr itlb_data_access_addr_t;
126	typedef union tlb_data_access_addr itlb_tag_read_addr_t;	126	typedef union tlb_data_access_addr itlb_tag_read_addr_t;
127		127
128	#elif defined (US3)	128	#elif defined (US3)
129		129
130	/*	130	/*
131	* In US3, I-MMU and D-MMU have different formats of the data	131	* In US3, I-MMU and D-MMU have different formats of the data
132	* access register virtual address. In the corresponding	132	* access register virtual address. In the corresponding
133	* structures the member variable for the entry number is	133	* structures the member variable for the entry number is
134	* called "local_tlb_entry" - it contrasts with the "tlb_entry"	134	* called "local_tlb_entry" - it contrasts with the "tlb_entry"
135	* for the US data access register VA structure. The rationale	135	* for the US data access register VA structure. The rationale
136	* behind this is to prevent careless mistakes in the code	136	* behind this is to prevent careless mistakes in the code
137	* caused by setting only the entry number and not the TLB	137	* caused by setting only the entry number and not the TLB
138	* number in the US3 code (when taking the code from US).	138	* number in the US3 code (when taking the code from US).
139	*/	139	*/
140		140
141	union dtlb_data_access_addr {	141	union dtlb_data_access_addr {
142	uint64_t value;	142	uint64_t value;
143	struct {	143	struct {
144	uint64_t : 45;	144	uint64_t : 45;
145	unsigned : 1;	145	unsigned : 1;
146	unsigned tlb_number : 2;	146	unsigned tlb_number : 2;
147	unsigned : 4;	147	unsigned : 4;
148	unsigned local_tlb_entry : 9;	148	unsigned local_tlb_entry : 9;
149	unsigned : 3;	149	unsigned : 3;
150	} __attribute__ ((packed));	150	} __attribute__ ((packed));
151	};	151	};
152	typedef union dtlb_data_access_addr dtlb_data_access_addr_t;	152	typedef union dtlb_data_access_addr dtlb_data_access_addr_t;
153	typedef union dtlb_data_access_addr dtlb_tag_read_addr_t;	153	typedef union dtlb_data_access_addr dtlb_tag_read_addr_t;
154		154
155	union itlb_data_access_addr {	155	union itlb_data_access_addr {
156	uint64_t value;	156	uint64_t value;
157	struct {	157	struct {
158	uint64_t : 45;	158	uint64_t : 45;
159	unsigned : 1;	159	unsigned : 1;
160	unsigned tlb_number : 2;	160	unsigned tlb_number : 2;
161	unsigned : 6;	161	unsigned : 6;
162	unsigned local_tlb_entry : 7;	162	unsigned local_tlb_entry : 7;
163	unsigned : 3;	163	unsigned : 3;
164	} __attribute__ ((packed));	164	} __attribute__ ((packed));
165	};	165	};
166	typedef union itlb_data_access_addr itlb_data_access_addr_t;	166	typedef union itlb_data_access_addr itlb_data_access_addr_t;
167	typedef union itlb_data_access_addr itlb_tag_read_addr_t;	167	typedef union itlb_data_access_addr itlb_tag_read_addr_t;
168		168
169	#endif	169	#endif
170		170
171	/** I-/D-TLB Tag Read Register. */	171	/** I-/D-TLB Tag Read Register. */
172	union tlb_tag_read_reg {	172	union tlb_tag_read_reg {
173	uint64_t value;	173	uint64_t value;
174	struct {	174	struct {
175	uint64_t vpn : 51; /*< Virtual Address bits 63:13. /	175	uint64_t vpn : 51; /*< Virtual Address bits 63:13. /
176	unsigned context : 13; /*< Context identifier. /	176	unsigned context : 13; /*< Context identifier. /
177	} __attribute__ ((packed));	177	} __attribute__ ((packed));
178	};	178	};
179	typedef union tlb_tag_read_reg tlb_tag_read_reg_t;	179	typedef union tlb_tag_read_reg tlb_tag_read_reg_t;
180	typedef union tlb_tag_read_reg tlb_tag_access_reg_t;	180	typedef union tlb_tag_read_reg tlb_tag_access_reg_t;
181		181
182		182
183	/** TLB Demap Operation Address. */	183	/** TLB Demap Operation Address. */
184	union tlb_demap_addr {	184	union tlb_demap_addr {
185	uint64_t value;	185	uint64_t value;
186	struct {	186	struct {
187	uint64_t vpn: 51; /*< Virtual Address bits 63:13. /	187	uint64_t vpn: 51; /*< Virtual Address bits 63:13. /
188	#if defined (US)	188	#if defined (US)
189	unsigned : 6; /*< Ignored. /	189	unsigned : 6; /*< Ignored. /
190	unsigned type : 1; /*< The type of demap operation. /	190	unsigned type : 1; /*< The type of demap operation. /
191	#elif defined (US3)	191	#elif defined (US3)
192	unsigned : 5; /*< Ignored. /	192	unsigned : 5; /*< Ignored. /
193	unsigned type: 2; /*< The type of demap operation. /	193	unsigned type: 2; /*< The type of demap operation. /
194	#endif	194	#endif
195	unsigned context : 2; /*< Context register selection. /	195	unsigned context : 2; /*< Context register selection. /
196	unsigned : 4; /*< Zero. /	196	unsigned : 4; /*< Zero. /
197	} __attribute__ ((packed));	197	} __attribute__ ((packed));
198	};	198	};
199	typedef union tlb_demap_addr tlb_demap_addr_t;	199	typedef union tlb_demap_addr tlb_demap_addr_t;
200		200
201	/** TLB Synchronous Fault Status Register. */	201	/** TLB Synchronous Fault Status Register. */
202	union tlb_sfsr_reg {	202	union tlb_sfsr_reg {
203	uint64_t value;	203	uint64_t value;
204	struct {	204	struct {
205	#if defined (US)	205	#if defined (US)
206	unsigned long : 40; /*< Implementation dependent. /	206	unsigned long : 40; /*< Implementation dependent. /
207	unsigned asi : 8; /*< ASI. /	207	unsigned asi : 8; /*< ASI. /
208	unsigned : 2;	208	unsigned : 2;
209	unsigned ft : 7; /*< Fault type. /	209	unsigned ft : 7; /*< Fault type. /
210	#elif defined (US3)	210	#elif defined (US3)
211	unsigned long : 39; /*< Implementation dependent. /	211	unsigned long : 39; /*< Implementation dependent. /
212	unsigned nf : 1; /*< Non-faulting load. /	212	unsigned nf : 1; /*< Non-faulting load. /
213	unsigned asi : 8; /*< ASI. /	213	unsigned asi : 8; /*< ASI. /
214	unsigned tm : 1; /*< I-TLB miss. /	214	unsigned tm : 1; /*< I-TLB miss. /
215	unsigned : 3; /*< Reserved. /	215	unsigned : 3; /*< Reserved. /
216	unsigned ft : 5; /*< Fault type. /	216	unsigned ft : 5; /*< Fault type. /
217	#endif	217	#endif
218	unsigned e : 1; /*< Side-effect bit. /	218	unsigned e : 1; /*< Side-effect bit. /
219	unsigned ct : 2; /*< Context Register selection. /	219	unsigned ct : 2; /*< Context Register selection. /
220	unsigned pr : 1; /*< Privilege bit. /	220	unsigned pr : 1; /*< Privilege bit. /
221	unsigned w : 1; /*< Write bit. /	221	unsigned w : 1; /*< Write bit. /
222	unsigned ow : 1; /*< Overwrite bit. /	222	unsigned ow : 1; /*< Overwrite bit. /
223	unsigned fv : 1; /*< Fault Valid bit. /	223	unsigned fv : 1; /*< Fault Valid bit. /
224	} __attribute__ ((packed));	224	} __attribute__ ((packed));
225	};	225	};
226	typedef union tlb_sfsr_reg tlb_sfsr_reg_t;	226	typedef union tlb_sfsr_reg tlb_sfsr_reg_t;
227		227
228	#if defined (US3)	228	#if defined (US3)
229		229
230	/*	230	/*
231	* Functions for determining the number of entries in TLBs. They either return	231	* Functions for determining the number of entries in TLBs. They either return
232	* a constant value or a value based on the CPU autodetection.	232	* a constant value or a value based on the CPU autodetection.
233	*/	233	*/
234		234
235	/**	235	/**
236	* Determine the number of entries in the DMMU's small TLB.	236	* Determine the number of entries in the DMMU's small TLB.
237	*/	237	*/
238	static inline uint16_t tlb_dsmall_size(void)	238	static inline uint16_t tlb_dsmall_size(void)
239	{	239	{
240	return 16;	240	return 16;
241	}	241	}
242		242
243	/**	243	/**
244	* Determine the number of entries in each DMMU's big TLB.	244	* Determine the number of entries in each DMMU's big TLB.
245	*/	245	*/
246	static inline uint16_t tlb_dbig_size(void)	246	static inline uint16_t tlb_dbig_size(void)
247	{	247	{
248	return 512;	248	return 512;
249	}	249	}
250		250
251	/**	251	/**
252	* Determine the number of entries in the IMMU's small TLB.	252	* Determine the number of entries in the IMMU's small TLB.
253	*/	253	*/
254	static inline uint16_t tlb_ismall_size(void)	254	static inline uint16_t tlb_ismall_size(void)
255	{	255	{
256	return 16;	256	return 16;
257	}	257	}
258		258
259	/**	259	/**
260	* Determine the number of entries in the IMMU's big TLB.	260	* Determine the number of entries in the IMMU's big TLB.
261	*/	261	*/
262	static inline uint16_t tlb_ibig_size(void)	262	static inline uint16_t tlb_ibig_size(void)
263	{	263	{
264	if (((ver_reg_t) ver_read()).impl == IMPL_ULTRASPARCIV_PLUS)	264	if (((ver_reg_t) ver_read()).impl == IMPL_ULTRASPARCIV_PLUS)
265	return 512;	265	return 512;
266	else	266	else
267	return 128;	267	return 128;
268	}	268	}
269		269
270	#endif	270	#endif
271		271
272	/** Read MMU Primary Context Register.	272	/** Read MMU Primary Context Register.
273	*	273	*
274	* @return Current value of Primary Context Register.	274	* @return Current value of Primary Context Register.
275	*/	275	*/
276	static inline uint64_t mmu_primary_context_read(void)	276	static inline uint64_t mmu_primary_context_read(void)
277	{	277	{
278	return asi_u64_read(ASI_DMMU, VA_PRIMARY_CONTEXT_REG);	278	return asi_u64_read(ASI_DMMU, VA_PRIMARY_CONTEXT_REG);
279	}	279	}
280		280
281	/** Write MMU Primary Context Register.	281	/** Write MMU Primary Context Register.
282	*	282	*
283	* @param v New value of Primary Context Register.	283	* @param v New value of Primary Context Register.
284	*/	284	*/
285	static inline void mmu_primary_context_write(uint64_t v)	285	static inline void mmu_primary_context_write(uint64_t v)
286	{	286	{
287	asi_u64_write(ASI_DMMU, VA_PRIMARY_CONTEXT_REG, v);	287	asi_u64_write(ASI_DMMU, VA_PRIMARY_CONTEXT_REG, v);
288	flush_pipeline();	288	flush_pipeline();
289	}	289	}
290		290
291	/** Read MMU Secondary Context Register.	291	/** Read MMU Secondary Context Register.
292	*	292	*
293	* @return Current value of Secondary Context Register.	293	* @return Current value of Secondary Context Register.
294	*/	294	*/
295	static inline uint64_t mmu_secondary_context_read(void)	295	static inline uint64_t mmu_secondary_context_read(void)
296	{	296	{
297	return asi_u64_read(ASI_DMMU, VA_SECONDARY_CONTEXT_REG);	297	return asi_u64_read(ASI_DMMU, VA_SECONDARY_CONTEXT_REG);
298	}	298	}
299		299
300	/** Write MMU Primary Context Register.	300	/** Write MMU Primary Context Register.
301	*	301	*
302	* @param v New value of Primary Context Register.	302	* @param v New value of Primary Context Register.
303	*/	303	*/
304	static inline void mmu_secondary_context_write(uint64_t v)	304	static inline void mmu_secondary_context_write(uint64_t v)
305	{	305	{
306	asi_u64_write(ASI_DMMU, VA_SECONDARY_CONTEXT_REG, v);	306	asi_u64_write(ASI_DMMU, VA_SECONDARY_CONTEXT_REG, v);
307	flush_pipeline();	307	flush_pipeline();
308	}	308	}
309		309
310	#if defined (US)	310	#if defined (US)
311		311
312	/** Read IMMU TLB Data Access Register.	312	/** Read IMMU TLB Data Access Register.
313	*	313	*
314	* @param entry TLB Entry index.	314	* @param entry TLB Entry index.
315	*	315	*
316	* @return Current value of specified IMMU TLB Data Access	316	* @return Current value of specified IMMU TLB Data Access
317	* Register.	317	* Register.
318	*/	318	*/
319	static inline uint64_t itlb_data_access_read(index_t entry)	319	static inline uint64_t itlb_data_access_read(index_t entry)
320	{	320	{
321	itlb_data_access_addr_t reg;	321	itlb_data_access_addr_t reg;
322		322
323	reg.value = 0;	323	reg.value = 0;
324	reg.tlb_entry = entry;	324	reg.tlb_entry = entry;
325	return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value);	325	return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value);
326	}	326	}
327		327
328	/** Write IMMU TLB Data Access Register.	328	/** Write IMMU TLB Data Access Register.
329	*	329	*
330	* @param entry TLB Entry index.	330	* @param entry TLB Entry index.
331	* @param value Value to be written.	331	* @param value Value to be written.
332	*/	332	*/
333	static inline void itlb_data_access_write(index_t entry, uint64_t value)	333	static inline void itlb_data_access_write(index_t entry, uint64_t value)
334	{	334	{
335	itlb_data_access_addr_t reg;	335	itlb_data_access_addr_t reg;
336		336
337	reg.value = 0;	337	reg.value = 0;
338	reg.tlb_entry = entry;	338	reg.tlb_entry = entry;
339	asi_u64_write(ASI_ITLB_DATA_ACCESS_REG, reg.value, value);	339	asi_u64_write(ASI_ITLB_DATA_ACCESS_REG, reg.value, value);
340	flush_pipeline();	340	flush_pipeline();
341	}	341	}
342		342
343	/** Read DMMU TLB Data Access Register.	343	/** Read DMMU TLB Data Access Register.
344	*	344	*
345	* @param entry TLB Entry index.	345	* @param entry TLB Entry index.
346	*	346	*
347	* @return Current value of specified DMMU TLB Data Access	347	* @return Current value of specified DMMU TLB Data Access
348	* Register.	348	* Register.
349	*/	349	*/
350	static inline uint64_t dtlb_data_access_read(index_t entry)	350	static inline uint64_t dtlb_data_access_read(index_t entry)
351	{	351	{
352	dtlb_data_access_addr_t reg;	352	dtlb_data_access_addr_t reg;
353		353
354	reg.value = 0;	354	reg.value = 0;
355	reg.tlb_entry = entry;	355	reg.tlb_entry = entry;
356	return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value);	356	return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value);
357	}	357	}
358		358
359	/** Write DMMU TLB Data Access Register.	359	/** Write DMMU TLB Data Access Register.
360	*	360	*
361	* @param entry TLB Entry index.	361	* @param entry TLB Entry index.
362	* @param value Value to be written.	362	* @param value Value to be written.
363	*/	363	*/
364	static inline void dtlb_data_access_write(index_t entry, uint64_t value)	364	static inline void dtlb_data_access_write(index_t entry, uint64_t value)
365	{	365	{
366	dtlb_data_access_addr_t reg;	366	dtlb_data_access_addr_t reg;
367		367
368	reg.value = 0;	368	reg.value = 0;
369	reg.tlb_entry = entry;	369	reg.tlb_entry = entry;
370	asi_u64_write(ASI_DTLB_DATA_ACCESS_REG, reg.value, value);	370	asi_u64_write(ASI_DTLB_DATA_ACCESS_REG, reg.value, value);
371	membar();	371	membar();
372	}	372	}
373		373
374	/** Read IMMU TLB Tag Read Register.	374	/** Read IMMU TLB Tag Read Register.
375	*	375	*
376	* @param entry TLB Entry index.	376	* @param entry TLB Entry index.
377	*	377	*
378	* @return Current value of specified IMMU TLB Tag Read Register.	378	* @return Current value of specified IMMU TLB Tag Read Register.
379	*/	379	*/
380	static inline uint64_t itlb_tag_read_read(index_t entry)	380	static inline uint64_t itlb_tag_read_read(index_t entry)
381	{	381	{
382	itlb_tag_read_addr_t tag;	382	itlb_tag_read_addr_t tag;
383		383
384	tag.value = 0;	384	tag.value = 0;
385	tag.tlb_entry = entry;	385	tag.tlb_entry = entry;
386	return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value);	386	return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value);
387	}	387	}
388		388
389	/** Read DMMU TLB Tag Read Register.	389	/** Read DMMU TLB Tag Read Register.
390	*	390	*
391	* @param entry TLB Entry index.	391	* @param entry TLB Entry index.
392	*	392	*
393	* @return Current value of specified DMMU TLB Tag Read Register.	393	* @return Current value of specified DMMU TLB Tag Read Register.
394	*/	394	*/
395	static inline uint64_t dtlb_tag_read_read(index_t entry)	395	static inline uint64_t dtlb_tag_read_read(index_t entry)
396	{	396	{
397	dtlb_tag_read_addr_t tag;	397	dtlb_tag_read_addr_t tag;
398		398
399	tag.value = 0;	399	tag.value = 0;
400	tag.tlb_entry = entry;	400	tag.tlb_entry = entry;
401	return asi_u64_read(ASI_DTLB_TAG_READ_REG, tag.value);	401	return asi_u64_read(ASI_DTLB_TAG_READ_REG, tag.value);
402	}	402	}
403		403
404	#elif defined (US3)	404	#elif defined (US3)
405		405
406		406
407	/** Read IMMU TLB Data Access Register.	407	/** Read IMMU TLB Data Access Register.
408	*	408	*
409	* @param tlb TLB number (one of TLB_ISMALL or TLB_IBIG)	409	* @param tlb TLB number (one of TLB_ISMALL or TLB_IBIG)
410	* @param entry TLB Entry index.	410	* @param entry TLB Entry index.
411	*	411	*
412	* @return Current value of specified IMMU TLB Data Access	412	* @return Current value of specified IMMU TLB Data Access
413	* Register.	413	* Register.
414	*/	414	*/
415	static inline uint64_t itlb_data_access_read(int tlb, index_t entry)	415	static inline uint64_t itlb_data_access_read(int tlb, index_t entry)
416	{	416	{
417	itlb_data_access_addr_t reg;	417	itlb_data_access_addr_t reg;
418		418
419	reg.value = 0;	419	reg.value = 0;
420	reg.tlb_number = tlb;	420	reg.tlb_number = tlb;
421	reg.local_tlb_entry = entry;	421	reg.local_tlb_entry = entry;
422	return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value);	422	return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value);
423	}	423	}
424		424
425	/** Write IMMU TLB Data Access Register.	425	/** Write IMMU TLB Data Access Register.
426	* @param tlb TLB number (one of TLB_ISMALL or TLB_IBIG)	426	* @param tlb TLB number (one of TLB_ISMALL or TLB_IBIG)
427	* @param entry TLB Entry index.	427	* @param entry TLB Entry index.
428	* @param value Value to be written.	428	* @param value Value to be written.
429	*/	429	*/
430	static inline void itlb_data_access_write(int tlb, index_t entry,	430	static inline void itlb_data_access_write(int tlb, index_t entry,
431	uint64_t value)	431	uint64_t value)
432	{	432	{
433	itlb_data_access_addr_t reg;	433	itlb_data_access_addr_t reg;
434		434
435	reg.value = 0;	435	reg.value = 0;
436	reg.tlb_number = tlb;	436	reg.tlb_number = tlb;
437	reg.local_tlb_entry = entry;	437	reg.local_tlb_entry = entry;
438	asi_u64_write(ASI_ITLB_DATA_ACCESS_REG, reg.value, value);	438	asi_u64_write(ASI_ITLB_DATA_ACCESS_REG, reg.value, value);
439	flush_pipeline();	439	flush_pipeline();
440	}	440	}
441		441
442	/** Read DMMU TLB Data Access Register.	442	/** Read DMMU TLB Data Access Register.
443	*	443	*
444	* @param tlb TLB number (one of TLB_DSMALL, TLB_DBIG, TLB_DBIG)	444	* @param tlb TLB number (one of TLB_DSMALL, TLB_DBIG, TLB_DBIG)
445	* @param entry TLB Entry index.	445	* @param entry TLB Entry index.
446	*	446	*
447	* @return Current value of specified DMMU TLB Data Access	447	* @return Current value of specified DMMU TLB Data Access
448	* Register.	448	* Register.
449	*/	449	*/
450	static inline uint64_t dtlb_data_access_read(int tlb, index_t entry)	450	static inline uint64_t dtlb_data_access_read(int tlb, index_t entry)
451	{	451	{
452	dtlb_data_access_addr_t reg;	452	dtlb_data_access_addr_t reg;
453		453
454	reg.value = 0;	454	reg.value = 0;
455	reg.tlb_number = tlb;	455	reg.tlb_number = tlb;
456	reg.local_tlb_entry = entry;	456	reg.local_tlb_entry = entry;
457	return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value);	457	return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value);
458	}	458	}
459		459
460	/** Write DMMU TLB Data Access Register.	460	/** Write DMMU TLB Data Access Register.
461	*	461	*
462	* @param tlb TLB number (one of TLB_DSMALL, TLB_DBIG_0, TLB_DBIG_1)	462	* @param tlb TLB number (one of TLB_DSMALL, TLB_DBIG_0, TLB_DBIG_1)
463	* @param entry TLB Entry index.	463	* @param entry TLB Entry index.
464	* @param value Value to be written.	464	* @param value Value to be written.
465	*/	465	*/
466	static inline void dtlb_data_access_write(int tlb, index_t entry,	466	static inline void dtlb_data_access_write(int tlb, index_t entry,
467	uint64_t value)	467	uint64_t value)
468	{	468	{
469	dtlb_data_access_addr_t reg;	469	dtlb_data_access_addr_t reg;
470		470
471	reg.value = 0;	471	reg.value = 0;
472	reg.tlb_number = tlb;	472	reg.tlb_number = tlb;
473	reg.local_tlb_entry = entry;	473	reg.local_tlb_entry = entry;
474	asi_u64_write(ASI_DTLB_DATA_ACCESS_REG, reg.value, value);	474	asi_u64_write(ASI_DTLB_DATA_ACCESS_REG, reg.value, value);
475	membar();	475	membar();
476	}	476	}
477		477
478	/** Read IMMU TLB Tag Read Register.	478	/** Read IMMU TLB Tag Read Register.
479	*	479	*
480	* @param tlb TLB number (one of TLB_ISMALL or TLB_IBIG)	480	* @param tlb TLB number (one of TLB_ISMALL or TLB_IBIG)
481	* @param entry TLB Entry index.	481	* @param entry TLB Entry index.
482	*	482	*
483	* @return Current value of specified IMMU TLB Tag Read Register.	483	* @return Current value of specified IMMU TLB Tag Read Register.
484	*/	484	*/
485	static inline uint64_t itlb_tag_read_read(int tlb, index_t entry)	485	static inline uint64_t itlb_tag_read_read(int tlb, index_t entry)
486	{	486	{
487	itlb_tag_read_addr_t tag;	487	itlb_tag_read_addr_t tag;
488		488
489	tag.value = 0;	489	tag.value = 0;
490	tag.tlb_number = tlb;	490	tag.tlb_number = tlb;
491	tag.local_tlb_entry = entry;	491	tag.local_tlb_entry = entry;
492	return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value);	492	return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value);
493	}	493	}
494		494
495	/** Read DMMU TLB Tag Read Register.	495	/** Read DMMU TLB Tag Read Register.
496	*	496	*
497	* @param tlb TLB number (one of TLB_DSMALL, TLB_DBIG_0, TLB_DBIG_1)	497	* @param tlb TLB number (one of TLB_DSMALL, TLB_DBIG_0, TLB_DBIG_1)
498	* @param entry TLB Entry index.	498	* @param entry TLB Entry index.
499	*	499	*
500	* @return Current value of specified DMMU TLB Tag Read Register.	500	* @return Current value of specified DMMU TLB Tag Read Register.

Subversion Repositories HelenOS

(root)/branches/sparc/kernel/arch/sparc64/include/mm/sun4u/tlb.h – Rev 3770 → 3862