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36 | #define KERN_sparc64_CACHE_SPEC_H_ |
36 | #define KERN_sparc64_CACHE_SPEC_H_ |
37 | 37 | ||
38 | /* |
38 | /* |
39 | * The following macros are valid for the following processors: |
39 | * The following macros are valid for the following processors: |
40 | * |
40 | * |
41 | * UltraSPARC, UltraSPARC II, UltraSPARC IIi |
41 | * UltraSPARC, UltraSPARC II, UltraSPARC IIi, UltraSPARC III Cu |
42 | * |
42 | * |
43 | * Should we support other UltraSPARC processors, we need to make sure that |
43 | * Should we support other UltraSPARC processors, we need to make sure that |
44 | * the macros are defined correctly for them. |
44 | * the macros are defined correctly for them. |
45 | */ |
45 | */ |
46 | 46 | ||
- | 47 | #if defined (US) |
|
47 | #define DCACHE_SIZE (16 * 1024) |
48 | #define DCACHE_SIZE (16 * 1024) |
- | 49 | #elif defined (US3) |
|
- | 50 | #define DCACHE_SIZE (64 * 1024) |
|
- | 51 | #endif |
|
48 | #define DCACHE_LINE_SIZE 32 |
52 | #define DCACHE_LINE_SIZE 32 |
49 | 53 | ||
- | 54 | #if defined (US) |
|
50 | #define ICACHE_SIZE (16 * 1024) |
55 | #define ICACHE_SIZE (16 * 1024) |
51 | #define ICACHE_WAYS 2 |
56 | #define ICACHE_WAYS 2 |
- | 57 | #elif defined (US3) |
|
- | 58 | #define ICACHE_SIZE (32 * 1024) |
|
- | 59 | #define ICACHE_WAYS 4 |
|
- | 60 | #endif |
|
52 | #define ICACHE_LINE_SIZE 32 |
61 | #define ICACHE_LINE_SIZE 32 |
53 | 62 | ||
54 | #endif |
63 | #endif |
55 | 64 | ||
56 | /** @} |
65 | /** @} |
57 | */ |
66 | */ |
58 | 67 |