WebSVN – HelenOS – Diff – /branches/sparc/kernel/arch/sparc64/include/cpu.h


/*
 * Copyright (c) 2005 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup sparc64
 * @{
 */
/** @file
 */
 
#ifndef KERN_sparc64_CPU_H_
#define KERN_sparc64_CPU_H_
 
#define MANUF_FUJITSU       0x04
#define MANUF_ULTRASPARC    0x17    /**< UltraSPARC I, UltraSPARC II */
#define MANUF_SUN       0x3e
 
#define IMPL_ULTRASPARCI    0x10
#define IMPL_ULTRASPARCII   0x11
#define IMPL_ULTRASPARCII_I 0x12
#define IMPL_ULTRASPARCII_E 0x13
#define IMPL_ULTRASPARCIII  0x14
#define IMPL_ULTRASPARCIII_PLUS 0x15
#define IMPL_ULTRASPARCIII_I    0x16
#define IMPL_ULTRASPARCIV   0x18
#define IMPL_ULTRASPARCIV_PLUS  0x19
 
#define IMPL_SPARC64V       0x5
 
#ifndef __ASM__
 
#include <arch/types.h>
#include <typedefs.h>
#include <arch/register.h>
#include <arch/sun4u/regdef.h>
#include <arch/asm.h>
#include <arch/sun4u/arch.h>
 
#ifdef CONFIG_SMP
#include <arch/mm/cache.h>
#endif
 
typedef struct {
    uint32_t mid;           /**< Processor ID as read from
                         UPA_CONFIG/FIREPLANE_CONFIG. */
    ver_reg_t ver;
    uint32_t clock_frequency;   /**< Processor frequency in Hz. */
    uint64_t next_tick_cmpr;    /**< Next clock interrupt should be
                         generated when the TICK register
                         matches this value. */
} cpu_arch_t;
 
 
/**
 * Reads the module ID (agent ID/CPUID) of the current CPU.
 */
static inline uint32_t read_mid(void)
{
    uint64_t icbus_config = asi_u64_read(ASI_ICBUS_CONFIG, 0);
    icbus_config = icbus_config >> ICBUS_CONFIG_MID_SHIFT;
#if defined (US)
    return icbus_config & 0x1f;
#elif defined (US3)
    if (((ver_reg_t) ver_read()).impl == IMPL_ULTRASPARCIII_I)
        return icbus_config & 0x1f;
    else
        return icbus_config & 0x3ff;
#else
    panic("Not implemented for this architecture.");
    return 0;
#endif
}
 
#endif  
 
#endif
 
/** @}
 */
 

Rev 3664	Rev 3743
1	/*	1	/*
2	* Copyright (c) 2005 Jakub Jermar	2	* Copyright (c) 2005 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	/** @addtogroup sparc64	29	/** @addtogroup sparc64
30	* @{	30	* @{
31	*/	31	*/
32	/** @file	32	/** @file
33	*/	33	*/
34		34
35	#ifndef KERN_sparc64_CPU_H_	35	#ifndef KERN_sparc64_CPU_H_
36	#define KERN_sparc64_CPU_H_	36	#define KERN_sparc64_CPU_H_
37		37
38	#define MANUF_FUJITSU 0x04	38	#define MANUF_FUJITSU 0x04
39	#define MANUF_ULTRASPARC 0x17 /*< UltraSPARC I, UltraSPARC II /	39	#define MANUF_ULTRASPARC 0x17 /*< UltraSPARC I, UltraSPARC II /
40	#define MANUF_SUN 0x3e	40	#define MANUF_SUN 0x3e
41		41
42	#define IMPL_ULTRASPARCI 0x10	42	#define IMPL_ULTRASPARCI 0x10
43	#define IMPL_ULTRASPARCII 0x11	43	#define IMPL_ULTRASPARCII 0x11
44	#define IMPL_ULTRASPARCII_I 0x12	44	#define IMPL_ULTRASPARCII_I 0x12
45	#define IMPL_ULTRASPARCII_E 0x13	45	#define IMPL_ULTRASPARCII_E 0x13
46	#define IMPL_ULTRASPARCIII 0x14	46	#define IMPL_ULTRASPARCIII 0x14
47	#define IMPL_ULTRASPARCIII_PLUS 0x15	47	#define IMPL_ULTRASPARCIII_PLUS 0x15
48	#define IMPL_ULTRASPARCIII_I 0x16	48	#define IMPL_ULTRASPARCIII_I 0x16
49	#define IMPL_ULTRASPARCIV 0x18	49	#define IMPL_ULTRASPARCIV 0x18
50	#define IMPL_ULTRASPARCIV_PLUS 0x19	50	#define IMPL_ULTRASPARCIV_PLUS 0x19
51		51
52	#define IMPL_SPARC64V 0x5	52	#define IMPL_SPARC64V 0x5
53		53
54	#ifndef __ASM__	54	#ifndef __ASM__
55		55
56	#include <arch/types.h>	56	#include <arch/types.h>
57	#include <typedefs.h>	57	#include <typedefs.h>
58	#include <arch/register.h>	58	#include <arch/register.h>
59	#include <arch/regdef.h>	59	#include <arch/sun4u/regdef.h>
60	#include <arch/asm.h>	60	#include <arch/asm.h>
-		61	#include <arch/sun4u/arch.h>
61		62
62	#ifdef CONFIG_SMP	63	#ifdef CONFIG_SMP
63	#include <arch/mm/cache.h>	64	#include <arch/mm/cache.h>
64	#endif	65	#endif
65		66
66	typedef struct {	67	typedef struct {
67	uint32_t mid; /**< Processor ID as read from	68	uint32_t mid; /**< Processor ID as read from
68	UPA_CONFIG/FIREPLANE_CONFIG. */	69	UPA_CONFIG/FIREPLANE_CONFIG. */
69	ver_reg_t ver;	70	ver_reg_t ver;
70	uint32_t clock_frequency; /*< Processor frequency in Hz. /	71	uint32_t clock_frequency; /*< Processor frequency in Hz. /
71	uint64_t next_tick_cmpr; /**< Next clock interrupt should be	72	uint64_t next_tick_cmpr; /**< Next clock interrupt should be
72	generated when the TICK register	73	generated when the TICK register
73	matches this value. */	74	matches this value. */
74	} cpu_arch_t;	75	} cpu_arch_t;
75		76
76		77
77	/**	78	/**
78	* Reads the module ID (agent ID/CPUID) of the current CPU.	79	* Reads the module ID (agent ID/CPUID) of the current CPU.
79	*/	80	*/
80	static inline uint32_t read_mid(void)	81	static inline uint32_t read_mid(void)
81	{	82	{
82	uint64_t icbus_config = asi_u64_read(ASI_ICBUS_CONFIG, 0);	83	uint64_t icbus_config = asi_u64_read(ASI_ICBUS_CONFIG, 0);
83	icbus_config = icbus_config >> ICBUS_CONFIG_MID_SHIFT;	84	icbus_config = icbus_config >> ICBUS_CONFIG_MID_SHIFT;
84	#if defined (US)	85	#if defined (US)
85	return icbus_config & 0x1f;	86	return icbus_config & 0x1f;
86	#elif defined (US3)	87	#elif defined (US3)
87	if (((ver_reg_t) ver_read()).impl == IMPL_ULTRASPARCIII_I)	88	if (((ver_reg_t) ver_read()).impl == IMPL_ULTRASPARCIII_I)
88	return icbus_config & 0x1f;	89	return icbus_config & 0x1f;
89	else	90	else
90	return icbus_config & 0x3ff;	91	return icbus_config & 0x3ff;
-		92	#else
-		93	panic("Not implemented for this architecture.");
-		94	return 0;
91	#endif	95	#endif
92	}	96	}
93		97
94	#endif	98	#endif
95		99
96	#endif	100	#endif
97		101
98	/** @}	102	/** @}
99	*/	103	*/
100		104

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(root)/branches/sparc/kernel/arch/sparc64/include/cpu.h – Rev 3664 → 3743