WebSVN – HelenOS – Diff – /branches/sparc/kernel/arch/sparc64/include/asm.h


/*
 * Copyright (c) 2005 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup sparc64
 * @{
 */
/** @file
 */
 
#ifndef KERN_sparc64_ASM_H_
#define KERN_sparc64_ASM_H_
 
#include <arch/arch.h>
#include <arch/types.h>
#include <typedefs.h>
#include <align.h>
#include <arch/register.h>
#include <config.h>
#include <arch/stack.h>
#include <arch/barrier.h>
 
static inline void outb(ioport_t port, uint8_t v)
{
    *((volatile uint8_t *)(port)) = v;
    memory_barrier();
}
 
static inline void outw(ioport_t port, uint16_t v)
{
    *((volatile uint16_t *)(port)) = v;
    memory_barrier();
}
 
static inline void outl(ioport_t port, uint32_t v)
{
    *((volatile uint32_t *)(port)) = v;
    memory_barrier();
}
 
static inline uint8_t inb(ioport_t port)
{
    uint8_t rv;
 
    rv = *((volatile uint8_t *)(port));
    memory_barrier();
 
    return rv;
}
 
static inline uint16_t inw(ioport_t port)
{
    uint16_t rv;
 
    rv = *((volatile uint16_t *)(port));
    memory_barrier();
 
    return rv;
}
 
static inline uint32_t inl(ioport_t port)
{
    uint32_t rv;
 
    rv = *((volatile uint32_t *)(port));
    memory_barrier();
 
    return rv;
}
 
/** Read Processor State register.
 *
 * @return Value of PSTATE register.
 */
static inline uint64_t pstate_read(void)
{
    uint64_t v;
   
    asm volatile ("rdpr %%pstate, %0\n" : "=r" (v));
   
    return v;
}
 
/** Write Processor State register.
 *
 * @param v New value of PSTATE register.
 */
static inline void pstate_write(uint64_t v)
{
    asm volatile ("wrpr %0, %1, %%pstate\n" : : "r" (v), "i" (0));
}
 
/** Read TICK_compare Register.
 *
 * @return Value of TICK_comapre register.
 */
static inline uint64_t tick_compare_read(void)
{
    uint64_t v;
   
    asm volatile ("rd %%tick_cmpr, %0\n" : "=r" (v));
   
    return v;
}
 
/** Write TICK_compare Register.
 *
 * @param v New value of TICK_comapre register.
 */
static inline void tick_compare_write(uint64_t v)
{
    asm volatile ("wr %0, %1, %%tick_cmpr\n" : : "r" (v), "i" (0));
}
 
/** Read TICK Register.
 *
 * @return Value of TICK register.
 */
static inline uint64_t tick_read(void)
{
    uint64_t v;
   
    asm volatile ("rdpr %%tick, %0\n" : "=r" (v));
   
    return v;
}
 
/** Write TICK Register.
 *
 * @param v New value of TICK register.
 */
static inline void tick_write(uint64_t v)
{
    asm volatile ("wrpr %0, %1, %%tick\n" : : "r" (v), "i" (0));
}
 
/** Read FPRS Register.
 *
 * @return Value of FPRS register.
 */
static inline uint64_t fprs_read(void)
{
    uint64_t v;
   
    asm volatile ("rd %%fprs, %0\n" : "=r" (v));
   
    return v;
}
 
/** Write FPRS Register.
 *
 * @param v New value of FPRS register.
 */
static inline void fprs_write(uint64_t v)
{
    asm volatile ("wr %0, %1, %%fprs\n" : : "r" (v), "i" (0));
}
 
/** Read SOFTINT Register.
 *
 * @return Value of SOFTINT register.
 */
static inline uint64_t softint_read(void)
{
    uint64_t v;
 
    asm volatile ("rd %%softint, %0\n" : "=r" (v));
 
    return v;
}
 
/** Write SOFTINT Register.
 *
 * @param v New value of SOFTINT register.
 */
static inline void softint_write(uint64_t v)
{
    asm volatile ("wr %0, %1, %%softint\n" : : "r" (v), "i" (0));
}
 
/** Write CLEAR_SOFTINT Register.
 *
 * Bits set in CLEAR_SOFTINT register will be cleared in SOFTINT register.
 *
 * @param v New value of CLEAR_SOFTINT register.
 */
static inline void clear_softint_write(uint64_t v)
{
    asm volatile ("wr %0, %1, %%clear_softint\n" : : "r" (v), "i" (0));
}
 
/** Write SET_SOFTINT Register.
 *
 * Bits set in SET_SOFTINT register will be set in SOFTINT register.
 *
 * @param v New value of SET_SOFTINT register.
 */
static inline void set_softint_write(uint64_t v)
{
    asm volatile ("wr %0, %1, %%set_softint\n" : : "r" (v), "i" (0));
}
 
/** Enable interrupts.
 *
 * Enable interrupts and return previous
 * value of IPL.
 *
 * @return Old interrupt priority level.
 */
static inline ipl_t interrupts_enable(void) {
    pstate_reg_t pstate;
    uint64_t value;
   
    value = pstate_read();
    pstate.value = value;
    pstate.ie = true;
    pstate_write(pstate.value);
   
    return (ipl_t) value;
}
 
/** Disable interrupts.
 *
 * Disable interrupts and return previous
 * value of IPL.
 *
 * @return Old interrupt priority level.
 */
static inline ipl_t interrupts_disable(void) {
    pstate_reg_t pstate;
    uint64_t value;
   
    value = pstate_read();
    pstate.value = value;
    pstate.ie = false;
    pstate_write(pstate.value);
   
    return (ipl_t) value;
}
 
/** Restore interrupt priority level.
 *
 * Restore IPL.
 *
 * @param ipl Saved interrupt priority level.
 */
static inline void interrupts_restore(ipl_t ipl) {
    pstate_reg_t pstate;
   
    pstate.value = pstate_read();
    pstate.ie = ((pstate_reg_t) ipl).ie;
    pstate_write(pstate.value);
}
 
/** Return interrupt priority level.
 *
 * Return IPL.
 *
 * @return Current interrupt priority level.
 */
static inline ipl_t interrupts_read(void) {
    return (ipl_t) pstate_read();
}
 
/** Return base address of current stack.
 *
 * Return the base address of the current stack.
 * The stack is assumed to be STACK_SIZE bytes long.
 * The stack must start on page boundary.
 */
static inline uintptr_t get_stack_base(void)
{
    uintptr_t unbiased_sp;
   
    asm volatile ("add %%sp, %1, %0\n" : "=r" (unbiased_sp) : "i" (STACK_BIAS));
   
    return ALIGN_DOWN(unbiased_sp, STACK_SIZE);
}
 
/** Read Version Register.
 *
 * @return Value of VER register.
 */
static inline uint64_t ver_read(void)
{
    uint64_t v;
   
    asm volatile ("rdpr %%ver, %0\n" : "=r" (v));
   
    return v;
}
 
/** Read Trap Program Counter register.
 *
 * @return Current value in TPC.
 */
static inline uint64_t tpc_read(void)
{
    uint64_t v;
   
    asm volatile ("rdpr %%tpc, %0\n" : "=r" (v));
   
    return v;
}
 
/** Read Trap Level register.
 *
 * @return Current value in TL.
 */
static inline uint64_t tl_read(void)
{
    uint64_t v;
   
    asm volatile ("rdpr %%tl, %0\n" : "=r" (v));
   
    return v;
}
 
/** Read Trap Base Address register.
 *
 * @return Current value in TBA.
 */
static inline uint64_t tba_read(void)
{
    uint64_t v;
   
    asm volatile ("rdpr %%tba, %0\n" : "=r" (v));
   
    return v;
}
 
/** Write Trap Base Address register.
 *
 * @param v New value of TBA.
 */
static inline void tba_write(uint64_t v)
{
    asm volatile ("wrpr %0, %1, %%tba\n" : : "r" (v), "i" (0));
}
 
/** Load uint64_t from alternate space.
 *
 * @param asi ASI determining the alternate space.
 * @param va Virtual address within the ASI.
 *
 * @return Value read from the virtual address in the specified address space.
 */
static inline uint64_t asi_u64_read(asi_t asi, uintptr_t va)
{
    uint64_t v;
   
    asm volatile ("ldxa [%1] %2, %0\n" : "=r" (v) : "r" (va), "i" ((unsigned) asi));
   
    return v;
}
 
/** Store uint64_t to alternate space.
 *
 * @param asi ASI determining the alternate space.
 * @param va Virtual address within the ASI.
 * @param v Value to be written.
 */
static inline void asi_u64_write(asi_t asi, uintptr_t va, uint64_t v)
{
    asm volatile ("stxa %0, [%1] %2\n" : :  "r" (v), "r" (va), "i" ((unsigned) asi) : "memory");
}
 
/** Flush all valid register windows to memory. */
static inline void flushw(void)
{
    asm volatile ("flushw\n");
}
 
/** Switch to nucleus by setting TL to 1. */
static inline void nucleus_enter(void)
{
    asm volatile ("wrpr %g0, 1, %tl\n");
}
 
/** Switch from nucleus by setting TL to 0. */
static inline void nucleus_leave(void)
{
    asm volatile ("wrpr %g0, %g0, %tl\n");
}
 
/** Read UPA_CONFIG/FIREPLANE_CONFIG register.
 *
 * @return
 *  Value of the UPA_CONFIG register in US,
 *  value of the FIREPLANE_CONFIG on US3.
 */
static inline uint64_t icbus_config_read(void)
{
    return asi_u64_read(ASI_ICBUS_CONFIG, 0);
}
 
extern void cpu_halt(void);
extern void cpu_sleep(void);
extern void asm_delay_loop(const uint32_t usec);
 
extern uint64_t read_from_ag_g7(void);
extern void write_to_ag_g6(uint64_t val);
extern void write_to_ag_g7(uint64_t val);
extern void write_to_ig_g6(uint64_t val);
 
extern void switch_to_userspace(uint64_t pc, uint64_t sp, uint64_t uarg);
 
#endif
 
/** @}
 */
 

Rev 3479	Rev 3593
1	/*	1	/*
2	* Copyright (c) 2005 Jakub Jermar	2	* Copyright (c) 2005 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	/** @addtogroup sparc64	29	/** @addtogroup sparc64
30	* @{	30	* @{
31	*/	31	*/
32	/** @file	32	/** @file
33	*/	33	*/
34		34
35	#ifndef KERN_sparc64_ASM_H_	35	#ifndef KERN_sparc64_ASM_H_
36	#define KERN_sparc64_ASM_H_	36	#define KERN_sparc64_ASM_H_
37		37
38	#include <arch/arch.h>	38	#include <arch/arch.h>
39	#include <arch/types.h>	39	#include <arch/types.h>
40	#include <typedefs.h>	40	#include <typedefs.h>
41	#include <align.h>	41	#include <align.h>
42	#include <arch/register.h>	42	#include <arch/register.h>
43	#include <config.h>	43	#include <config.h>
44	#include <arch/stack.h>	44	#include <arch/stack.h>
-		45	#include <arch/barrier.h>
-		46
-		47	static inline void outb(ioport_t port, uint8_t v)
-		48	{
-		49	((volatile uint8_t )(port)) = v;
-		50	memory_barrier();
-		51	}
-		52
-		53	static inline void outw(ioport_t port, uint16_t v)
-		54	{
-		55	((volatile uint16_t )(port)) = v;
-		56	memory_barrier();
-		57	}
-		58
-		59	static inline void outl(ioport_t port, uint32_t v)
-		60	{
-		61	((volatile uint32_t )(port)) = v;
-		62	memory_barrier();
-		63	}
-		64
-		65	static inline uint8_t inb(ioport_t port)
-		66	{
-		67	uint8_t rv;
-		68
-		69	rv = ((volatile uint8_t )(port));
-		70	memory_barrier();
-		71
-		72	return rv;
-		73	}
-		74
-		75	static inline uint16_t inw(ioport_t port)
-		76	{
-		77	uint16_t rv;
-		78
-		79	rv = ((volatile uint16_t )(port));
-		80	memory_barrier();
-		81
-		82	return rv;
-		83	}
-		84
-		85	static inline uint32_t inl(ioport_t port)
-		86	{
-		87	uint32_t rv;
-		88
-		89	rv = ((volatile uint32_t )(port));
-		90	memory_barrier();
-		91
-		92	return rv;
-		93	}
45		94
46	/** Read Processor State register.	95	/** Read Processor State register.
47	*	96	*
48	* @return Value of PSTATE register.	97	* @return Value of PSTATE register.
49	*/	98	*/
50	static inline uint64_t pstate_read(void)	99	static inline uint64_t pstate_read(void)
51	{	100	{
52	uint64_t v;	101	uint64_t v;
53		102
54	asm volatile ("rdpr %%pstate, %0\n" : "=r" (v));	103	asm volatile ("rdpr %%pstate, %0\n" : "=r" (v));
55		104
56	return v;	105	return v;
57	}	106	}
58		107
59	/** Write Processor State register.	108	/** Write Processor State register.
60	*	109	*
61	* @param v New value of PSTATE register.	110	* @param v New value of PSTATE register.
62	*/	111	*/
63	static inline void pstate_write(uint64_t v)	112	static inline void pstate_write(uint64_t v)
64	{	113	{
65	asm volatile ("wrpr %0, %1, %%pstate\n" : : "r" (v), "i" (0));	114	asm volatile ("wrpr %0, %1, %%pstate\n" : : "r" (v), "i" (0));
66	}	115	}
67		116
68	/** Read TICK_compare Register.	117	/** Read TICK_compare Register.
69	*	118	*
70	* @return Value of TICK_comapre register.	119	* @return Value of TICK_comapre register.
71	*/	120	*/
72	static inline uint64_t tick_compare_read(void)	121	static inline uint64_t tick_compare_read(void)
73	{	122	{
74	uint64_t v;	123	uint64_t v;
75		124
76	asm volatile ("rd %%tick_cmpr, %0\n" : "=r" (v));	125	asm volatile ("rd %%tick_cmpr, %0\n" : "=r" (v));
77		126
78	return v;	127	return v;
79	}	128	}
80		129
81	/** Write TICK_compare Register.	130	/** Write TICK_compare Register.
82	*	131	*
83	* @param v New value of TICK_comapre register.	132	* @param v New value of TICK_comapre register.
84	*/	133	*/
85	static inline void tick_compare_write(uint64_t v)	134	static inline void tick_compare_write(uint64_t v)
86	{	135	{
87	asm volatile ("wr %0, %1, %%tick_cmpr\n" : : "r" (v), "i" (0));	136	asm volatile ("wr %0, %1, %%tick_cmpr\n" : : "r" (v), "i" (0));
88	}	137	}
89		138
90	/** Read TICK Register.	139	/** Read TICK Register.
91	*	140	*
92	* @return Value of TICK register.	141	* @return Value of TICK register.
93	*/	142	*/
94	static inline uint64_t tick_read(void)	143	static inline uint64_t tick_read(void)
95	{	144	{
96	uint64_t v;	145	uint64_t v;
97		146
98	asm volatile ("rdpr %%tick, %0\n" : "=r" (v));	147	asm volatile ("rdpr %%tick, %0\n" : "=r" (v));
99		148
100	return v;	149	return v;
101	}	150	}
102		151
103	/** Write TICK Register.	152	/** Write TICK Register.
104	*	153	*
105	* @param v New value of TICK register.	154	* @param v New value of TICK register.
106	*/	155	*/
107	static inline void tick_write(uint64_t v)	156	static inline void tick_write(uint64_t v)
108	{	157	{
109	asm volatile ("wrpr %0, %1, %%tick\n" : : "r" (v), "i" (0));	158	asm volatile ("wrpr %0, %1, %%tick\n" : : "r" (v), "i" (0));
110	}	159	}
111		160
112	/** Read FPRS Register.	161	/** Read FPRS Register.
113	*	162	*
114	* @return Value of FPRS register.	163	* @return Value of FPRS register.
115	*/	164	*/
116	static inline uint64_t fprs_read(void)	165	static inline uint64_t fprs_read(void)
117	{	166	{
118	uint64_t v;	167	uint64_t v;
119		168
120	asm volatile ("rd %%fprs, %0\n" : "=r" (v));	169	asm volatile ("rd %%fprs, %0\n" : "=r" (v));
121		170
122	return v;	171	return v;
123	}	172	}
124		173
125	/** Write FPRS Register.	174	/** Write FPRS Register.
126	*	175	*
127	* @param v New value of FPRS register.	176	* @param v New value of FPRS register.
128	*/	177	*/
129	static inline void fprs_write(uint64_t v)	178	static inline void fprs_write(uint64_t v)
130	{	179	{
131	asm volatile ("wr %0, %1, %%fprs\n" : : "r" (v), "i" (0));	180	asm volatile ("wr %0, %1, %%fprs\n" : : "r" (v), "i" (0));
132	}	181	}
133		182
134	/** Read SOFTINT Register.	183	/** Read SOFTINT Register.
135	*	184	*
136	* @return Value of SOFTINT register.	185	* @return Value of SOFTINT register.
137	*/	186	*/
138	static inline uint64_t softint_read(void)	187	static inline uint64_t softint_read(void)
139	{	188	{
140	uint64_t v;	189	uint64_t v;
141		190
142	asm volatile ("rd %%softint, %0\n" : "=r" (v));	191	asm volatile ("rd %%softint, %0\n" : "=r" (v));
143		192
144	return v;	193	return v;
145	}	194	}
146		195
147	/** Write SOFTINT Register.	196	/** Write SOFTINT Register.
148	*	197	*
149	* @param v New value of SOFTINT register.	198	* @param v New value of SOFTINT register.
150	*/	199	*/
151	static inline void softint_write(uint64_t v)	200	static inline void softint_write(uint64_t v)
152	{	201	{
153	asm volatile ("wr %0, %1, %%softint\n" : : "r" (v), "i" (0));	202	asm volatile ("wr %0, %1, %%softint\n" : : "r" (v), "i" (0));
154	}	203	}
155		204
156	/** Write CLEAR_SOFTINT Register.	205	/** Write CLEAR_SOFTINT Register.
157	*	206	*
158	* Bits set in CLEAR_SOFTINT register will be cleared in SOFTINT register.	207	* Bits set in CLEAR_SOFTINT register will be cleared in SOFTINT register.
159	*	208	*
160	* @param v New value of CLEAR_SOFTINT register.	209	* @param v New value of CLEAR_SOFTINT register.
161	*/	210	*/
162	static inline void clear_softint_write(uint64_t v)	211	static inline void clear_softint_write(uint64_t v)
163	{	212	{
164	asm volatile ("wr %0, %1, %%clear_softint\n" : : "r" (v), "i" (0));	213	asm volatile ("wr %0, %1, %%clear_softint\n" : : "r" (v), "i" (0));
165	}	214	}
166		215
167	/** Write SET_SOFTINT Register.	216	/** Write SET_SOFTINT Register.
168	*	217	*
169	* Bits set in SET_SOFTINT register will be set in SOFTINT register.	218	* Bits set in SET_SOFTINT register will be set in SOFTINT register.
170	*	219	*
171	* @param v New value of SET_SOFTINT register.	220	* @param v New value of SET_SOFTINT register.
172	*/	221	*/
173	static inline void set_softint_write(uint64_t v)	222	static inline void set_softint_write(uint64_t v)
174	{	223	{
175	asm volatile ("wr %0, %1, %%set_softint\n" : : "r" (v), "i" (0));	224	asm volatile ("wr %0, %1, %%set_softint\n" : : "r" (v), "i" (0));
176	}	225	}
177		226
178	/** Enable interrupts.	227	/** Enable interrupts.
179	*	228	*
180	* Enable interrupts and return previous	229	* Enable interrupts and return previous
181	* value of IPL.	230	* value of IPL.
182	*	231	*
183	* @return Old interrupt priority level.	232	* @return Old interrupt priority level.
184	*/	233	*/
185	static inline ipl_t interrupts_enable(void) {	234	static inline ipl_t interrupts_enable(void) {
186	pstate_reg_t pstate;	235	pstate_reg_t pstate;
187	uint64_t value;	236	uint64_t value;
188		237
189	value = pstate_read();	238	value = pstate_read();
190	pstate.value = value;	239	pstate.value = value;
191	pstate.ie = true;	240	pstate.ie = true;
192	pstate_write(pstate.value);	241	pstate_write(pstate.value);
193		242
194	return (ipl_t) value;	243	return (ipl_t) value;
195	}	244	}
196		245
197	/** Disable interrupts.	246	/** Disable interrupts.
198	*	247	*
199	* Disable interrupts and return previous	248	* Disable interrupts and return previous
200	* value of IPL.	249	* value of IPL.
201	*	250	*
202	* @return Old interrupt priority level.	251	* @return Old interrupt priority level.
203	*/	252	*/
204	static inline ipl_t interrupts_disable(void) {	253	static inline ipl_t interrupts_disable(void) {
205	pstate_reg_t pstate;	254	pstate_reg_t pstate;
206	uint64_t value;	255	uint64_t value;
207		256
208	value = pstate_read();	257	value = pstate_read();
209	pstate.value = value;	258	pstate.value = value;
210	pstate.ie = false;	259	pstate.ie = false;
211	pstate_write(pstate.value);	260	pstate_write(pstate.value);
212		261
213	return (ipl_t) value;	262	return (ipl_t) value;
214	}	263	}
215		264
216	/** Restore interrupt priority level.	265	/** Restore interrupt priority level.
217	*	266	*
218	* Restore IPL.	267	* Restore IPL.
219	*	268	*
220	* @param ipl Saved interrupt priority level.	269	* @param ipl Saved interrupt priority level.
221	*/	270	*/
222	static inline void interrupts_restore(ipl_t ipl) {	271	static inline void interrupts_restore(ipl_t ipl) {
223	pstate_reg_t pstate;	272	pstate_reg_t pstate;
224		273
225	pstate.value = pstate_read();	274	pstate.value = pstate_read();
226	pstate.ie = ((pstate_reg_t) ipl).ie;	275	pstate.ie = ((pstate_reg_t) ipl).ie;
227	pstate_write(pstate.value);	276	pstate_write(pstate.value);
228	}	277	}
229		278
230	/** Return interrupt priority level.	279	/** Return interrupt priority level.
231	*	280	*
232	* Return IPL.	281	* Return IPL.
233	*	282	*
234	* @return Current interrupt priority level.	283	* @return Current interrupt priority level.
235	*/	284	*/
236	static inline ipl_t interrupts_read(void) {	285	static inline ipl_t interrupts_read(void) {
237	return (ipl_t) pstate_read();	286	return (ipl_t) pstate_read();
238	}	287	}
239		288
240	/** Return base address of current stack.	289	/** Return base address of current stack.
241	*	290	*
242	* Return the base address of the current stack.	291	* Return the base address of the current stack.
243	* The stack is assumed to be STACK_SIZE bytes long.	292	* The stack is assumed to be STACK_SIZE bytes long.
244	* The stack must start on page boundary.	293	* The stack must start on page boundary.
245	*/	294	*/
246	static inline uintptr_t get_stack_base(void)	295	static inline uintptr_t get_stack_base(void)
247	{	296	{
248	uintptr_t unbiased_sp;	297	uintptr_t unbiased_sp;
249		298
250	asm volatile ("add %%sp, %1, %0\n" : "=r" (unbiased_sp) : "i" (STACK_BIAS));	299	asm volatile ("add %%sp, %1, %0\n" : "=r" (unbiased_sp) : "i" (STACK_BIAS));
251		300
252	return ALIGN_DOWN(unbiased_sp, STACK_SIZE);	301	return ALIGN_DOWN(unbiased_sp, STACK_SIZE);
253	}	302	}
254		303
255	/** Read Version Register.	304	/** Read Version Register.
256	*	305	*
257	* @return Value of VER register.	306	* @return Value of VER register.
258	*/	307	*/
259	static inline uint64_t ver_read(void)	308	static inline uint64_t ver_read(void)
260	{	309	{
261	uint64_t v;	310	uint64_t v;
262		311
263	asm volatile ("rdpr %%ver, %0\n" : "=r" (v));	312	asm volatile ("rdpr %%ver, %0\n" : "=r" (v));
264		313
265	return v;	314	return v;
266	}	315	}
267		316
268	/** Read Trap Program Counter register.	317	/** Read Trap Program Counter register.
269	*	318	*
270	* @return Current value in TPC.	319	* @return Current value in TPC.
271	*/	320	*/
272	static inline uint64_t tpc_read(void)	321	static inline uint64_t tpc_read(void)
273	{	322	{
274	uint64_t v;	323	uint64_t v;
275		324
276	asm volatile ("rdpr %%tpc, %0\n" : "=r" (v));	325	asm volatile ("rdpr %%tpc, %0\n" : "=r" (v));
277		326
278	return v;	327	return v;
279	}	328	}
280		329
281	/** Read Trap Level register.	330	/** Read Trap Level register.
282	*	331	*
283	* @return Current value in TL.	332	* @return Current value in TL.
284	*/	333	*/
285	static inline uint64_t tl_read(void)	334	static inline uint64_t tl_read(void)
286	{	335	{
287	uint64_t v;	336	uint64_t v;
288		337
289	asm volatile ("rdpr %%tl, %0\n" : "=r" (v));	338	asm volatile ("rdpr %%tl, %0\n" : "=r" (v));
290		339
291	return v;	340	return v;
292	}	341	}
293		342
294	/** Read Trap Base Address register.	343	/** Read Trap Base Address register.
295	*	344	*
296	* @return Current value in TBA.	345	* @return Current value in TBA.
297	*/	346	*/
298	static inline uint64_t tba_read(void)	347	static inline uint64_t tba_read(void)
299	{	348	{
300	uint64_t v;	349	uint64_t v;
301		350
302	asm volatile ("rdpr %%tba, %0\n" : "=r" (v));	351	asm volatile ("rdpr %%tba, %0\n" : "=r" (v));
303		352
304	return v;	353	return v;
305	}	354	}
306		355
307	/** Write Trap Base Address register.	356	/** Write Trap Base Address register.
308	*	357	*
309	* @param v New value of TBA.	358	* @param v New value of TBA.
310	*/	359	*/
311	static inline void tba_write(uint64_t v)	360	static inline void tba_write(uint64_t v)
312	{	361	{
313	asm volatile ("wrpr %0, %1, %%tba\n" : : "r" (v), "i" (0));	362	asm volatile ("wrpr %0, %1, %%tba\n" : : "r" (v), "i" (0));
314	}	363	}
315		364
316	/** Load uint64_t from alternate space.	365	/** Load uint64_t from alternate space.
317	*	366	*
318	* @param asi ASI determining the alternate space.	367	* @param asi ASI determining the alternate space.
319	* @param va Virtual address within the ASI.	368	* @param va Virtual address within the ASI.
320	*	369	*
321	* @return Value read from the virtual address in the specified address space.	370	* @return Value read from the virtual address in the specified address space.
322	*/	371	*/
323	static inline uint64_t asi_u64_read(asi_t asi, uintptr_t va)	372	static inline uint64_t asi_u64_read(asi_t asi, uintptr_t va)
324	{	373	{
325	uint64_t v;	374	uint64_t v;
326		375
327	asm volatile ("ldxa [%1] %2, %0\n" : "=r" (v) : "r" (va), "i" ((unsigned) asi));	376	asm volatile ("ldxa [%1] %2, %0\n" : "=r" (v) : "r" (va), "i" ((unsigned) asi));
328		377
329	return v;	378	return v;
330	}	379	}
331		380
332	/** Store uint64_t to alternate space.	381	/** Store uint64_t to alternate space.
333	*	382	*
334	* @param asi ASI determining the alternate space.	383	* @param asi ASI determining the alternate space.
335	* @param va Virtual address within the ASI.	384	* @param va Virtual address within the ASI.
336	* @param v Value to be written.	385	* @param v Value to be written.
337	*/	386	*/
338	static inline void asi_u64_write(asi_t asi, uintptr_t va, uint64_t v)	387	static inline void asi_u64_write(asi_t asi, uintptr_t va, uint64_t v)
339	{	388	{
340	asm volatile ("stxa %0, [%1] %2\n" : : "r" (v), "r" (va), "i" ((unsigned) asi) : "memory");	389	asm volatile ("stxa %0, [%1] %2\n" : : "r" (v), "r" (va), "i" ((unsigned) asi) : "memory");
341	}	390	}
342		391
343	/** Flush all valid register windows to memory. */	392	/** Flush all valid register windows to memory. */
344	static inline void flushw(void)	393	static inline void flushw(void)
345	{	394	{
346	asm volatile ("flushw\n");	395	asm volatile ("flushw\n");
347	}	396	}
348		397
349	/** Switch to nucleus by setting TL to 1. */	398	/** Switch to nucleus by setting TL to 1. */
350	static inline void nucleus_enter(void)	399	static inline void nucleus_enter(void)
351	{	400	{
352	asm volatile ("wrpr %g0, 1, %tl\n");	401	asm volatile ("wrpr %g0, 1, %tl\n");
353	}	402	}
354		403
355	/** Switch from nucleus by setting TL to 0. */	404	/** Switch from nucleus by setting TL to 0. */
356	static inline void nucleus_leave(void)	405	static inline void nucleus_leave(void)
357	{	406	{
358	asm volatile ("wrpr %g0, %g0, %tl\n");	407	asm volatile ("wrpr %g0, %g0, %tl\n");
359	}	408	}
360		409
361	/** Read UPA_CONFIG/FIREPLANE_CONFIG register.	410	/** Read UPA_CONFIG/FIREPLANE_CONFIG register.
362	*	411	*
363	* @return	412	* @return
364	* Value of the UPA_CONFIG register in US,	413	* Value of the UPA_CONFIG register in US,
365	* value of the FIREPLANE_CONFIG on US3.	414	* value of the FIREPLANE_CONFIG on US3.
366	*/	415	*/
367	static inline uint64_t icbus_config_read(void)	416	static inline uint64_t icbus_config_read(void)
368	{	417	{
369	return asi_u64_read(ASI_ICBUS_CONFIG, 0);	418	return asi_u64_read(ASI_ICBUS_CONFIG, 0);
370	}	419	}
371		420
372	extern void cpu_halt(void);	421	extern void cpu_halt(void);
373	extern void cpu_sleep(void);	422	extern void cpu_sleep(void);
374	extern void asm_delay_loop(const uint32_t usec);	423	extern void asm_delay_loop(const uint32_t usec);
375		424
376	extern uint64_t read_from_ag_g7(void);	425	extern uint64_t read_from_ag_g7(void);
377	extern void write_to_ag_g6(uint64_t val);	426	extern void write_to_ag_g6(uint64_t val);
378	extern void write_to_ag_g7(uint64_t val);	427	extern void write_to_ag_g7(uint64_t val);
379	extern void write_to_ig_g6(uint64_t val);	428	extern void write_to_ig_g6(uint64_t val);
380		429
381	extern void switch_to_userspace(uint64_t pc, uint64_t sp, uint64_t uarg);	430	extern void switch_to_userspace(uint64_t pc, uint64_t sp, uint64_t uarg);
382		431
383	#endif	432	#endif
384		433
385	/** @}	434	/** @}
386	*/	435	*/
387		436

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(root)/branches/sparc/kernel/arch/sparc64/include/asm.h – Rev 3479 → 3593