WebSVN – HelenOS – Diff – /branches/sparc/kernel/arch/ppc32/src/mm/tlb.c


/*
 * Copyright (c) 2006 Martin Decky
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup ppc32mm
 * @{
 */
/** @file
 */
 
#include <mm/tlb.h>
#include <arch/mm/tlb.h>
#include <arch/interrupt.h>
#include <mm/as.h>
#include <arch.h>
#include <print.h>
#include <symtab.h>
 
 
/** Try to find PTE for faulting address
 *
 * Try to find PTE for faulting address.
 * The as->lock must be held on entry to this function
 * if lock is true.
 *
 * @param as        Address space.
 * @param lock      Lock/unlock the address space.
 * @param badvaddr  Faulting virtual address.
 * @param access    Access mode that caused the fault.
 * @param istate    Pointer to interrupted state.
 * @param pfrc      Pointer to variable where as_page_fault() return code
 *          will be stored.
 * @return      PTE on success, NULL otherwise.
 *
 */
static pte_t *
find_mapping_and_check(as_t *as, bool lock, uintptr_t badvaddr, int access,
    istate_t *istate, int *pfrc)
{
    /*
     * Check if the mapping exists in page tables.
     */
    pte_t *pte = page_mapping_find(as, badvaddr);
    if ((pte) && (pte->p)) {
        /*
         * Mapping found in page tables.
         * Immediately succeed.
         */
        return pte;
    } else {
        int rc;
   
        /*
         * Mapping not found in page tables.
         * Resort to higher-level page fault handler.
         */
        page_table_unlock(as, lock);
        switch (rc = as_page_fault(badvaddr, access, istate)) {
        case AS_PF_OK:
            /*
             * The higher-level page fault handler succeeded,
             * The mapping ought to be in place.
             */
            page_table_lock(as, lock);
            pte = page_mapping_find(as, badvaddr);
            ASSERT((pte) && (pte->p));
            *pfrc = 0;
            return pte;
        case AS_PF_DEFER:
            page_table_lock(as, lock);
            *pfrc = rc;
            return NULL;
        case AS_PF_FAULT:
            page_table_lock(as, lock);
 
            *pfrc = rc;
            return NULL;
        default:
            panic("unexpected rc (%d)\n", rc);
        }  
    }
}
 
 
static void pht_refill_fail(uintptr_t badvaddr, istate_t *istate)
{
    char *symbol = "";
    char *sym2 = "";
 
    char *s = get_symtab_entry(istate->pc);
    if (s)
        symbol = s;
    s = get_symtab_entry(istate->lr);
    if (s)
        sym2 = s;
    panic("%p: PHT Refill Exception at %p (%s<-%s)\n", badvaddr,
        istate->pc, symbol, sym2);
}
 
 
static void pht_insert(const uintptr_t vaddr, const pfn_t pfn)
{
    uint32_t page = (vaddr >> 12) & 0xffff;
    uint32_t api = (vaddr >> 22) & 0x3f;
   
    uint32_t vsid;
    asm volatile (
        "mfsrin %0, %1\n"
        : "=r" (vsid)
        : "r" (vaddr)
    );
   
    uint32_t sdr1;
    asm volatile (
        "mfsdr1 %0\n"
        : "=r" (sdr1)
    );
    phte_t *phte = (phte_t *) PA2KA(sdr1 & 0xffff0000);
   
    /* Primary hash (xor) */
    uint32_t h = 0;
    uint32_t hash = vsid ^ page;
    uint32_t base = (hash & 0x3ff) << 3;
    uint32_t i;
    bool found = false;
   
    /* Find unused or colliding
       PTE in PTEG */
    for (i = 0; i < 8; i++) {
        if ((!phte[base + i].v) || ((phte[base + i].vsid == vsid) &&
            (phte[base + i].api == api))) {
            found = true;
            break;
        }
    }
   
    if (!found) {
        /* Secondary hash (not) */
        uint32_t base2 = (~hash & 0x3ff) << 3;
       
        /* Find unused or colliding
           PTE in PTEG */
        for (i = 0; i < 8; i++) {
            if ((!phte[base2 + i].v) ||
                ((phte[base2 + i].vsid == vsid) &&
                (phte[base2 + i].api == api))) {
                found = true;
                base = base2;
                h = 1;
                break;
            }
        }
       
        if (!found) {
            // TODO: A/C precedence groups
            i = page % 8;
        }
    }
   
    phte[base + i].v = 1;
    phte[base + i].vsid = vsid;
    phte[base + i].h = h;
    phte[base + i].api = api;
    phte[base + i].rpn = pfn;
    phte[base + i].r = 0;
    phte[base + i].c = 0;
    phte[base + i].pp = 2; // FIXME
}
 
 
static void pht_real_insert(const uintptr_t vaddr, const pfn_t pfn)
{
    uint32_t page = (vaddr >> 12) & 0xffff;
    uint32_t api = (vaddr >> 22) & 0x3f;
   
    uint32_t vsid;
    asm volatile (
        "mfsrin %0, %1\n"
        : "=r" (vsid)
        : "r" (vaddr)
    );
   
    uint32_t sdr1;
    asm volatile (
        "mfsdr1 %0\n"
        : "=r" (sdr1)
    );
    phte_t *phte_physical = (phte_t *) (sdr1 & 0xffff0000);
   
    /* Primary hash (xor) */
    uint32_t h = 0;
    uint32_t hash = vsid ^ page;
    uint32_t base = (hash & 0x3ff) << 3;
    uint32_t i;
    bool found = false;
   
    /* Find unused or colliding
       PTE in PTEG */
    for (i = 0; i < 8; i++) {
        if ((!phte_physical[base + i].v) ||
            ((phte_physical[base + i].vsid == vsid) &&
            (phte_physical[base + i].api == api))) {
            found = true;
            break;
        }
    }
   
    if (!found) {
        /* Secondary hash (not) */
        uint32_t base2 = (~hash & 0x3ff) << 3;
       
        /* Find unused or colliding
           PTE in PTEG */
        for (i = 0; i < 8; i++) {
            if ((!phte_physical[base2 + i].v) ||
                ((phte_physical[base2 + i].vsid == vsid) &&
                (phte_physical[base2 + i].api == api))) {
                found = true;
                base = base2;
                h = 1;
                break;
            }
        }
       
        if (!found) {
            // TODO: A/C precedence groups
            i = page % 8;
        }
    }
   
    phte_physical[base + i].v = 1;
    phte_physical[base + i].vsid = vsid;
    phte_physical[base + i].h = h;
    phte_physical[base + i].api = api;
    phte_physical[base + i].rpn = pfn;
    phte_physical[base + i].r = 0;
    phte_physical[base + i].c = 0;
    phte_physical[base + i].pp = 2; // FIXME
}
 
 
/** Process Instruction/Data Storage Interrupt
 *
 * @param n     Interrupt vector number.
 * @param istate    Interrupted register context.
 *
 */
void pht_refill(int n, istate_t *istate)
{
    uintptr_t badvaddr;
    pte_t *pte;
    int pfrc;
    as_t *as;
    bool lock;
   
    if (AS == NULL) {
        as = AS_KERNEL;
        lock = false;
    } else {
        as = AS;
        lock = true;
    }
   
    if (n == VECTOR_DATA_STORAGE) {
        asm volatile (
            "mfdar %0\n"
            : "=r" (badvaddr)
        );
    } else
        badvaddr = istate->pc;
       
    page_table_lock(as, lock);
   
    pte = find_mapping_and_check(as, lock, badvaddr,
        PF_ACCESS_READ /* FIXME */, istate, &pfrc);
    if (!pte) {
        switch (pfrc) {
        case AS_PF_FAULT:
            goto fail;
            break;
        case AS_PF_DEFER:
            /*
             * The page fault came during copy_from_uspace()
             * or copy_to_uspace().
             */
            page_table_unlock(as, lock);
            return;
        default:
            panic("Unexpected pfrc (%d)\n", pfrc);
        }
    }
   
    pte->a = 1; /* Record access to PTE */
    pht_insert(badvaddr, pte->pfn);
   
    page_table_unlock(as, lock);
    return;
   
fail:
    page_table_unlock(as, lock);
    pht_refill_fail(badvaddr, istate);
}
 
 
/** Process Instruction/Data Storage Interrupt in Real Mode
 *
 * @param n     Interrupt vector number.
 * @param istate    Interrupted register context.
 *
 */
bool pht_real_refill(int n, istate_t *istate)
{
    uintptr_t badvaddr;
   
    if (n == VECTOR_DATA_STORAGE) {
        asm volatile (
            "mfdar %0\n"
            : "=r" (badvaddr)
        );
    } else
        badvaddr = istate->pc;
   
    uint32_t physmem;
    asm volatile (
        "mfsprg3 %0\n"
        : "=r" (physmem)
    );
   
    if ((badvaddr >= PA2KA(0)) && (badvaddr < PA2KA(physmem))) {
        pht_real_insert(badvaddr, KA2PA(badvaddr) >> 12);
        return true;
    }
   
    return false;
}
 
 
void tlb_arch_init(void)
{
    tlb_invalidate_all();
}
 
 
void tlb_invalidate_all(void)
{
    asm volatile (
        "tlbia\n"
        "tlbsync\n"
    );
}
 
 
void tlb_invalidate_asid(asid_t asid)
{
    uint32_t sdr1;
    asm volatile (
        "mfsdr1 %0\n"
        : "=r" (sdr1)
    );
    phte_t *phte = (phte_t *) PA2KA(sdr1 & 0xffff0000);
   
    uint32_t i;
    for (i = 0; i < 8192; i++) {
        if ((phte[i].v) && (phte[i].vsid >= (asid << 4)) &&
            (phte[i].vsid < ((asid << 4) + 16)))
            phte[i].v = 0;
    }
    tlb_invalidate_all();
}
 
 
void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt)
{
    // TODO
    tlb_invalidate_all();
}
 
 
#define PRINT_BAT(name, ureg, lreg) \
    asm volatile ( \
        "mfspr %0," #ureg "\n" \
        "mfspr %1," #lreg "\n" \
        : "=r" (upper), "=r" (lower) \
    ); \
    mask = (upper & 0x1ffc) >> 2; \
    if (upper & 3) { \
        uint32_t tmp = mask; \
        length = 128; \
        while (tmp) { \
            if ((tmp & 1) == 0) { \
                printf("ibat[0]: error in mask\n"); \
                break; \
            } \
            length <<= 1; \
            tmp >>= 1; \
        } \
    } else \
        length = 0; \
    printf(name ": page=%.*p frame=%.*p length=%d KB (mask=%#x)%s%s\n", \
        sizeof(upper) * 2, upper & 0xffff0000, sizeof(lower) * 2, \
        lower & 0xffff0000, length, mask, \
        ((upper >> 1) & 1) ? " supervisor" : "", \
        (upper & 1) ? " user" : "");
 
 
void tlb_print(void)
{
    uint32_t sr;
   
    for (sr = 0; sr < 16; sr++) {
        uint32_t vsid;
        asm volatile (
            "mfsrin %0, %1\n"
            : "=r" (vsid)
            : "r" (sr << 28)
        );
        printf("vsid[%d]: VSID=%.*p (ASID=%d)%s%s\n", sr,
            sizeof(vsid) * 2, vsid & 0xffffff, (vsid & 0xffffff) >> 4,
            ((vsid >> 30) & 1) ? " supervisor" : "",
            ((vsid >> 29) & 1) ? " user" : "");
    }
   
    uint32_t upper;
    uint32_t lower;
    uint32_t mask;
    uint32_t length;
   
    PRINT_BAT("ibat[0]", 528, 529);
    PRINT_BAT("ibat[1]", 530, 531);
    PRINT_BAT("ibat[2]", 532, 533);
    PRINT_BAT("ibat[3]", 534, 535);
   
    PRINT_BAT("dbat[0]", 536, 537);
    PRINT_BAT("dbat[1]", 538, 539);
    PRINT_BAT("dbat[2]", 540, 541);
    PRINT_BAT("dbat[3]", 542, 543);
}
 
/** @}
 */
 

Rev 3343	Rev 3593
1	/*	1	/*
2	* Copyright (c) 2006 Martin Decky	2	* Copyright (c) 2006 Martin Decky
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	/** @addtogroup ppc32mm	29	/** @addtogroup ppc32mm
30	* @{	30	* @{
31	*/	31	*/
32	/** @file	32	/** @file
33	*/	33	*/
34		34
35	#include <mm/tlb.h>	35	#include <mm/tlb.h>
36	#include <arch/mm/tlb.h>	36	#include <arch/mm/tlb.h>
37	#include <arch/interrupt.h>	37	#include <arch/interrupt.h>
38	#include <mm/as.h>	38	#include <mm/as.h>
39	#include <arch.h>	39	#include <arch.h>
40	#include <print.h>	40	#include <print.h>
41	#include <symtab.h>	41	#include <symtab.h>
42		42
43		43
44	/** Try to find PTE for faulting address	44	/** Try to find PTE for faulting address
45	*	45	*
46	* Try to find PTE for faulting address.	46	* Try to find PTE for faulting address.
47	* The as->lock must be held on entry to this function	47	* The as->lock must be held on entry to this function
48	* if lock is true.	48	* if lock is true.
49	*	49	*
50	* @param as Address space.	50	* @param as Address space.
51	* @param lock Lock/unlock the address space.	51	* @param lock Lock/unlock the address space.
52	* @param badvaddr Faulting virtual address.	52	* @param badvaddr Faulting virtual address.
53	* @param access Access mode that caused the fault.	53	* @param access Access mode that caused the fault.
54	* @param istate Pointer to interrupted state.	54	* @param istate Pointer to interrupted state.
55	* @param pfrc Pointer to variable where as_page_fault() return code	55	* @param pfrc Pointer to variable where as_page_fault() return code
56	* will be stored.	56	* will be stored.
57	* @return PTE on success, NULL otherwise.	57	* @return PTE on success, NULL otherwise.
58	*	58	*
59	*/	59	*/
60	static pte_t *	60	static pte_t *
61	find_mapping_and_check(as_t *as, bool lock, uintptr_t badvaddr, int access,	61	find_mapping_and_check(as_t *as, bool lock, uintptr_t badvaddr, int access,
62	istate_t istate, int pfrc)	62	istate_t istate, int pfrc)
63	{	63	{
64	/*	64	/*
65	* Check if the mapping exists in page tables.	65	* Check if the mapping exists in page tables.
66	*/	66	*/
67	pte_t *pte = page_mapping_find(as, badvaddr);	67	pte_t *pte = page_mapping_find(as, badvaddr);
68	if ((pte) && (pte->p)) {	68	if ((pte) && (pte->p)) {
69	/*	69	/*
70	* Mapping found in page tables.	70	* Mapping found in page tables.
71	* Immediately succeed.	71	* Immediately succeed.
72	*/	72	*/
73	return pte;	73	return pte;
74	} else {	74	} else {
75	int rc;	75	int rc;
76		76
77	/*	77	/*
78	* Mapping not found in page tables.	78	* Mapping not found in page tables.
79	* Resort to higher-level page fault handler.	79	* Resort to higher-level page fault handler.
80	*/	80	*/
81	page_table_unlock(as, lock);	81	page_table_unlock(as, lock);
82	switch (rc = as_page_fault(badvaddr, access, istate)) {	82	switch (rc = as_page_fault(badvaddr, access, istate)) {
83	case AS_PF_OK:	83	case AS_PF_OK:
84	/*	84	/*
85	* The higher-level page fault handler succeeded,	85	* The higher-level page fault handler succeeded,
86	* The mapping ought to be in place.	86	* The mapping ought to be in place.
87	*/	87	*/
88	page_table_lock(as, lock);	88	page_table_lock(as, lock);
89	pte = page_mapping_find(as, badvaddr);	89	pte = page_mapping_find(as, badvaddr);
90	ASSERT((pte) && (pte->p));	90	ASSERT((pte) && (pte->p));
91	*pfrc = 0;	91	*pfrc = 0;
92	return pte;	92	return pte;
93	case AS_PF_DEFER:	93	case AS_PF_DEFER:
94	page_table_lock(as, lock);	94	page_table_lock(as, lock);
95	*pfrc = rc;	95	*pfrc = rc;
96	return NULL;	96	return NULL;
97	case AS_PF_FAULT:	97	case AS_PF_FAULT:
98	page_table_lock(as, lock);	98	page_table_lock(as, lock);
99	printf("Page fault.\n");	-
100	*pfrc = rc;	99	*pfrc = rc;
101	return NULL;	100	return NULL;
102	default:	101	default:
103	panic("unexpected rc (%d)\n", rc);	102	panic("unexpected rc (%d)\n", rc);
104	}	103	}
105	}	104	}
106	}	105	}
107		106
108		107
109	static void pht_refill_fail(uintptr_t badvaddr, istate_t *istate)	108	static void pht_refill_fail(uintptr_t badvaddr, istate_t *istate)
110	{	109	{
111	char *symbol = "";	110	char *symbol = "";
112	char *sym2 = "";	111	char *sym2 = "";
113		112
114	char *s = get_symtab_entry(istate->pc);	113	char *s = get_symtab_entry(istate->pc);
115	if (s)	114	if (s)
116	symbol = s;	115	symbol = s;
117	s = get_symtab_entry(istate->lr);	116	s = get_symtab_entry(istate->lr);
118	if (s)	117	if (s)
119	sym2 = s;	118	sym2 = s;
120	panic("%p: PHT Refill Exception at %p (%s<-%s)\n", badvaddr,	119	panic("%p: PHT Refill Exception at %p (%s<-%s)\n", badvaddr,
121	istate->pc, symbol, sym2);	120	istate->pc, symbol, sym2);
122	}	121	}
123		122
124		123
125	static void pht_insert(const uintptr_t vaddr, const pfn_t pfn)	124	static void pht_insert(const uintptr_t vaddr, const pfn_t pfn)
126	{	125	{
127	uint32_t page = (vaddr >> 12) & 0xffff;	126	uint32_t page = (vaddr >> 12) & 0xffff;
128	uint32_t api = (vaddr >> 22) & 0x3f;	127	uint32_t api = (vaddr >> 22) & 0x3f;
129		128
130	uint32_t vsid;	129	uint32_t vsid;
131	asm volatile (	130	asm volatile (
132	"mfsrin %0, %1\n"	131	"mfsrin %0, %1\n"
133	: "=r" (vsid)	132	: "=r" (vsid)
134	: "r" (vaddr)	133	: "r" (vaddr)
135	);	134	);
136		135
137	uint32_t sdr1;	136	uint32_t sdr1;
138	asm volatile (	137	asm volatile (
139	"mfsdr1 %0\n"	138	"mfsdr1 %0\n"
140	: "=r" (sdr1)	139	: "=r" (sdr1)
141	);	140	);
142	phte_t phte = (phte_t ) PA2KA(sdr1 & 0xffff0000);	141	phte_t phte = (phte_t ) PA2KA(sdr1 & 0xffff0000);
143		142
144	/* Primary hash (xor) */	143	/* Primary hash (xor) */
145	uint32_t h = 0;	144	uint32_t h = 0;
146	uint32_t hash = vsid ^ page;	145	uint32_t hash = vsid ^ page;
147	uint32_t base = (hash & 0x3ff) << 3;	146	uint32_t base = (hash & 0x3ff) << 3;
148	uint32_t i;	147	uint32_t i;
149	bool found = false;	148	bool found = false;
150		149
151	/* Find unused or colliding	150	/* Find unused or colliding
152	PTE in PTEG */	151	PTE in PTEG */
153	for (i = 0; i < 8; i++) {	152	for (i = 0; i < 8; i++) {
154	if ((!phte[base + i].v) \|\| ((phte[base + i].vsid == vsid) &&	153	if ((!phte[base + i].v) \|\| ((phte[base + i].vsid == vsid) &&
155	(phte[base + i].api == api))) {	154	(phte[base + i].api == api))) {
156	found = true;	155	found = true;
157	break;	156	break;
158	}	157	}
159	}	158	}
160		159
161	if (!found) {	160	if (!found) {
162	/* Secondary hash (not) */	161	/* Secondary hash (not) */
163	uint32_t base2 = (~hash & 0x3ff) << 3;	162	uint32_t base2 = (~hash & 0x3ff) << 3;
164		163
165	/* Find unused or colliding	164	/* Find unused or colliding
166	PTE in PTEG */	165	PTE in PTEG */
167	for (i = 0; i < 8; i++) {	166	for (i = 0; i < 8; i++) {
168	if ((!phte[base2 + i].v) \|\|	167	if ((!phte[base2 + i].v) \|\|
169	((phte[base2 + i].vsid == vsid) &&	168	((phte[base2 + i].vsid == vsid) &&
170	(phte[base2 + i].api == api))) {	169	(phte[base2 + i].api == api))) {
171	found = true;	170	found = true;
172	base = base2;	171	base = base2;
173	h = 1;	172	h = 1;
174	break;	173	break;
175	}	174	}
176	}	175	}
177		176
178	if (!found) {	177	if (!found) {
179	// TODO: A/C precedence groups	178	// TODO: A/C precedence groups
180	i = page % 8;	179	i = page % 8;
181	}	180	}
182	}	181	}
183		182
184	phte[base + i].v = 1;	183	phte[base + i].v = 1;
185	phte[base + i].vsid = vsid;	184	phte[base + i].vsid = vsid;
186	phte[base + i].h = h;	185	phte[base + i].h = h;
187	phte[base + i].api = api;	186	phte[base + i].api = api;
188	phte[base + i].rpn = pfn;	187	phte[base + i].rpn = pfn;
189	phte[base + i].r = 0;	188	phte[base + i].r = 0;
190	phte[base + i].c = 0;	189	phte[base + i].c = 0;
191	phte[base + i].pp = 2; // FIXME	190	phte[base + i].pp = 2; // FIXME
192	}	191	}
193		192
194		193
195	static void pht_real_insert(const uintptr_t vaddr, const pfn_t pfn)	194	static void pht_real_insert(const uintptr_t vaddr, const pfn_t pfn)
196	{	195	{
197	uint32_t page = (vaddr >> 12) & 0xffff;	196	uint32_t page = (vaddr >> 12) & 0xffff;
198	uint32_t api = (vaddr >> 22) & 0x3f;	197	uint32_t api = (vaddr >> 22) & 0x3f;
199		198
200	uint32_t vsid;	199	uint32_t vsid;
201	asm volatile (	200	asm volatile (
202	"mfsrin %0, %1\n"	201	"mfsrin %0, %1\n"
203	: "=r" (vsid)	202	: "=r" (vsid)
204	: "r" (vaddr)	203	: "r" (vaddr)
205	);	204	);
206		205
207	uint32_t sdr1;	206	uint32_t sdr1;
208	asm volatile (	207	asm volatile (
209	"mfsdr1 %0\n"	208	"mfsdr1 %0\n"
210	: "=r" (sdr1)	209	: "=r" (sdr1)
211	);	210	);
212	phte_t phte_physical = (phte_t ) (sdr1 & 0xffff0000);	211	phte_t phte_physical = (phte_t ) (sdr1 & 0xffff0000);
213		212
214	/* Primary hash (xor) */	213	/* Primary hash (xor) */
215	uint32_t h = 0;	214	uint32_t h = 0;
216	uint32_t hash = vsid ^ page;	215	uint32_t hash = vsid ^ page;
217	uint32_t base = (hash & 0x3ff) << 3;	216	uint32_t base = (hash & 0x3ff) << 3;
218	uint32_t i;	217	uint32_t i;
219	bool found = false;	218	bool found = false;
220		219
221	/* Find unused or colliding	220	/* Find unused or colliding
222	PTE in PTEG */	221	PTE in PTEG */
223	for (i = 0; i < 8; i++) {	222	for (i = 0; i < 8; i++) {
224	if ((!phte_physical[base + i].v) \|\|	223	if ((!phte_physical[base + i].v) \|\|
225	((phte_physical[base + i].vsid == vsid) &&	224	((phte_physical[base + i].vsid == vsid) &&
226	(phte_physical[base + i].api == api))) {	225	(phte_physical[base + i].api == api))) {
227	found = true;	226	found = true;
228	break;	227	break;
229	}	228	}
230	}	229	}
231		230
232	if (!found) {	231	if (!found) {
233	/* Secondary hash (not) */	232	/* Secondary hash (not) */
234	uint32_t base2 = (~hash & 0x3ff) << 3;	233	uint32_t base2 = (~hash & 0x3ff) << 3;
235		234
236	/* Find unused or colliding	235	/* Find unused or colliding
237	PTE in PTEG */	236	PTE in PTEG */
238	for (i = 0; i < 8; i++) {	237	for (i = 0; i < 8; i++) {
239	if ((!phte_physical[base2 + i].v) \|\|	238	if ((!phte_physical[base2 + i].v) \|\|
240	((phte_physical[base2 + i].vsid == vsid) &&	239	((phte_physical[base2 + i].vsid == vsid) &&
241	(phte_physical[base2 + i].api == api))) {	240	(phte_physical[base2 + i].api == api))) {
242	found = true;	241	found = true;
243	base = base2;	242	base = base2;
244	h = 1;	243	h = 1;
245	break;	244	break;
246	}	245	}
247	}	246	}
248		247
249	if (!found) {	248	if (!found) {
250	// TODO: A/C precedence groups	249	// TODO: A/C precedence groups
251	i = page % 8;	250	i = page % 8;
252	}	251	}
253	}	252	}
254		253
255	phte_physical[base + i].v = 1;	254	phte_physical[base + i].v = 1;
256	phte_physical[base + i].vsid = vsid;	255	phte_physical[base + i].vsid = vsid;
257	phte_physical[base + i].h = h;	256	phte_physical[base + i].h = h;
258	phte_physical[base + i].api = api;	257	phte_physical[base + i].api = api;
259	phte_physical[base + i].rpn = pfn;	258	phte_physical[base + i].rpn = pfn;
260	phte_physical[base + i].r = 0;	259	phte_physical[base + i].r = 0;
261	phte_physical[base + i].c = 0;	260	phte_physical[base + i].c = 0;
262	phte_physical[base + i].pp = 2; // FIXME	261	phte_physical[base + i].pp = 2; // FIXME
263	}	262	}
264		263
265		264
266	/** Process Instruction/Data Storage Interrupt	265	/** Process Instruction/Data Storage Interrupt
267	*	266	*
268	* @param n Interrupt vector number.	267	* @param n Interrupt vector number.
269	* @param istate Interrupted register context.	268	* @param istate Interrupted register context.
270	*	269	*
271	*/	270	*/
272	void pht_refill(int n, istate_t *istate)	271	void pht_refill(int n, istate_t *istate)
273	{	272	{
274	uintptr_t badvaddr;	273	uintptr_t badvaddr;
275	pte_t *pte;	274	pte_t *pte;
276	int pfrc;	275	int pfrc;
277	as_t *as;	276	as_t *as;
278	bool lock;	277	bool lock;
279		278
280	if (AS == NULL) {	279	if (AS == NULL) {
281	as = AS_KERNEL;	280	as = AS_KERNEL;
282	lock = false;	281	lock = false;
283	} else {	282	} else {
284	as = AS;	283	as = AS;
285	lock = true;	284	lock = true;
286	}	285	}
287		286
288	if (n == VECTOR_DATA_STORAGE) {	287	if (n == VECTOR_DATA_STORAGE) {
289	asm volatile (	288	asm volatile (
290	"mfdar %0\n"	289	"mfdar %0\n"
291	: "=r" (badvaddr)	290	: "=r" (badvaddr)
292	);	291	);
293	} else	292	} else
294	badvaddr = istate->pc;	293	badvaddr = istate->pc;
295		294
296	page_table_lock(as, lock);	295	page_table_lock(as, lock);
297		296
298	pte = find_mapping_and_check(as, lock, badvaddr,	297	pte = find_mapping_and_check(as, lock, badvaddr,
299	PF_ACCESS_READ /* FIXME */, istate, &pfrc);	298	PF_ACCESS_READ /* FIXME */, istate, &pfrc);
300	if (!pte) {	299	if (!pte) {
301	switch (pfrc) {	300	switch (pfrc) {
302	case AS_PF_FAULT:	301	case AS_PF_FAULT:
303	goto fail;	302	goto fail;
304	break;	303	break;
305	case AS_PF_DEFER:	304	case AS_PF_DEFER:
306	/*	305	/*
307	* The page fault came during copy_from_uspace()	306	* The page fault came during copy_from_uspace()
308	* or copy_to_uspace().	307	* or copy_to_uspace().
309	*/	308	*/
310	page_table_unlock(as, lock);	309	page_table_unlock(as, lock);
311	return;	310	return;
312	default:	311	default:
313	panic("Unexpected pfrc (%d)\n", pfrc);	312	panic("Unexpected pfrc (%d)\n", pfrc);
314	}	313	}
315	}	314	}
316		315
317	pte->a = 1; /* Record access to PTE */	316	pte->a = 1; /* Record access to PTE */
318	pht_insert(badvaddr, pte->pfn);	317	pht_insert(badvaddr, pte->pfn);
319		318
320	page_table_unlock(as, lock);	319	page_table_unlock(as, lock);
321	return;	320	return;
322		321
323	fail:	322	fail:
324	page_table_unlock(as, lock);	323	page_table_unlock(as, lock);
325	pht_refill_fail(badvaddr, istate);	324	pht_refill_fail(badvaddr, istate);
326	}	325	}
327		326
328		327
329	/** Process Instruction/Data Storage Interrupt in Real Mode	328	/** Process Instruction/Data Storage Interrupt in Real Mode
330	*	329	*
331	* @param n Interrupt vector number.	330	* @param n Interrupt vector number.
332	* @param istate Interrupted register context.	331	* @param istate Interrupted register context.
333	*	332	*
334	*/	333	*/
335	bool pht_real_refill(int n, istate_t *istate)	334	bool pht_real_refill(int n, istate_t *istate)
336	{	335	{
337	uintptr_t badvaddr;	336	uintptr_t badvaddr;
338		337
339	if (n == VECTOR_DATA_STORAGE) {	338	if (n == VECTOR_DATA_STORAGE) {
340	asm volatile (	339	asm volatile (
341	"mfdar %0\n"	340	"mfdar %0\n"
342	: "=r" (badvaddr)	341	: "=r" (badvaddr)
343	);	342	);
344	} else	343	} else
345	badvaddr = istate->pc;	344	badvaddr = istate->pc;
346		345
347	uint32_t physmem;	346	uint32_t physmem;
348	asm volatile (	347	asm volatile (
349	"mfsprg3 %0\n"	348	"mfsprg3 %0\n"
350	: "=r" (physmem)	349	: "=r" (physmem)
351	);	350	);
352		351
353	if ((badvaddr >= PA2KA(0)) && (badvaddr < PA2KA(physmem))) {	352	if ((badvaddr >= PA2KA(0)) && (badvaddr < PA2KA(physmem))) {
354	pht_real_insert(badvaddr, KA2PA(badvaddr) >> 12);	353	pht_real_insert(badvaddr, KA2PA(badvaddr) >> 12);
355	return true;	354	return true;
356	}	355	}
357		356
358	return false;	357	return false;
359	}	358	}
360		359
361		360
362	void tlb_arch_init(void)	361	void tlb_arch_init(void)
363	{	362	{
364	tlb_invalidate_all();	363	tlb_invalidate_all();
365	}	364	}
366		365
367		366
368	void tlb_invalidate_all(void)	367	void tlb_invalidate_all(void)
369	{	368	{
370	asm volatile (	369	asm volatile (
371	"tlbia\n"	370	"tlbia\n"
372	"tlbsync\n"	371	"tlbsync\n"
373	);	372	);
374	}	373	}
375		374
376		375
377	void tlb_invalidate_asid(asid_t asid)	376	void tlb_invalidate_asid(asid_t asid)
378	{	377	{
379	uint32_t sdr1;	378	uint32_t sdr1;
380	asm volatile (	379	asm volatile (
381	"mfsdr1 %0\n"	380	"mfsdr1 %0\n"
382	: "=r" (sdr1)	381	: "=r" (sdr1)
383	);	382	);
384	phte_t phte = (phte_t ) PA2KA(sdr1 & 0xffff0000);	383	phte_t phte = (phte_t ) PA2KA(sdr1 & 0xffff0000);
385		384
386	uint32_t i;	385	uint32_t i;
387	for (i = 0; i < 8192; i++) {	386	for (i = 0; i < 8192; i++) {
388	if ((phte[i].v) && (phte[i].vsid >= (asid << 4)) &&	387	if ((phte[i].v) && (phte[i].vsid >= (asid << 4)) &&
389	(phte[i].vsid < ((asid << 4) + 16)))	388	(phte[i].vsid < ((asid << 4) + 16)))
390	phte[i].v = 0;	389	phte[i].v = 0;
391	}	390	}
392	tlb_invalidate_all();	391	tlb_invalidate_all();
393	}	392	}
394		393
395		394
396	void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt)	395	void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt)
397	{	396	{
398	// TODO	397	// TODO
399	tlb_invalidate_all();	398	tlb_invalidate_all();
400	}	399	}
401		400
402		401
403	#define PRINT_BAT(name, ureg, lreg) \	402	#define PRINT_BAT(name, ureg, lreg) \
404	asm volatile ( \	403	asm volatile ( \
405	"mfspr %0," #ureg "\n" \	404	"mfspr %0," #ureg "\n" \
406	"mfspr %1," #lreg "\n" \	405	"mfspr %1," #lreg "\n" \
407	: "=r" (upper), "=r" (lower) \	406	: "=r" (upper), "=r" (lower) \
408	); \	407	); \
409	mask = (upper & 0x1ffc) >> 2; \	408	mask = (upper & 0x1ffc) >> 2; \
410	if (upper & 3) { \	409	if (upper & 3) { \
411	uint32_t tmp = mask; \	410	uint32_t tmp = mask; \
412	length = 128; \	411	length = 128; \
413	while (tmp) { \	412	while (tmp) { \
414	if ((tmp & 1) == 0) { \	413	if ((tmp & 1) == 0) { \
415	printf("ibat[0]: error in mask\n"); \	414	printf("ibat[0]: error in mask\n"); \
416	break; \	415	break; \
417	} \	416	} \
418	length <<= 1; \	417	length <<= 1; \
419	tmp >>= 1; \	418	tmp >>= 1; \
420	} \	419	} \
421	} else \	420	} else \
422	length = 0; \	421	length = 0; \
423	printf(name ": page=%.p frame=%.p length=%d KB (mask=%#x)%s%s\n", \	422	printf(name ": page=%.p frame=%.p length=%d KB (mask=%#x)%s%s\n", \
424	sizeof(upper) * 2, upper & 0xffff0000, sizeof(lower) * 2, \	423	sizeof(upper) * 2, upper & 0xffff0000, sizeof(lower) * 2, \
425	lower & 0xffff0000, length, mask, \	424	lower & 0xffff0000, length, mask, \
426	((upper >> 1) & 1) ? " supervisor" : "", \	425	((upper >> 1) & 1) ? " supervisor" : "", \
427	(upper & 1) ? " user" : "");	426	(upper & 1) ? " user" : "");
428		427
429		428
430	void tlb_print(void)	429	void tlb_print(void)
431	{	430	{
432	uint32_t sr;	431	uint32_t sr;
433		432
434	for (sr = 0; sr < 16; sr++) {	433	for (sr = 0; sr < 16; sr++) {
435	uint32_t vsid;	434	uint32_t vsid;
436	asm volatile (	435	asm volatile (
437	"mfsrin %0, %1\n"	436	"mfsrin %0, %1\n"
438	: "=r" (vsid)	437	: "=r" (vsid)
439	: "r" (sr << 28)	438	: "r" (sr << 28)
440	);	439	);
441	printf("vsid[%d]: VSID=%.*p (ASID=%d)%s%s\n", sr,	440	printf("vsid[%d]: VSID=%.*p (ASID=%d)%s%s\n", sr,
442	sizeof(vsid) * 2, vsid & 0xffffff, (vsid & 0xffffff) >> 4,	441	sizeof(vsid) * 2, vsid & 0xffffff, (vsid & 0xffffff) >> 4,
443	((vsid >> 30) & 1) ? " supervisor" : "",	442	((vsid >> 30) & 1) ? " supervisor" : "",
444	((vsid >> 29) & 1) ? " user" : "");	443	((vsid >> 29) & 1) ? " user" : "");
445	}	444	}
446		445
447	uint32_t upper;	446	uint32_t upper;
448	uint32_t lower;	447	uint32_t lower;
449	uint32_t mask;	448	uint32_t mask;
450	uint32_t length;	449	uint32_t length;
451		450
452	PRINT_BAT("ibat[0]", 528, 529);	451	PRINT_BAT("ibat[0]", 528, 529);
453	PRINT_BAT("ibat[1]", 530, 531);	452	PRINT_BAT("ibat[1]", 530, 531);
454	PRINT_BAT("ibat[2]", 532, 533);	453	PRINT_BAT("ibat[2]", 532, 533);
455	PRINT_BAT("ibat[3]", 534, 535);	454	PRINT_BAT("ibat[3]", 534, 535);
456		455
457	PRINT_BAT("dbat[0]", 536, 537);	456	PRINT_BAT("dbat[0]", 536, 537);
458	PRINT_BAT("dbat[1]", 538, 539);	457	PRINT_BAT("dbat[1]", 538, 539);
459	PRINT_BAT("dbat[2]", 540, 541);	458	PRINT_BAT("dbat[2]", 540, 541);
460	PRINT_BAT("dbat[3]", 542, 543);	459	PRINT_BAT("dbat[3]", 542, 543);
461	}	460	}
462		461
463	/** @}	462	/** @}
464	*/	463	*/
465		464

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(root)/branches/sparc/kernel/arch/ppc32/src/mm/tlb.c – Rev 3343 → 3593