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Rev 3343 Rev 3593
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#
 1 
#
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# Copyright (c) 2005 Jakub Jermar
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# Copyright (c) 2005 Jakub Jermar
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# All rights reserved.
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# All rights reserved.
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#
 4 
#
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# Redistribution and use in source and binary forms, with or without
 5 
# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions
 6 
# modification, are permitted provided that the following conditions
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# are met:
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# are met:
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#
 8 
#
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# - Redistributions of source code must retain the above copyright
 9 
# - Redistributions of source code must retain the above copyright
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#   notice, this list of conditions and the following disclaimer.
 10 
#   notice, this list of conditions and the following disclaimer.
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# - Redistributions in binary form must reproduce the above copyright
 11 
# - Redistributions in binary form must reproduce the above copyright
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#   notice, this list of conditions and the following disclaimer in the
 12 
#   notice, this list of conditions and the following disclaimer in the
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#   documentation and/or other materials provided with the distribution.
 13 
#   documentation and/or other materials provided with the distribution.
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# - The name of the author may not be used to endorse or promote products
 14 
# - The name of the author may not be used to endorse or promote products
15 
#   derived from this software without specific prior written permission.
 15 
#   derived from this software without specific prior written permission.
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#
 16 
#
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# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 17 
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 18 
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 19 
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 21 
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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#
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#include <arch/register.h>
 29 
#include <arch/register.h>
30 
#include <arch/mm/page.h>
 30 
#include <arch/mm/page.h>
31 
#include <arch/mm/asid.h>
 31 
#include <arch/mm/asid.h>
32 
#include <mm/asid.h>
 32 
#include <mm/asid.h>
33 
 
 33 
 
34 
#define RR_MASK (0xFFFFFFFF00000002)
 34 
#define RR_MASK (0xFFFFFFFF00000002)
35 
#define RID_SHIFT 8
 35 
#define RID_SHIFT 8
36 
#define PS_SHIFT 2
 36 
#define PS_SHIFT 2
37 
 
 37 
 
38 
#define KERNEL_TRANSLATION_I  0x0010000000000661
 38 
#define KERNEL_TRANSLATION_I  0x0010000000000661
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#define KERNEL_TRANSLATION_D  0x0010000000000661
 39 
#define KERNEL_TRANSLATION_D  0x0010000000000661
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#define KERNEL_TRANSLATION_VIO 0x0010000000000671
 40 
#define KERNEL_TRANSLATION_VIO 0x0010000000000671
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#define KERNEL_TRANSLATION_IO 0x00100FFFFC000671
41 
#define KERNEL_TRANSLATION_IO 0x00100FFFFC000671
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#define VIO_OFFSET            0x0002000000000000
 - 
 
43 
 
 - 
 
44 
#define IO_OFFSET             0x0001000000000000
 42 
#define KERNEL_TRANSLATION_FW 0x00100000F0000671
45 
 
 43 
 
46 
 
 44 
 
47 
 
 45 
 
48 
.section K_TEXT_START, "ax"
 46 
.section K_TEXT_START, "ax"
49 
 
 47 
 
50 
.global kernel_image_start
 48 
.global kernel_image_start
51 
 
 49 
 
52 
stack0:
 50 
stack0:
53 
kernel_image_start:
 51 
kernel_image_start:
54 
	.auto
 52 
	.auto
55 
 
 53 
 
- 
 
 54 
#identifi self(CPU) in OS structures by ID / EID
- 
 
 55 
	mov r9=cr64
- 
 
 56 
	mov r10=1
- 
 
 57 
	movl r12=0xffffffff
- 
 
 58 
	movl r8=cpu_by_id_eid_list
- 
 
 59 
	and r8=r8,r12
- 
 
 60 
	shr r9=r9,16
- 
 
 61 
	add r8=r8,r9
- 
 
 62 
	st1 [r8]=r10
- 
 
 63 
 
- 
 
 64 
 
- 
 
 65 
 
56 
	mov psr.l = r0
 66 
	mov psr.l = r0
57 
	srlz.i
 67 
	srlz.i
58 
	srlz.d
 68 
	srlz.d
59 
 
 69 
 
60 
	# Fill TR.i and TR.d using Region Register #VRN_KERNEL
 70 
	# Fill TR.i and TR.d using Region Register #VRN_KERNEL
61 
 
 71 
 
62 
 
 72 
 
63 
	movl r8 = (VRN_KERNEL << VRN_SHIFT)
 73 
	movl r8 = (VRN_KERNEL << VRN_SHIFT)
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	mov r9 = rr[r8]
 74 
	mov r9 = rr[r8]
65 
 
 75 
 
66 
 
 76 
 
67 
	movl r10 = (RR_MASK)
 77 
	movl r10 = (RR_MASK)
68 
	and r9 = r10, r9
 78 
	and r9 = r10, r9
69 
	movl r10 = ((RID_KERNEL << RID_SHIFT) | (KERNEL_PAGE_WIDTH << PS_SHIFT))
 79 
	movl r10 = ((RID_KERNEL << RID_SHIFT) | (KERNEL_PAGE_WIDTH << PS_SHIFT))
70 
	or  r9 = r10, r9
 80 
	or  r9 = r10, r9
71 
 
 81 
 
72 
 
 82 
 
73 
	mov rr[r8] = r9
 83 
	mov rr[r8] = r9
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 84 
 
75 
 
 85 
 
76 
 
 86 
 
77 
	movl r8 = (VRN_KERNEL << VRN_SHIFT)
 87 
	movl r8 = (VRN_KERNEL << VRN_SHIFT)
78 
	mov cr.ifa = r8
 88 
	mov cr.ifa = r8
79 
 
 89 
 
80
90
81 
	mov r11 = cr.itir ;;
 91 
	mov r11 = cr.itir ;;
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	movl r10 = (KERNEL_PAGE_WIDTH << PS_SHIFT);;
 92 
	movl r10 = (KERNEL_PAGE_WIDTH << PS_SHIFT);;
83 
	or r10 =r10 , r11  ;;
 93 
	or r10 =r10 , r11  ;;
84 
	mov cr.itir = r10;;
 94 
	mov cr.itir = r10;;
85 
 
 95 
 
86
96
87 
	movl r10 = (KERNEL_TRANSLATION_I)
 97 
	movl r10 = (KERNEL_TRANSLATION_I)
88 
	itr.i itr[r0] = r10
 98 
	itr.i itr[r0] = r10
89 
 
 99 
 
90
100
91 
	movl r10 = (KERNEL_TRANSLATION_D)
 101 
	movl r10 = (KERNEL_TRANSLATION_D)
92 
	itr.d dtr[r0] = r10
 102 
	itr.d dtr[r0] = r10
93 
 
 103 
 
94 
 
 104 
 
95 
	movl r7 = 1
 105 
	movl r7 = 1
96 
	movl r8 = (VRN_KERNEL << VRN_SHIFT) | VIO_OFFSET
 106 
	movl r8 = (VRN_KERNEL << VRN_SHIFT) | VIO_OFFSET
97 
	mov cr.ifa = r8
 107 
	mov cr.ifa = r8
98 
	movl r10 = (KERNEL_TRANSLATION_VIO)
 108 
	movl r10 = (KERNEL_TRANSLATION_VIO)
99 
	itr.d dtr[r7] = r10
 109 
	itr.d dtr[r7] = r10
100 
 
 110 
 
101 
 
 111 
 
102 
	mov r11 = cr.itir ;;
 112 
	mov r11 = cr.itir ;;
103 
	movl r10 = ~0xfc;;
 113 
	movl r10 = ~0xfc;;
104 
	and r10 =r10 , r11  ;;
 114 
	and r10 =r10 , r11  ;;
105 
	movl r11 = (IO_PAGE_WIDTH << PS_SHIFT);;
 115 
	movl r11 = (IO_PAGE_WIDTH << PS_SHIFT);;
106 
	or r10 =r10 , r11  ;;
 116 
	or r10 =r10 , r11  ;;
107 
	mov cr.itir = r10;;
 117 
	mov cr.itir = r10;;
108 
 
 118 
 
109 
 
 119 
 
110 
	movl r7 = 2
 120 
	movl r7 = 2
111 
	movl r8 = (VRN_KERNEL << VRN_SHIFT) | IO_OFFSET
 121 
	movl r8 = (VRN_KERNEL << VRN_SHIFT) | IO_OFFSET
112 
	mov cr.ifa = r8
 122 
	mov cr.ifa = r8
113 
	movl r10 = (KERNEL_TRANSLATION_IO)
 123 
	movl r10 = (KERNEL_TRANSLATION_IO)
114 
	itr.d dtr[r7] = r10
 124 
	itr.d dtr[r7] = r10
115 
 
 125 
 
116 
 
 126 
 
- 
 
 127 
#setup mapping for fimware arrea (also SAPIC)
- 
 
 128 
	mov r11 = cr.itir ;;
- 
 
 129 
	movl r10 = ~0xfc;;
- 
 
 130 
	and r10 =r10 , r11  ;;
- 
 
 131 
	movl r11 = (FW_PAGE_WIDTH << PS_SHIFT);;
- 
 
 132 
	or r10 =r10 , r11  ;;
- 
 
 133 
	mov cr.itir = r10;;
- 
 
 134 
 
- 
 
 135 
 
- 
 
 136 
	movl r7 = 3
- 
 
 137 
	movl r8 = (VRN_KERNEL << VRN_SHIFT) | FW_OFFSET
- 
 
 138 
	mov cr.ifa = r8
- 
 
 139 
	movl r10 = (KERNEL_TRANSLATION_FW)
- 
 
 140 
	itr.d dtr[r7] = r10
- 
 
 141 
 
- 
 
 142 
 
- 
 
 143 
 
117 
 
 144 
 
118 
 
 145 
 
119 
	# initialize PSR
 146 
	# initialize PSR
120 
	movl r10 = (PSR_DT_MASK | PSR_RT_MASK | PSR_IT_MASK | PSR_IC_MASK)  /* Enable paging */
 147 
	movl r10 = (PSR_DT_MASK | PSR_RT_MASK | PSR_IT_MASK | PSR_IC_MASK)  /* Enable paging */
121 
	mov r9 = psr
 148 
	mov r9 = psr
122 
	or r10 = r10, r9
 149 
	or r10 = r10, r9
123 
	mov cr.ipsr = r10
 150 
	mov cr.ipsr = r10
124 
	mov cr.ifs = r0
 151 
	mov cr.ifs = r0
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	movl r8 = paging_start
 152 
	movl r8 = paging_start
126 
	mov cr.iip = r8
 153 
	mov cr.iip = r8
127 
	srlz.d
 154 
	srlz.d
128 
	srlz.i
 155 
	srlz.i
129 
 
 156 
 
130 
	.explicit
 157 
	.explicit
131 
	/*
 158 
	/*
132 
	 * Return From Interupt is the only the way to fill upper half word of PSR.
 159 
	 * Return From Interupt is the only the way to fill upper half word of PSR.
133 
	 */
 160 
	 */
134 
	rfi;;
 161 
	rfi;;
135 
 
 162 
 
136 
.global paging_start
 163 
.global paging_start
137 
paging_start:
 164 
paging_start:
138 
 
 165 
 
139 
	/*
 166 
	/*
140 
	 * Now we are paging.
 167 
	 * Now we are paging.
141 
	 */
 168 
	 */
142 
 
 169 
 
143 
	# switch to register bank 1
 170 
	# switch to register bank 1
144 
	bsw.1
 171 
	bsw.1
- 
 
 172 
 
- 
 
 173 
#Am'I BSP or AP
- 
 
 174 
	movl r20=bsp_started;;
- 
 
 175 
	ld8 r20=[r20];;
- 
 
 176 
	cmp.eq p3,p2=r20,r0;;
- 
 
 177 
 
145
178
146 
	# initialize register stack
 179 
	# initialize register stack
147 
	mov ar.rsc = r0
 180 
	mov ar.rsc = r0
148 
	movl r8 = (VRN_KERNEL << VRN_SHIFT) ;;
 181 
	movl r8 = (VRN_KERNEL << VRN_SHIFT) ;;
149 
	mov ar.bspstore = r8
 182 
	mov ar.bspstore = r8
150 
	loadrs
 183 
	loadrs
151 
 
 184 
 
152 
	# initialize memory stack to some sane value
 185 
	# initialize memory stack to some sane value
153 
	movl r12 = stack0 ;;
 186 
	movl r12 = stack0 ;;
154
187
155 
	add r12 = -16, r12	/* allocate a scratch area on the stack */
 188 
	add r12 = -16, r12	/* allocate a scratch area on the stack */
156 
 
 189 
 
157 
	# initialize gp (Global Pointer) register
 190 
	# initialize gp (Global Pointer) register
158 
	movl r20 = (VRN_KERNEL << VRN_SHIFT);;
 191 
	movl r20 = (VRN_KERNEL << VRN_SHIFT);;
159 
	or r20 = r20,r1;;
 192 
	or r20 = r20,r1;;
160 
	movl r1 = _hardcoded_load_address
 193 
	movl r1 = _hardcoded_load_address
161
194
162 
	/*
 195 
	/*
163 
	 * Initialize hardcoded_* variables.
 196 
	 * Initialize hardcoded_* variables. Do only BSP
164 
	 */
 197 
	 */
165 
	movl r14 = _hardcoded_ktext_size
 198 
(p3)	movl r14 = _hardcoded_ktext_size
166 
	movl r15 = _hardcoded_kdata_size
 199 
(p3)	movl r15 = _hardcoded_kdata_size
167 
	movl r16 = _hardcoded_load_address ;;
 200 
(p3)	movl r16 = _hardcoded_load_address ;;
168 
	addl r17 = @gprel(hardcoded_ktext_size), gp
 201 
(p3)	addl r17 = @gprel(hardcoded_ktext_size), gp
169 
	addl r18 = @gprel(hardcoded_kdata_size), gp
 202 
(p3)	addl r18 = @gprel(hardcoded_kdata_size), gp
170 
	addl r19 = @gprel(hardcoded_load_address), gp
 203 
(p3)	addl r19 = @gprel(hardcoded_load_address), gp
171 
	addl r21 = @gprel(bootinfo), gp
 204 
(p3)	addl r21 = @gprel(bootinfo), gp
172 
	;;
 205 
	;;
173 
	st8 [r17] = r14
 206 
(p3)	st8 [r17] = r14
174 
	st8 [r18] = r15
 207 
(p3)	st8 [r18] = r15
175 
	st8 [r19] = r16
 208 
(p3)	st8 [r19] = r16
176 
	st8 [r21] = r20
 209 
(p3)	st8 [r21] = r20
177 
 
 210 
 
178 
	ssm (1 << 19) ;; /* Disable f32 - f127 */
 211 
	ssm (1 << 19) ;; /* Disable f32 - f127 */
179 
	srlz.i
 212 
	srlz.i
180 
	srlz.d ;;
 213 
	srlz.d ;;
181 
 
 214 
 
- 
 
 215 
(p2)	movl r18 = main_ap ;;
- 
 
 216 
(p2)   	mov b1 = r18 ;;
- 
 
 217 
(p2)	br.call.sptk.many b0 = b1
- 
 
 218 
 
- 
 
 219 
#Mark that BSP is on
- 
 
 220 
	mov r20=1;;
- 
 
 221 
	movl r21=bsp_started;;
- 
 
 222 
	st8 [r21]=r20;;
- 
 
 223 
 
- 
 
 224 
 
182 
	br.call.sptk.many b0 = arch_pre_main
 225 
	br.call.sptk.many b0 = arch_pre_main
183 
 
 226 
 
184 
	movl r18 = main_bsp ;;
 227 
	movl r18 = main_bsp ;;
185 
	mov b1 = r18 ;;
 228 
	mov b1 = r18 ;;
186 
	br.call.sptk.many b0 = b1
 229 
	br.call.sptk.many b0 = b1
187 
 
 230 
 
188 
 
 231 
 
189 
0:
 232 
0:
190 
	br 0b
 233 
	br 0b
- 
 
 234 
.align 4096
- 
 
 235 
 
- 
 
 236 
kernel_image_ap_start:
- 
 
 237 
	.auto
- 
 
 238 
#identifi self(CPU) in OS structures by ID / EID
- 
 
 239 
	mov r9=cr64
- 
 
 240 
	mov r10=1
- 
 
 241 
	movl r12=0xffffffff
- 
 
 242 
	movl r8=cpu_by_id_eid_list
- 
 
 243 
	and r8=r8,r12
- 
 
 244 
	shr r9=r9,16
- 
 
 245 
	add r8=r8,r9
- 
 
 246 
	st1 [r8]=r10
- 
 
 247
- 
 
 248 
#wait for wakeup sychro signal (#3 in cpu_by_id_eid_list)
- 
 
 249 
kernel_image_ap_start_loop:
- 
 
 250 
	movl r11=kernel_image_ap_start_loop
- 
 
 251 
	and r11=r11,r12
- 
 
 252 
   	mov b1 = r11
- 
 
 253 
 
- 
 
 254 
	ld1 r20=[r8];;
- 
 
 255 
	movl r21=3;;
- 
 
 256 
	cmp.eq p2,p3=r20,r21;;
- 
 
 257 
(p3)br.call.sptk.many b0 = b1
- 
 
 258 
 
- 
 
 259 
	movl r11=kernel_image_start
- 
 
 260 
	and r11=r11,r12
- 
 
 261 
    mov b1 = r11
- 
 
 262 
	br.call.sptk.many b0 = b1
- 
 
 263 
 
- 
 
 264 
 
- 
 
 265 
.align 16
- 
 
 266 
.global bsp_started
- 
 
 267 
bsp_started:
- 
 
 268 
.space 8
- 
 
 269 
 
- 
 
 270 
 
- 
 
 271 
.align 4096
- 
 
 272 
.global cpu_by_id_eid_list
- 
 
 273 
cpu_by_id_eid_list:
- 
 
 274 
.space 65536
- 
 
 275 
 
- 
 
 276 
 
191 
 
 277