WebSVN – HelenOS – Diff – /branches/sparc/kernel/arch/ia32/src/cpu/cpu.c


/*
 * Copyright (c) 2001-2004 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup ia32
 * @{
 */
/** @file
 */
 
#include <arch/cpu.h>
#include <arch/cpuid.h>
#include <arch/pm.h>
 
#include <arch.h>
#include <arch/types.h>
#include <print.h>
#include <fpu_context.h>
 
#include <arch/smp/apic.h>
#include <arch/syscall.h>
 
/*
 * Identification of CPUs.
 * Contains only non-MP-Specification specific SMP code.
 */
#define AMD_CPUID_EBX   0x68747541
#define AMD_CPUID_ECX   0x444d4163
#define AMD_CPUID_EDX   0x69746e65
 
#define INTEL_CPUID_EBX 0x756e6547
#define INTEL_CPUID_ECX 0x6c65746e
#define INTEL_CPUID_EDX 0x49656e69
 
 
enum vendor {
    VendorUnknown=0,
    VendorAMD,
    VendorIntel
};
 
static char *vendor_str[] = {
    "Unknown Vendor",
    "AMD",
    "Intel"
};
 
void fpu_disable(void)
{
    asm volatile (
        "mov %%cr0,%%eax;"
        "or $8,%%eax;"
        "mov %%eax,%%cr0;"
        :
        :
        : "%eax"
    );
}
 
void fpu_enable(void)
{
    asm volatile (
        "mov %%cr0,%%eax;"
        "and $0xffFFffF7,%%eax;"
        "mov %%eax,%%cr0;"
        :
        :
        : "%eax"
    ); 
}
 
void cpu_arch_init(void)
{
    cpuid_feature_info fi;
    cpuid_extended_feature_info efi;
    cpu_info_t info;
    uint32_t help = 0;
   
    CPU->arch.tss = tss_p;
    CPU->arch.tss->iomap_base = &CPU->arch.tss->iomap[0] - ((uint8_t *) CPU->arch.tss);
 
    CPU->fpu_owner = NULL;
 
    cpuid(1, &info);
 
    fi.word = info.cpuid_edx;
    efi.word = info.cpuid_ecx;
   
    if (fi.bits.fxsr)
        fpu_fxsr();
    else
        fpu_fsr(); 
   
    if (fi.bits.sse) {
        asm volatile (
            "mov %%cr4,%0\n"
            "or %1,%0\n"
            "mov %0,%%cr4\n"
            : "+r" (help)
            : "i" (CR4_OSFXSR_MASK|(1<<10))
        );
    }
   
    /* Setup fast SYSENTER/SYSEXIT syscalls */
    syscall_setup_cpu();
}
 
void cpu_identify(void)
{
    cpu_info_t info;
 
    CPU->arch.vendor = VendorUnknown;
    if (has_cpuid()) {
        cpuid(0, &info);
 
        /*
         * Check for AMD processor.
         */
        if ((info.cpuid_ebx == AMD_CPUID_EBX)
            && (info.cpuid_ecx == AMD_CPUID_ECX)
            && (info.cpuid_edx == AMD_CPUID_EDX))
            CPU->arch.vendor = VendorAMD;
       
 
        /*
         * Check for Intel processor.
         */    
        if ((info.cpuid_ebx == INTEL_CPUID_EBX)
            && (info.cpuid_ecx == INTEL_CPUID_ECX)
            && (info.cpuid_edx == INTEL_CPUID_EDX))
            CPU->arch.vendor = VendorIntel;
       
 
        cpuid(1, &info);
        CPU->arch.family = (info.cpuid_eax >> 8) & 0x0f;
        CPU->arch.model = (info.cpuid_eax >> 4) & 0x0f;
        CPU->arch.stepping = (info.cpuid_eax >> 0) & 0x0f;                     
    }
}
 
void cpu_print_report(cpu_t* cpu)
{
    printf("cpu%u: (%s family=%u model=%u stepping=%u) %" PRIu16 " MHz\n",
        cpu->id, vendor_str[cpu->arch.vendor], cpu->arch.family,
        cpu->arch.model, cpu->arch.stepping, cpu->frequency_mhz);
}
 
/** @}
 */
 

Rev 3492	Rev 3742
1	/*	1	/*
2	* Copyright (c) 2001-2004 Jakub Jermar	2	* Copyright (c) 2001-2004 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	/** @addtogroup ia32	29	/** @addtogroup ia32
30	* @{	30	* @{
31	*/	31	*/
32	/** @file	32	/** @file
33	*/	33	*/
34		34
35	#include <arch/cpu.h>	35	#include <arch/cpu.h>
36	#include <arch/cpuid.h>	36	#include <arch/cpuid.h>
37	#include <arch/pm.h>	37	#include <arch/pm.h>
38		38
39	#include <arch.h>	39	#include <arch.h>
40	#include <arch/types.h>	40	#include <arch/types.h>
41	#include <print.h>	41	#include <print.h>
42	#include <fpu_context.h>	42	#include <fpu_context.h>
43		43
44	#include <arch/smp/apic.h>	44	#include <arch/smp/apic.h>
45	#include <arch/syscall.h>	45	#include <arch/syscall.h>
46		46
47	/*	47	/*
48	* Identification of CPUs.	48	* Identification of CPUs.
49	* Contains only non-MP-Specification specific SMP code.	49	* Contains only non-MP-Specification specific SMP code.
50	*/	50	*/
51	#define AMD_CPUID_EBX 0x68747541	51	#define AMD_CPUID_EBX 0x68747541
52	#define AMD_CPUID_ECX 0x444d4163	52	#define AMD_CPUID_ECX 0x444d4163
53	#define AMD_CPUID_EDX 0x69746e65	53	#define AMD_CPUID_EDX 0x69746e65
54		54
55	#define INTEL_CPUID_EBX 0x756e6547	55	#define INTEL_CPUID_EBX 0x756e6547
56	#define INTEL_CPUID_ECX 0x6c65746e	56	#define INTEL_CPUID_ECX 0x6c65746e
57	#define INTEL_CPUID_EDX 0x49656e69	57	#define INTEL_CPUID_EDX 0x49656e69
58		58
59		59
60	enum vendor {	60	enum vendor {
61	VendorUnknown=0,	61	VendorUnknown=0,
62	VendorAMD,	62	VendorAMD,
63	VendorIntel	63	VendorIntel
64	};	64	};
65		65
66	static char *vendor_str[] = {	66	static char *vendor_str[] = {
67	"Unknown Vendor",	67	"Unknown Vendor",
68	"AuthenticAMD",	68	"AMD",
69	"GenuineIntel"	69	"Intel"
70	};	70	};
71		71
72	void fpu_disable(void)	72	void fpu_disable(void)
73	{	73	{
74	asm volatile (	74	asm volatile (
75	"mov %%cr0,%%eax;"	75	"mov %%cr0,%%eax;"
76	"or $8,%%eax;"	76	"or $8,%%eax;"
77	"mov %%eax,%%cr0;"	77	"mov %%eax,%%cr0;"
78	:	78	:
79	:	79	:
80	:"%eax"	80	: "%eax"
81	);	81	);
82	}	82	}
83		83
84	void fpu_enable(void)	84	void fpu_enable(void)
85	{	85	{
86	asm volatile (	86	asm volatile (
87	"mov %%cr0,%%eax;"	87	"mov %%cr0,%%eax;"
88	"and $0xffFFffF7,%%eax;"	88	"and $0xffFFffF7,%%eax;"
89	"mov %%eax,%%cr0;"	89	"mov %%eax,%%cr0;"
90	:	90	:
91	:	91	:
92	:"%eax"	92	: "%eax"
93	);	93	);
94	}	94	}
95		95
96	void cpu_arch_init(void)	96	void cpu_arch_init(void)
97	{	97	{
98	cpuid_feature_info fi;	98	cpuid_feature_info fi;
99	cpuid_extended_feature_info efi;	99	cpuid_extended_feature_info efi;
100	cpu_info_t info;	100	cpu_info_t info;
101	uint32_t help = 0;	101	uint32_t help = 0;
102		102
103	CPU->arch.tss = tss_p;	103	CPU->arch.tss = tss_p;
104	CPU->arch.tss->iomap_base = &CPU->arch.tss->iomap[0] - ((uint8_t *) CPU->arch.tss);	104	CPU->arch.tss->iomap_base = &CPU->arch.tss->iomap[0] - ((uint8_t *) CPU->arch.tss);
105		105
106	CPU->fpu_owner = NULL;	106	CPU->fpu_owner = NULL;
107		107
108	cpuid(1, &info);	108	cpuid(1, &info);
109		109
110	fi.word = info.cpuid_edx;	110	fi.word = info.cpuid_edx;
111	efi.word = info.cpuid_ecx;	111	efi.word = info.cpuid_ecx;
112		112
113	if (fi.bits.fxsr)	113	if (fi.bits.fxsr)
114	fpu_fxsr();	114	fpu_fxsr();
115	else	115	else
116	fpu_fsr();	116	fpu_fsr();
117		117
118	if (fi.bits.sse) {	118	if (fi.bits.sse) {
119	asm volatile (	119	asm volatile (
120	"mov %%cr4,%0\n"	120	"mov %%cr4,%0\n"
121	"or %1,%0\n"	121	"or %1,%0\n"
122	"mov %0,%%cr4\n"	122	"mov %0,%%cr4\n"
123	: "+r" (help)	123	: "+r" (help)
124	: "i" (CR4_OSFXSR_MASK\|(1<<10))	124	: "i" (CR4_OSFXSR_MASK\|(1<<10))
125	);	125	);
126	}	126	}
127		127
128	/* Setup fast SYSENTER/SYSEXIT syscalls */	128	/* Setup fast SYSENTER/SYSEXIT syscalls */
129	syscall_setup_cpu();	129	syscall_setup_cpu();
130	}	130	}
131		131
132	void cpu_identify(void)	132	void cpu_identify(void)
133	{	133	{
134	cpu_info_t info;	134	cpu_info_t info;
135		135
136	CPU->arch.vendor = VendorUnknown;	136	CPU->arch.vendor = VendorUnknown;
137	if (has_cpuid()) {	137	if (has_cpuid()) {
138	cpuid(0, &info);	138	cpuid(0, &info);
139		139
140	/*	140	/*
141	* Check for AMD processor.	141	* Check for AMD processor.
142	*/	142	*/
-		143	if ((info.cpuid_ebx == AMD_CPUID_EBX)
143	if (info.cpuid_ebx==AMD_CPUID_EBX && info.cpuid_ecx==AMD_CPUID_ECX && info.cpuid_edx==AMD_CPUID_EDX) {	144	&& (info.cpuid_ecx == AMD_CPUID_ECX)
-		145	&& (info.cpuid_edx == AMD_CPUID_EDX))
144	CPU->arch.vendor = VendorAMD;	146	CPU->arch.vendor = VendorAMD;
145	}	147
146		-
147	/*	148	/*
148	* Check for Intel processor.	149	* Check for Intel processor.
149	*/	150	*/
-		151	if ((info.cpuid_ebx == INTEL_CPUID_EBX)
150	if (info.cpuid_ebx==INTEL_CPUID_EBX && info.cpuid_ecx==INTEL_CPUID_ECX && info.cpuid_edx==INTEL_CPUID_EDX) {	152	&& (info.cpuid_ecx == INTEL_CPUID_ECX)
-		153	&& (info.cpuid_edx == INTEL_CPUID_EDX))
151	CPU->arch.vendor = VendorIntel;	154	CPU->arch.vendor = VendorIntel;
152	}	155
153		-
154	cpuid(1, &info);	156	cpuid(1, &info);
155	CPU->arch.family = (info.cpuid_eax>>8)&0xf;	157	CPU->arch.family = (info.cpuid_eax >> 8) & 0x0f;
156	CPU->arch.model = (info.cpuid_eax>>4)&0xf;	158	CPU->arch.model = (info.cpuid_eax >> 4) & 0x0f;
157	CPU->arch.stepping = (info.cpuid_eax>>0)&0xf;	159	CPU->arch.stepping = (info.cpuid_eax >> 0) & 0x0f;
158	}	160	}
159	}	161	}
160		162
161	void cpu_print_report(cpu_t* m)	163	void cpu_print_report(cpu_t* cpu)
162	{	164	{
163	printf("cpu%d: (%s family=%d model=%d stepping=%d) %dMHz\n",	165	printf("cpu%u: (%s family=%u model=%u stepping=%u) %" PRIu16 " MHz\n",
164	m->id, vendor_str[m->arch.vendor], m->arch.family, m->arch.model, m->arch.stepping,	166	cpu->id, vendor_str[cpu->arch.vendor], cpu->arch.family,
165	m->frequency_mhz);	167	cpu->arch.model, cpu->arch.stepping, cpu->frequency_mhz);
166	}	168	}
167		169
168	/** @}	170	/** @}
169	*/	171	*/
170		172

Subversion Repositories HelenOS

(root)/branches/sparc/kernel/arch/ia32/src/cpu/cpu.c – Rev 3492 → 3742