WebSVN – HelenOS – Diff – /branches/rcu/kernel/arch/sparc64/src/mm/tsb.c



    count_t cnt;
   
    ASSERT(as->arch.itsb && as->arch.dtsb);
   
    i0 = (page >> MMU_PAGE_WIDTH) & TSB_INDEX_MASK;
    ASSERT(i0 < ITSB_ENTRY_COUNT && i0 < DTSB_ENTRY_COUNT);
 
    if (pages == (count_t) -1 || (pages * 2) > ITSB_ENTRY_COUNT)
        cnt = ITSB_ENTRY_COUNT;
    else
        cnt = pages * 2;
   

void itsb_pte_copy(pte_t *t, index_t index)
{
    as_t *as;
    tsb_entry_t *tsb;
    index_t entry;
 
    ASSERT(index <= 1);
   
    as = t->as;
    entry = ((t->page >> MMU_PAGE_WIDTH) + index) & TSB_INDEX_MASK;
    ASSERT(entry < ITSB_ENTRY_COUNT);
    tsb = &as->arch.itsb[entry];
 
    /*
     * We use write barriers to make sure that the TSB load
     * won't use inconsistent data or that the fault will

                     * set to 0) */
 
    write_barrier();
 
    tsb->tag.context = as->asid;
    /* the shift is bigger than PAGE_WIDTH, do not bother with index  */
    tsb->tag.va_tag = t->page >> VA_TAG_PAGE_SHIFT;
    tsb->data.value = 0;
    tsb->data.size = PAGESIZE_8K;
    tsb->data.pfn = (t->frame >> MMU_FRAME_WIDTH) + index;
    tsb->data.cp = t->c;
    tsb->data.p = t->k;     /* p as privileged */

{
    as_t *as;
    tsb_entry_t *tsb;
    index_t entry;
   
    ASSERT(index <= 1);
 
    as = t->as;
    entry = ((t->page >> MMU_PAGE_WIDTH) + index) & TSB_INDEX_MASK;
    ASSERT(entry < DTSB_ENTRY_COUNT);
    tsb = &as->arch.dtsb[entry];
 
    /*
     * We use write barriers to make sure that the TSB load
     * won't use inconsistent data or that the fault will

                     * set to 0) */
 
    write_barrier();
 
    tsb->tag.context = as->asid;
    /* the shift is bigger than PAGE_WIDTH, do not bother with index */
    tsb->tag.va_tag = t->page >> VA_TAG_PAGE_SHIFT;
    tsb->data.value = 0;
    tsb->data.size = PAGESIZE_8K;
    tsb->data.pfn = (t->frame >> MMU_FRAME_WIDTH) + index;
    tsb->data.cp = t->c;
#ifdef CONFIG_VIRT_IDX_DCACHE

Rev 2292	Rev 2307
Line 59...	Line 59...
59	count_t cnt;	59	count_t cnt;
60		60
61	ASSERT(as->arch.itsb && as->arch.dtsb);	61	ASSERT(as->arch.itsb && as->arch.dtsb);
62		62
63	i0 = (page >> MMU_PAGE_WIDTH) & TSB_INDEX_MASK;	63	i0 = (page >> MMU_PAGE_WIDTH) & TSB_INDEX_MASK;
-		64	ASSERT(i0 < ITSB_ENTRY_COUNT && i0 < DTSB_ENTRY_COUNT);
-		65
64	if (pages == (count_t) -1 \|\| (pages * 2) > ITSB_ENTRY_COUNT)	66	if (pages == (count_t) -1 \|\| (pages * 2) > ITSB_ENTRY_COUNT)
65	cnt = ITSB_ENTRY_COUNT;	67	cnt = ITSB_ENTRY_COUNT;
66	else	68	else
67	cnt = pages * 2;	69	cnt = pages * 2;
68		70
Line 82...	Line 84...
82	void itsb_pte_copy(pte_t *t, index_t index)	84	void itsb_pte_copy(pte_t *t, index_t index)
83	{	85	{
84	as_t *as;	86	as_t *as;
85	tsb_entry_t *tsb;	87	tsb_entry_t *tsb;
86	index_t entry;	88	index_t entry;
-		89
-		90	ASSERT(index <= 1);
87		91
88	as = t->as;	92	as = t->as;
89	entry = ((t->page >> MMU_PAGE_WIDTH) + index) & TSB_INDEX_MASK;	93	entry = ((t->page >> MMU_PAGE_WIDTH) + index) & TSB_INDEX_MASK;
-		94	ASSERT(entry < ITSB_ENTRY_COUNT);
90	tsb = &as->arch.itsb[entry];	95	tsb = &as->arch.itsb[entry];
91		96
92	/*	97	/*
93	* We use write barriers to make sure that the TSB load	98	* We use write barriers to make sure that the TSB load
94	* won't use inconsistent data or that the fault will	99	* won't use inconsistent data or that the fault will
Line 100...	Line 105...
100	* set to 0) */	105	* set to 0) */
101		106
102	write_barrier();	107	write_barrier();
103		108
104	tsb->tag.context = as->asid;	109	tsb->tag.context = as->asid;
105	tsb->tag.va_tag = (t->page + (index << MMU_PAGE_WIDTH)) >>	110	/* the shift is bigger than PAGE_WIDTH, do not bother with index */
106	VA_TAG_PAGE_SHIFT;	111	tsb->tag.va_tag = t->page >> VA_TAG_PAGE_SHIFT;
107	tsb->data.value = 0;	112	tsb->data.value = 0;
108	tsb->data.size = PAGESIZE_8K;	113	tsb->data.size = PAGESIZE_8K;
109	tsb->data.pfn = (t->frame >> MMU_FRAME_WIDTH) + index;	114	tsb->data.pfn = (t->frame >> MMU_FRAME_WIDTH) + index;
110	tsb->data.cp = t->c;	115	tsb->data.cp = t->c;
111	tsb->data.p = t->k; /* p as privileged */	116	tsb->data.p = t->k; /* p as privileged */
Line 126...	Line 131...
126	{	131	{
127	as_t *as;	132	as_t *as;
128	tsb_entry_t *tsb;	133	tsb_entry_t *tsb;
129	index_t entry;	134	index_t entry;
130		135
-		136	ASSERT(index <= 1);
-		137
131	as = t->as;	138	as = t->as;
132	entry = ((t->page >> MMU_PAGE_WIDTH) + index) & TSB_INDEX_MASK;	139	entry = ((t->page >> MMU_PAGE_WIDTH) + index) & TSB_INDEX_MASK;
-		140	ASSERT(entry < DTSB_ENTRY_COUNT);
133	tsb = &as->arch.dtsb[entry];	141	tsb = &as->arch.dtsb[entry];
134		142
135	/*	143	/*
136	* We use write barriers to make sure that the TSB load	144	* We use write barriers to make sure that the TSB load
137	* won't use inconsistent data or that the fault will	145	* won't use inconsistent data or that the fault will
Line 143...	Line 151...
143	* set to 0) */	151	* set to 0) */
144		152
145	write_barrier();	153	write_barrier();
146		154
147	tsb->tag.context = as->asid;	155	tsb->tag.context = as->asid;
148	tsb->tag.va_tag = (t->page + (index << MMU_PAGE_WIDTH)) >>	156	/* the shift is bigger than PAGE_WIDTH, do not bother with index */
149	VA_TAG_PAGE_SHIFT;	157	tsb->tag.va_tag = t->page >> VA_TAG_PAGE_SHIFT;
150	tsb->data.value = 0;	158	tsb->data.value = 0;
151	tsb->data.size = PAGESIZE_8K;	159	tsb->data.size = PAGESIZE_8K;
152	tsb->data.pfn = (t->frame >> MMU_FRAME_WIDTH) + index;	160	tsb->data.pfn = (t->frame >> MMU_FRAME_WIDTH) + index;
153	tsb->data.cp = t->c;	161	tsb->data.cp = t->c;
154	#ifdef CONFIG_VIRT_IDX_DCACHE	162	#ifdef CONFIG_VIRT_IDX_DCACHE

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(root)/branches/rcu/kernel/arch/sparc64/src/mm/tsb.c – Rev 2292 → 2307