WebSVN – HelenOS – Diff – /branches/rcu/kernel/arch/sparc64/src/mm/tlb.c


/*
 * Copyright (c) 2005 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup sparc64mm  
 * @{
 */
/** @file
 */
 
#include <arch/mm/tlb.h>
#include <mm/tlb.h>
#include <mm/as.h>
#include <mm/asid.h>
#include <arch/mm/frame.h>
#include <arch/mm/page.h>
#include <arch/mm/mmu.h>
#include <arch/interrupt.h>
#include <interrupt.h>
#include <arch.h>
#include <print.h>
#include <arch/types.h>
#include <config.h>
#include <arch/trap/trap.h>
#include <arch/trap/exception.h>
#include <panic.h>
#include <arch/asm.h>
 
#ifdef CONFIG_TSB
#include <arch/mm/tsb.h>
#endif
 
static void dtlb_pte_copy(pte_t *t, index_t index, bool ro);
static void itlb_pte_copy(pte_t *t, index_t index);
static void do_fast_instruction_access_mmu_miss_fault(istate_t *istate,
    const char *str);
static void do_fast_data_access_mmu_miss_fault(istate_t *istate,
    tlb_tag_access_reg_t tag, const char *str);
static void do_fast_data_access_protection_fault(istate_t *istate,
    tlb_tag_access_reg_t tag, const char *str);
 
char *context_encoding[] = {
    "Primary",
    "Secondary",
    "Nucleus",
    "Reserved"
};
 
void tlb_arch_init(void)
{
    /*
     * Invalidate all non-locked DTLB and ITLB entries.
     */
    tlb_invalidate_all();
 
    /*
     * Clear both SFSRs.
     */
    dtlb_sfsr_write(0);
    itlb_sfsr_write(0);
}
 
/** Insert privileged mapping into DMMU TLB.
 *
 * @param page Virtual page address.
 * @param frame Physical frame address.
 * @param pagesize Page size.
 * @param locked True for permanent mappings, false otherwise.
 * @param cacheable True if the mapping is cacheable, false otherwise.
 */
void dtlb_insert_mapping(uintptr_t page, uintptr_t frame, int pagesize,
    bool locked, bool cacheable)
{
    tlb_tag_access_reg_t tag;
    tlb_data_t data;
    page_address_t pg;
    frame_address_t fr;
 
    pg.address = page;
    fr.address = frame;
 
    tag.value = ASID_KERNEL;
    tag.vpn = pg.vpn;
 
    dtlb_tag_access_write(tag.value);
 
    data.value = 0;
    data.v = true;
    data.size = pagesize;
    data.pfn = fr.pfn;
    data.l = locked;
    data.cp = cacheable;
#ifdef CONFIG_VIRT_IDX_DCACHE
    data.cv = cacheable;
#endif /* CONFIG_VIRT_IDX_DCACHE */
    data.p = true;
    data.w = true;
    data.g = false;
 
    dtlb_data_in_write(data.value);
}
 
/** Copy PTE to TLB.
 *
 * @param t     Page Table Entry to be copied.
 * @param index Zero if lower 8K-subpage, one if higher 8K-subpage.
 * @param ro    If true, the entry will be created read-only, regardless of its
 *      w field.
 */
void dtlb_pte_copy(pte_t *t, index_t index, bool ro)
{
    tlb_tag_access_reg_t tag;
    tlb_data_t data;
    page_address_t pg;
    frame_address_t fr;
 
    pg.address = t->page + (index << MMU_PAGE_WIDTH);
    fr.address = t->frame + (index << MMU_PAGE_WIDTH);
 
    tag.value = 0;
    tag.context = t->as->asid;
    tag.vpn = pg.vpn;
 
    dtlb_tag_access_write(tag.value);
 
    data.value = 0;
    data.v = true;
    data.size = PAGESIZE_8K;
    data.pfn = fr.pfn;
    data.l = false;
    data.cp = t->c;
#ifdef CONFIG_VIRT_IDX_DCACHE
    data.cv = t->c;
#endif /* CONFIG_VIRT_IDX_DCACHE */
    data.p = t->k;      /* p like privileged */
    data.w = ro ? false : t->w;
    data.g = t->g;
 
    dtlb_data_in_write(data.value);
}
 
/** Copy PTE to ITLB.
 *
 * @param t     Page Table Entry to be copied.
 * @param index Zero if lower 8K-subpage, one if higher 8K-subpage.
 */
void itlb_pte_copy(pte_t *t, index_t index)
{
    tlb_tag_access_reg_t tag;
    tlb_data_t data;
    page_address_t pg;
    frame_address_t fr;
 
    pg.address = t->page + (index << MMU_PAGE_WIDTH);
    fr.address = t->frame + (index << MMU_PAGE_WIDTH);
 
    tag.value = 0;
    tag.context = t->as->asid;
    tag.vpn = pg.vpn;
   
    itlb_tag_access_write(tag.value);
   
    data.value = 0;
    data.v = true;
    data.size = PAGESIZE_8K;
    data.pfn = fr.pfn;
    data.l = false;
    data.cp = t->c;
    data.p = t->k;      /* p like privileged */
    data.w = false;
    data.g = t->g;
   
    itlb_data_in_write(data.value);
}
 
/** ITLB miss handler. */
void fast_instruction_access_mmu_miss(unative_t unused, istate_t *istate)
{
    uintptr_t va = ALIGN_DOWN(istate->tpc, PAGE_SIZE);
    index_t index = (istate->tpc >> MMU_PAGE_WIDTH) % MMU_PAGES_PER_PAGE;
    pte_t *t;
 
    page_table_lock(AS, true);
    t = page_mapping_find(AS, va);
    if (t && PTE_EXECUTABLE(t)) {
        /*
         * The mapping was found in the software page hash table.
         * Insert it into ITLB.
         */
        t->a = true;
        itlb_pte_copy(t, index);
#ifdef CONFIG_TSB
        itsb_pte_copy(t, index);
#endif
        page_table_unlock(AS, true);
    } else {
        /*
         * Forward the page fault to the address space page fault
         * handler.
         */    
        page_table_unlock(AS, true);
        if (as_page_fault(va, PF_ACCESS_EXEC, istate) == AS_PF_FAULT) {
            do_fast_instruction_access_mmu_miss_fault(istate,
                __FUNCTION__);
        }
    }
}
 
/** DTLB miss handler.
 *
 * Note that some faults (e.g. kernel faults) were already resolved by the
 * low-level, assembly language part of the fast_data_access_mmu_miss handler.
 *
 * @param tag Content of the TLB Tag Access register as it existed when the
 *    trap happened. This is to prevent confusion created by clobbered
 *    Tag Access register during a nested DTLB miss.
 * @param istate Interrupted state saved on the stack.
 */
void fast_data_access_mmu_miss(tlb_tag_access_reg_t tag, istate_t *istate)
{
 
    uintptr_t va;
    index_t index;
    pte_t *t;
 
 
    va = ALIGN_DOWN((uint64_t) tag.vpn << MMU_PAGE_WIDTH, PAGE_SIZE);
    index = tag.vpn % MMU_PAGES_PER_PAGE;
 
    if (tag.context == ASID_KERNEL) {
        if (!tag.vpn) {
            /* NULL access in kernel */
            do_fast_data_access_mmu_miss_fault(istate, tag,
                __FUNCTION__);
        }
        do_fast_data_access_mmu_miss_fault(istate, tag, "Unexpected "
            "kernel page fault.");
    }
 
    page_table_lock(AS, true);
    t = page_mapping_find(AS, va);
    if (t) {
        /*
         * The mapping was found in the software page hash table.
         * Insert it into DTLB.
         */
        t->a = true;
        dtlb_pte_copy(t, index, true);
#ifdef CONFIG_TSB
        dtsb_pte_copy(t, index, true);
#endif
        page_table_unlock(AS, true);
    } else {
        /*
         * Forward the page fault to the address space page fault
         * handler.
         */    
        page_table_unlock(AS, true);
        if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) {
            do_fast_data_access_mmu_miss_fault(istate, tag,
                __FUNCTION__);
        }
    }
}
 
/** DTLB protection fault handler.
 *
 * @param tag Content of the TLB Tag Access register as it existed when the
 *    trap happened. This is to prevent confusion created by clobbered
 *    Tag Access register during a nested DTLB miss.
 * @param istate Interrupted state saved on the stack.
 */
void fast_data_access_protection(tlb_tag_access_reg_t tag, istate_t *istate)
{
 
    uintptr_t va;
    index_t index;
    pte_t *t;
 
 
    va = ALIGN_DOWN((uint64_t) tag.vpn << MMU_PAGE_WIDTH, PAGE_SIZE);
    index = tag.vpn % MMU_PAGES_PER_PAGE;   /* 16K-page emulation */
 
    page_table_lock(AS, true);
    t = page_mapping_find(AS, va);
    if (t && PTE_WRITABLE(t)) {
        /*
         * The mapping was found in the software page hash table and is
         * writable. Demap the old mapping and insert an updated mapping
         * into DTLB.
         */
        t->a = true;
        t->d = true;
        dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_SECONDARY,
            va + index * MMU_PAGE_SIZE);
        dtlb_pte_copy(t, index, false);
#ifdef CONFIG_TSB
        dtsb_pte_copy(t, index, false);
#endif
        page_table_unlock(AS, true);
    } else {
        /*
         * Forward the page fault to the address space page fault
         * handler.
         */    
        page_table_unlock(AS, true);
        if (as_page_fault(va, PF_ACCESS_WRITE, istate) == AS_PF_FAULT) {
            do_fast_data_access_protection_fault(istate, tag,
                __FUNCTION__);
        }
    }
}
 
/** Print contents of both TLBs. */
void tlb_print(void)
{
    int i;
    tlb_data_t d;
    tlb_tag_read_reg_t t;
   
    printf("I-TLB contents:\n");
    for (i = 0; i < ITLB_ENTRY_COUNT; i++) {
        d.value = itlb_data_access_read(i);
        t.value = itlb_tag_read_read(i);
 
        printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, "
            "ie=%d, soft2=%#x, diag=%#x, pfn=%#x, soft=%#x, l=%d, "
            "cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n", i, t.vpn,
            t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag,
            d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);
    }
 
    printf("D-TLB contents:\n");
    for (i = 0; i < DTLB_ENTRY_COUNT; i++) {
        d.value = dtlb_data_access_read(i);
        t.value = dtlb_tag_read_read(i);
       
        printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, "
            "ie=%d, soft2=%#x, diag=%#x, pfn=%#x, soft=%#x, l=%d, "
            "cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n", i, t.vpn,
            t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag,
            d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);
    }
 
}
 
void do_fast_instruction_access_mmu_miss_fault(istate_t *istate,
    const char *str)
{
    fault_if_from_uspace(istate, "%s\n", str);
    dump_istate(istate);
    panic("%s\n", str);
}
 
void do_fast_data_access_mmu_miss_fault(istate_t *istate,
    tlb_tag_access_reg_t tag, const char *str)
{
    uintptr_t va;
 
    va = tag.vpn << MMU_PAGE_WIDTH;
 
    if (tag.context) {
        fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d)\n", str, va,
            tag.context);
    }
    dump_istate(istate);
    printf("Faulting page: %p, ASID=%d\n", va, tag.context);
    panic("%s\n", str);
}
 
void do_fast_data_access_protection_fault(istate_t *istate,
    tlb_tag_access_reg_t tag, const char *str)
{
    uintptr_t va;
 
    va = tag.vpn << MMU_PAGE_WIDTH;
 
    if (tag.context) {
        fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d)\n", str, va,
            tag.context);
    }
    printf("Faulting page: %p, ASID=%d\n", va, tag.context);
    dump_istate(istate);
    panic("%s\n", str);
}
 
void dump_sfsr_and_sfar(void)
{
    tlb_sfsr_reg_t sfsr;
    uintptr_t sfar;
 
    sfsr.value = dtlb_sfsr_read();
    sfar = dtlb_sfar_read();
   
    printf("DTLB SFSR: asi=%#x, ft=%#x, e=%d, ct=%d, pr=%d, w=%d, ow=%d, "
        "fv=%d\n", sfsr.asi, sfsr.ft, sfsr.e, sfsr.ct, sfsr.pr, sfsr.w,
        sfsr.ow, sfsr.fv);
    printf("DTLB SFAR: address=%p\n", sfar);
   
    dtlb_sfsr_write(0);
}
 
/** Invalidate all unlocked ITLB and DTLB entries. */
void tlb_invalidate_all(void)
{
    int i;
    tlb_data_t d;
    tlb_tag_read_reg_t t;
 
    /*
     * Walk all ITLB and DTLB entries and remove all unlocked mappings.
     *
     * The kernel doesn't use global mappings so any locked global mappings
     * found  must have been created by someone else. Their only purpose now
     * is to collide with proper mappings. Invalidate immediately. It should
     * be safe to invalidate them as late as now.
     */
 
    for (i = 0; i < ITLB_ENTRY_COUNT; i++) {
        d.value = itlb_data_access_read(i);
        if (!d.l || d.g) {
            t.value = itlb_tag_read_read(i);
            d.v = false;
            itlb_tag_access_write(t.value);
            itlb_data_access_write(i, d.value);
        }
    }
   
    for (i = 0; i < DTLB_ENTRY_COUNT; i++) {
        d.value = dtlb_data_access_read(i);
        if (!d.l || d.g) {
            t.value = dtlb_tag_read_read(i);
            d.v = false;
            dtlb_tag_access_write(t.value);
            dtlb_data_access_write(i, d.value);
        }
    }
   
}
 
/** Invalidate all ITLB and DTLB entries that belong to specified ASID
 * (Context).
 *
 * @param asid Address Space ID.
 */
void tlb_invalidate_asid(asid_t asid)
{
    tlb_context_reg_t pc_save, ctx;
   
    /* switch to nucleus because we are mapped by the primary context */
    nucleus_enter();
   
    ctx.v = pc_save.v = mmu_primary_context_read();
    ctx.context = asid;
    mmu_primary_context_write(ctx.v);
   
    itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_PRIMARY, 0);
    dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_PRIMARY, 0);
   
    mmu_primary_context_write(pc_save.v);
   
    nucleus_leave();
}
 
/** Invalidate all ITLB and DTLB entries for specified page range in specified
 * address space.
 *
 * @param asid Address Space ID.
 * @param page First page which to sweep out from ITLB and DTLB.
 * @param cnt Number of ITLB and DTLB entries to invalidate.
 */
void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt)
{
    int i;
    tlb_context_reg_t pc_save, ctx;
   
    /* switch to nucleus because we are mapped by the primary context */
    nucleus_enter();
   
    ctx.v = pc_save.v = mmu_primary_context_read();
    ctx.context = asid;
    mmu_primary_context_write(ctx.v);
   
    for (i = 0; i < cnt * MMU_PAGES_PER_PAGE; i++) {
        itlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_PRIMARY,
            page + i * MMU_PAGE_SIZE);
        dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_PRIMARY,
            page + i * MMU_PAGE_SIZE);
    }
   
    mmu_primary_context_write(pc_save.v);
   
    nucleus_leave();
}
 
/** @}
 */
 

Rev 2292	Rev 2307
1	/*	1	/*
2	* Copyright (c) 2005 Jakub Jermar	2	* Copyright (c) 2005 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	/** @addtogroup sparc64mm	29	/** @addtogroup sparc64mm
30	* @{	30	* @{
31	*/	31	*/
32	/** @file	32	/** @file
33	*/	33	*/
34		34
35	#include <arch/mm/tlb.h>	35	#include <arch/mm/tlb.h>
36	#include <mm/tlb.h>	36	#include <mm/tlb.h>
37	#include <mm/as.h>	37	#include <mm/as.h>
38	#include <mm/asid.h>	38	#include <mm/asid.h>
39	#include <arch/mm/frame.h>	39	#include <arch/mm/frame.h>
40	#include <arch/mm/page.h>	40	#include <arch/mm/page.h>
41	#include <arch/mm/mmu.h>	41	#include <arch/mm/mmu.h>
42	#include <arch/interrupt.h>	42	#include <arch/interrupt.h>
43	#include <interrupt.h>	43	#include <interrupt.h>
44	#include <arch.h>	44	#include <arch.h>
45	#include <print.h>	45	#include <print.h>
46	#include <arch/types.h>	46	#include <arch/types.h>
47	#include <config.h>	47	#include <config.h>
48	#include <arch/trap/trap.h>	48	#include <arch/trap/trap.h>
49	#include <arch/trap/exception.h>	49	#include <arch/trap/exception.h>
50	#include <panic.h>	50	#include <panic.h>
51	#include <arch/asm.h>	51	#include <arch/asm.h>
52		52
53	#ifdef CONFIG_TSB	53	#ifdef CONFIG_TSB
54	#include <arch/mm/tsb.h>	54	#include <arch/mm/tsb.h>
55	#endif	55	#endif
56		56
57	static void dtlb_pte_copy(pte_t *t, index_t index, bool ro);	57	static void dtlb_pte_copy(pte_t *t, index_t index, bool ro);
58	static void itlb_pte_copy(pte_t *t, index_t index);	58	static void itlb_pte_copy(pte_t *t, index_t index);
59	static void do_fast_instruction_access_mmu_miss_fault(istate_t *istate,	59	static void do_fast_instruction_access_mmu_miss_fault(istate_t *istate,
60	const char *str);	60	const char *str);
61	static void do_fast_data_access_mmu_miss_fault(istate_t *istate,	61	static void do_fast_data_access_mmu_miss_fault(istate_t *istate,
62	tlb_tag_access_reg_t tag, const char *str);	62	tlb_tag_access_reg_t tag, const char *str);
63	static void do_fast_data_access_protection_fault(istate_t *istate,	63	static void do_fast_data_access_protection_fault(istate_t *istate,
64	tlb_tag_access_reg_t tag, const char *str);	64	tlb_tag_access_reg_t tag, const char *str);
65		65
66	char *context_encoding[] = {	66	char *context_encoding[] = {
67	"Primary",	67	"Primary",
68	"Secondary",	68	"Secondary",
69	"Nucleus",	69	"Nucleus",
70	"Reserved"	70	"Reserved"
71	};	71	};
72		72
73	void tlb_arch_init(void)	73	void tlb_arch_init(void)
74	{	74	{
75	/*	75	/*
76	* Invalidate all non-locked DTLB and ITLB entries.	76	* Invalidate all non-locked DTLB and ITLB entries.
77	*/	77	*/
78	tlb_invalidate_all();	78	tlb_invalidate_all();
79		79
80	/*	80	/*
81	* Clear both SFSRs.	81	* Clear both SFSRs.
82	*/	82	*/
83	dtlb_sfsr_write(0);	83	dtlb_sfsr_write(0);
84	itlb_sfsr_write(0);	84	itlb_sfsr_write(0);
85	}	85	}
86		86
87	/** Insert privileged mapping into DMMU TLB.	87	/** Insert privileged mapping into DMMU TLB.
88	*	88	*
89	* @param page Virtual page address.	89	* @param page Virtual page address.
90	* @param frame Physical frame address.	90	* @param frame Physical frame address.
91	* @param pagesize Page size.	91	* @param pagesize Page size.
92	* @param locked True for permanent mappings, false otherwise.	92	* @param locked True for permanent mappings, false otherwise.
93	* @param cacheable True if the mapping is cacheable, false otherwise.	93	* @param cacheable True if the mapping is cacheable, false otherwise.
94	*/	94	*/
95	void dtlb_insert_mapping(uintptr_t page, uintptr_t frame, int pagesize,	95	void dtlb_insert_mapping(uintptr_t page, uintptr_t frame, int pagesize,
96	bool locked, bool cacheable)	96	bool locked, bool cacheable)
97	{	97	{
98	tlb_tag_access_reg_t tag;	98	tlb_tag_access_reg_t tag;
99	tlb_data_t data;	99	tlb_data_t data;
100	page_address_t pg;	100	page_address_t pg;
101	frame_address_t fr;	101	frame_address_t fr;
102		102
103	pg.address = page;	103	pg.address = page;
104	fr.address = frame;	104	fr.address = frame;
105		105
106	tag.value = ASID_KERNEL;	106	tag.value = ASID_KERNEL;
107	tag.vpn = pg.vpn;	107	tag.vpn = pg.vpn;
108		108
109	dtlb_tag_access_write(tag.value);	109	dtlb_tag_access_write(tag.value);
110		110
111	data.value = 0;	111	data.value = 0;
112	data.v = true;	112	data.v = true;
113	data.size = pagesize;	113	data.size = pagesize;
114	data.pfn = fr.pfn;	114	data.pfn = fr.pfn;
115	data.l = locked;	115	data.l = locked;
116	data.cp = cacheable;	116	data.cp = cacheable;
117	#ifdef CONFIG_VIRT_IDX_DCACHE	117	#ifdef CONFIG_VIRT_IDX_DCACHE
118	data.cv = cacheable;	118	data.cv = cacheable;
119	#endif /* CONFIG_VIRT_IDX_DCACHE */	119	#endif /* CONFIG_VIRT_IDX_DCACHE */
120	data.p = true;	120	data.p = true;
121	data.w = true;	121	data.w = true;
122	data.g = false;	122	data.g = false;
123		123
124	dtlb_data_in_write(data.value);	124	dtlb_data_in_write(data.value);
125	}	125	}
126		126
127	/** Copy PTE to TLB.	127	/** Copy PTE to TLB.
128	*	128	*
129	* @param t Page Table Entry to be copied.	129	* @param t Page Table Entry to be copied.
130	* @param index Zero if lower 8K-subpage, one if higher 8K-subpage.	130	* @param index Zero if lower 8K-subpage, one if higher 8K-subpage.
131	* @param ro If true, the entry will be created read-only, regardless of its	131	* @param ro If true, the entry will be created read-only, regardless of its
132	* w field.	132	* w field.
133	*/	133	*/
134	void dtlb_pte_copy(pte_t *t, index_t index, bool ro)	134	void dtlb_pte_copy(pte_t *t, index_t index, bool ro)
135	{	135	{
136	tlb_tag_access_reg_t tag;	136	tlb_tag_access_reg_t tag;
137	tlb_data_t data;	137	tlb_data_t data;
138	page_address_t pg;	138	page_address_t pg;
139	frame_address_t fr;	139	frame_address_t fr;
140		140
141	pg.address = t->page + (index << MMU_PAGE_WIDTH);	141	pg.address = t->page + (index << MMU_PAGE_WIDTH);
142	fr.address = t->frame + (index << MMU_PAGE_WIDTH);	142	fr.address = t->frame + (index << MMU_PAGE_WIDTH);
143		143
144	tag.value = 0;	144	tag.value = 0;
145	tag.context = t->as->asid;	145	tag.context = t->as->asid;
146	tag.vpn = pg.vpn;	146	tag.vpn = pg.vpn;
147		147
148	dtlb_tag_access_write(tag.value);	148	dtlb_tag_access_write(tag.value);
149		149
150	data.value = 0;	150	data.value = 0;
151	data.v = true;	151	data.v = true;
152	data.size = PAGESIZE_8K;	152	data.size = PAGESIZE_8K;
153	data.pfn = fr.pfn;	153	data.pfn = fr.pfn;
154	data.l = false;	154	data.l = false;
155	data.cp = t->c;	155	data.cp = t->c;
156	#ifdef CONFIG_VIRT_IDX_DCACHE	156	#ifdef CONFIG_VIRT_IDX_DCACHE
157	data.cv = t->c;	157	data.cv = t->c;
158	#endif /* CONFIG_VIRT_IDX_DCACHE */	158	#endif /* CONFIG_VIRT_IDX_DCACHE */
159	data.p = t->k; /* p like privileged */	159	data.p = t->k; /* p like privileged */
160	data.w = ro ? false : t->w;	160	data.w = ro ? false : t->w;
161	data.g = t->g;	161	data.g = t->g;
162		162
163	dtlb_data_in_write(data.value);	163	dtlb_data_in_write(data.value);
164	}	164	}
165		165
166	/** Copy PTE to ITLB.	166	/** Copy PTE to ITLB.
167	*	167	*
168	* @param t Page Table Entry to be copied.	168	* @param t Page Table Entry to be copied.
169	* @param index Zero if lower 8K-subpage, one if higher 8K-subpage.	169	* @param index Zero if lower 8K-subpage, one if higher 8K-subpage.
170	*/	170	*/
171	void itlb_pte_copy(pte_t *t, index_t index)	171	void itlb_pte_copy(pte_t *t, index_t index)
172	{	172	{
173	tlb_tag_access_reg_t tag;	173	tlb_tag_access_reg_t tag;
174	tlb_data_t data;	174	tlb_data_t data;
175	page_address_t pg;	175	page_address_t pg;
176	frame_address_t fr;	176	frame_address_t fr;
177		177
178	pg.address = t->page + (index << MMU_PAGE_WIDTH);	178	pg.address = t->page + (index << MMU_PAGE_WIDTH);
179	fr.address = t->frame + (index << MMU_PAGE_WIDTH);	179	fr.address = t->frame + (index << MMU_PAGE_WIDTH);
180		180
181	tag.value = 0;	181	tag.value = 0;
182	tag.context = t->as->asid;	182	tag.context = t->as->asid;
183	tag.vpn = pg.vpn;	183	tag.vpn = pg.vpn;
184		184
185	itlb_tag_access_write(tag.value);	185	itlb_tag_access_write(tag.value);
186		186
187	data.value = 0;	187	data.value = 0;
188	data.v = true;	188	data.v = true;
189	data.size = PAGESIZE_8K;	189	data.size = PAGESIZE_8K;
190	data.pfn = fr.pfn;	190	data.pfn = fr.pfn;
191	data.l = false;	191	data.l = false;
192	data.cp = t->c;	192	data.cp = t->c;
193	data.p = t->k; /* p like privileged */	193	data.p = t->k; /* p like privileged */
194	data.w = false;	194	data.w = false;
195	data.g = t->g;	195	data.g = t->g;
196		196
197	itlb_data_in_write(data.value);	197	itlb_data_in_write(data.value);
198	}	198	}
199		199
200	/** ITLB miss handler. */	200	/** ITLB miss handler. */
201	void fast_instruction_access_mmu_miss(int n, istate_t *istate)	201	void fast_instruction_access_mmu_miss(unative_t unused, istate_t *istate)
202	{	202	{
203	uintptr_t va = ALIGN_DOWN(istate->tpc, PAGE_SIZE);	203	uintptr_t va = ALIGN_DOWN(istate->tpc, PAGE_SIZE);
204	index_t index = (istate->tpc >> MMU_PAGE_WIDTH) % MMU_PAGES_PER_PAGE;	204	index_t index = (istate->tpc >> MMU_PAGE_WIDTH) % MMU_PAGES_PER_PAGE;
205	pte_t *t;	205	pte_t *t;
206		206
207	page_table_lock(AS, true);	207	page_table_lock(AS, true);
208	t = page_mapping_find(AS, va);	208	t = page_mapping_find(AS, va);
209	if (t && PTE_EXECUTABLE(t)) {	209	if (t && PTE_EXECUTABLE(t)) {
210	/*	210	/*
211	* The mapping was found in the software page hash table.	211	* The mapping was found in the software page hash table.
212	* Insert it into ITLB.	212	* Insert it into ITLB.
213	*/	213	*/
214	t->a = true;	214	t->a = true;
215	itlb_pte_copy(t, index);	215	itlb_pte_copy(t, index);
216	#ifdef CONFIG_TSB	216	#ifdef CONFIG_TSB
217	itsb_pte_copy(t, index);	217	itsb_pte_copy(t, index);
218	#endif	218	#endif
219	page_table_unlock(AS, true);	219	page_table_unlock(AS, true);
220	} else {	220	} else {
221	/*	221	/*
222	* Forward the page fault to the address space page fault	222	* Forward the page fault to the address space page fault
223	* handler.	223	* handler.
224	*/	224	*/
225	page_table_unlock(AS, true);	225	page_table_unlock(AS, true);
226	if (as_page_fault(va, PF_ACCESS_EXEC, istate) == AS_PF_FAULT) {	226	if (as_page_fault(va, PF_ACCESS_EXEC, istate) == AS_PF_FAULT) {
227	do_fast_instruction_access_mmu_miss_fault(istate,	227	do_fast_instruction_access_mmu_miss_fault(istate,
228	__FUNCTION__);	228	__FUNCTION__);
229	}	229	}
230	}	230	}
231	}	231	}
232		232
233	/** DTLB miss handler.	233	/** DTLB miss handler.
234	*	234	*
235	* Note that some faults (e.g. kernel faults) were already resolved by the	235	* Note that some faults (e.g. kernel faults) were already resolved by the
236	* low-level, assembly language part of the fast_data_access_mmu_miss handler.	236	* low-level, assembly language part of the fast_data_access_mmu_miss handler.
-		237	*
-		238	* @param tag Content of the TLB Tag Access register as it existed when the
-		239	* trap happened. This is to prevent confusion created by clobbered
-		240	* Tag Access register during a nested DTLB miss.
-		241	* @param istate Interrupted state saved on the stack.
237	*/	242	*/
238	void fast_data_access_mmu_miss(int n, istate_t *istate)	243	void fast_data_access_mmu_miss(tlb_tag_access_reg_t tag, istate_t *istate)
239	{	244	{
240	tlb_tag_access_reg_t tag;	-
241	uintptr_t va;	245	uintptr_t va;
242	index_t index;	246	index_t index;
243	pte_t *t;	247	pte_t *t;
244		248
245	tag.value = dtlb_tag_access_read();	-
246	va = ALIGN_DOWN((uint64_t) tag.vpn << MMU_PAGE_WIDTH, PAGE_SIZE);	249	va = ALIGN_DOWN((uint64_t) tag.vpn << MMU_PAGE_WIDTH, PAGE_SIZE);
247	index = tag.vpn % MMU_PAGES_PER_PAGE;	250	index = tag.vpn % MMU_PAGES_PER_PAGE;
248		251
249	if (tag.context == ASID_KERNEL) {	252	if (tag.context == ASID_KERNEL) {
250	if (!tag.vpn) {	253	if (!tag.vpn) {
251	/* NULL access in kernel */	254	/* NULL access in kernel */
252	do_fast_data_access_mmu_miss_fault(istate, tag,	255	do_fast_data_access_mmu_miss_fault(istate, tag,
253	__FUNCTION__);	256	__FUNCTION__);
254	}	257	}
255	do_fast_data_access_mmu_miss_fault(istate, tag, "Unexpected "	258	do_fast_data_access_mmu_miss_fault(istate, tag, "Unexpected "
256	"kernel page fault.");	259	"kernel page fault.");
257	}	260	}
258		261
259	page_table_lock(AS, true);	262	page_table_lock(AS, true);
260	t = page_mapping_find(AS, va);	263	t = page_mapping_find(AS, va);
261	if (t) {	264	if (t) {
262	/*	265	/*
263	* The mapping was found in the software page hash table.	266	* The mapping was found in the software page hash table.
264	* Insert it into DTLB.	267	* Insert it into DTLB.
265	*/	268	*/
266	t->a = true;	269	t->a = true;
267	dtlb_pte_copy(t, index, true);	270	dtlb_pte_copy(t, index, true);
268	#ifdef CONFIG_TSB	271	#ifdef CONFIG_TSB
269	dtsb_pte_copy(t, index, true);	272	dtsb_pte_copy(t, index, true);
270	#endif	273	#endif
271	page_table_unlock(AS, true);	274	page_table_unlock(AS, true);
272	} else {	275	} else {
273	/*	276	/*
274	* Forward the page fault to the address space page fault	277	* Forward the page fault to the address space page fault
275	* handler.	278	* handler.
276	*/	279	*/
277	page_table_unlock(AS, true);	280	page_table_unlock(AS, true);
278	if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) {	281	if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) {
279	do_fast_data_access_mmu_miss_fault(istate, tag,	282	do_fast_data_access_mmu_miss_fault(istate, tag,
280	__FUNCTION__);	283	__FUNCTION__);
281	}	284	}
282	}	285	}
283	}	286	}
284		287
285	/** DTLB protection fault handler. */	288	/** DTLB protection fault handler.
-		289	*
-		290	* @param tag Content of the TLB Tag Access register as it existed when the
-		291	* trap happened. This is to prevent confusion created by clobbered
-		292	* Tag Access register during a nested DTLB miss.
-		293	* @param istate Interrupted state saved on the stack.
-		294	*/
286	void fast_data_access_protection(int n, istate_t *istate)	295	void fast_data_access_protection(tlb_tag_access_reg_t tag, istate_t *istate)
287	{	296	{
288	tlb_tag_access_reg_t tag;	-
289	uintptr_t va;	297	uintptr_t va;
290	index_t index;	298	index_t index;
291	pte_t *t;	299	pte_t *t;
292		300
293	tag.value = dtlb_tag_access_read();	-
294	va = ALIGN_DOWN((uint64_t) tag.vpn << MMU_PAGE_WIDTH, PAGE_SIZE);	301	va = ALIGN_DOWN((uint64_t) tag.vpn << MMU_PAGE_WIDTH, PAGE_SIZE);
295	index = tag.vpn % MMU_PAGES_PER_PAGE; /* 16K-page emulation */	302	index = tag.vpn % MMU_PAGES_PER_PAGE; /* 16K-page emulation */
296		303
297	page_table_lock(AS, true);	304	page_table_lock(AS, true);
298	t = page_mapping_find(AS, va);	305	t = page_mapping_find(AS, va);
299	if (t && PTE_WRITABLE(t)) {	306	if (t && PTE_WRITABLE(t)) {
300	/*	307	/*
301	* The mapping was found in the software page hash table and is	308	* The mapping was found in the software page hash table and is
302	* writable. Demap the old mapping and insert an updated mapping	309	* writable. Demap the old mapping and insert an updated mapping
303	* into DTLB.	310	* into DTLB.
304	*/	311	*/
305	t->a = true;	312	t->a = true;
306	t->d = true;	313	t->d = true;
307	dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_SECONDARY,	314	dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_SECONDARY,
308	va + index * MMU_PAGE_SIZE);	315	va + index * MMU_PAGE_SIZE);
309	dtlb_pte_copy(t, index, false);	316	dtlb_pte_copy(t, index, false);
310	#ifdef CONFIG_TSB	317	#ifdef CONFIG_TSB
311	dtsb_pte_copy(t, index, false);	318	dtsb_pte_copy(t, index, false);
312	#endif	319	#endif
313	page_table_unlock(AS, true);	320	page_table_unlock(AS, true);
314	} else {	321	} else {
315	/*	322	/*
316	* Forward the page fault to the address space page fault	323	* Forward the page fault to the address space page fault
317	* handler.	324	* handler.
318	*/	325	*/
319	page_table_unlock(AS, true);	326	page_table_unlock(AS, true);
320	if (as_page_fault(va, PF_ACCESS_WRITE, istate) == AS_PF_FAULT) {	327	if (as_page_fault(va, PF_ACCESS_WRITE, istate) == AS_PF_FAULT) {
321	do_fast_data_access_protection_fault(istate, tag,	328	do_fast_data_access_protection_fault(istate, tag,
322	__FUNCTION__);	329	__FUNCTION__);
323	}	330	}
324	}	331	}
325	}	332	}
326		333
327	/** Print contents of both TLBs. */	334	/** Print contents of both TLBs. */
328	void tlb_print(void)	335	void tlb_print(void)
329	{	336	{
330	int i;	337	int i;
331	tlb_data_t d;	338	tlb_data_t d;
332	tlb_tag_read_reg_t t;	339	tlb_tag_read_reg_t t;
333		340
334	printf("I-TLB contents:\n");	341	printf("I-TLB contents:\n");
335	for (i = 0; i < ITLB_ENTRY_COUNT; i++) {	342	for (i = 0; i < ITLB_ENTRY_COUNT; i++) {
336	d.value = itlb_data_access_read(i);	343	d.value = itlb_data_access_read(i);
337	t.value = itlb_tag_read_read(i);	344	t.value = itlb_tag_read_read(i);
338		345
339	printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, "	346	printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, "
340	"ie=%d, soft2=%#x, diag=%#x, pfn=%#x, soft=%#x, l=%d, "	347	"ie=%d, soft2=%#x, diag=%#x, pfn=%#x, soft=%#x, l=%d, "
341	"cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n", i, t.vpn,	348	"cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n", i, t.vpn,
342	t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag,	349	t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag,
343	d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);	350	d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);
344	}	351	}
345		352
346	printf("D-TLB contents:\n");	353	printf("D-TLB contents:\n");
347	for (i = 0; i < DTLB_ENTRY_COUNT; i++) {	354	for (i = 0; i < DTLB_ENTRY_COUNT; i++) {
348	d.value = dtlb_data_access_read(i);	355	d.value = dtlb_data_access_read(i);
349	t.value = dtlb_tag_read_read(i);	356	t.value = dtlb_tag_read_read(i);
350		357
351	printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, "	358	printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, "
352	"ie=%d, soft2=%#x, diag=%#x, pfn=%#x, soft=%#x, l=%d, "	359	"ie=%d, soft2=%#x, diag=%#x, pfn=%#x, soft=%#x, l=%d, "
353	"cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n", i, t.vpn,	360	"cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n", i, t.vpn,
354	t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag,	361	t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag,
355	d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);	362	d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);
356	}	363	}
357		364
358	}	365	}
359		366
360	void do_fast_instruction_access_mmu_miss_fault(istate_t *istate,	367	void do_fast_instruction_access_mmu_miss_fault(istate_t *istate,
361	const char *str)	368	const char *str)
362	{	369	{
363	fault_if_from_uspace(istate, "%s\n", str);	370	fault_if_from_uspace(istate, "%s\n", str);
364	dump_istate(istate);	371	dump_istate(istate);
365	panic("%s\n", str);	372	panic("%s\n", str);
366	}	373	}
367		374
368	void do_fast_data_access_mmu_miss_fault(istate_t *istate,	375	void do_fast_data_access_mmu_miss_fault(istate_t *istate,
369	tlb_tag_access_reg_t tag, const char *str)	376	tlb_tag_access_reg_t tag, const char *str)
370	{	377	{
371	uintptr_t va;	378	uintptr_t va;
372		379
373	va = tag.vpn << MMU_PAGE_WIDTH;	380	va = tag.vpn << MMU_PAGE_WIDTH;
374		-
-		381	if (tag.context) {
375	fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d)\n", str, va,	382	fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d)\n", str, va,
376	tag.context);	383	tag.context);
-		384	}
377	dump_istate(istate);	385	dump_istate(istate);
378	printf("Faulting page: %p, ASID=%d\n", va, tag.context);	386	printf("Faulting page: %p, ASID=%d\n", va, tag.context);
379	panic("%s\n", str);	387	panic("%s\n", str);
380	}	388	}
381		389
382	void do_fast_data_access_protection_fault(istate_t *istate,	390	void do_fast_data_access_protection_fault(istate_t *istate,
383	tlb_tag_access_reg_t tag, const char *str)	391	tlb_tag_access_reg_t tag, const char *str)
384	{	392	{
385	uintptr_t va;	393	uintptr_t va;
386		394
387	va = tag.vpn << MMU_PAGE_WIDTH;	395	va = tag.vpn << MMU_PAGE_WIDTH;
388		396
-		397	if (tag.context) {
389	fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d)\n", str, va,	398	fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d)\n", str, va,
390	tag.context);	399	tag.context);
-		400	}
391	printf("Faulting page: %p, ASID=%d\n", va, tag.context);	401	printf("Faulting page: %p, ASID=%d\n", va, tag.context);
392	dump_istate(istate);	402	dump_istate(istate);
393	panic("%s\n", str);	403	panic("%s\n", str);
394	}	404	}
395		405
396	void dump_sfsr_and_sfar(void)	406	void dump_sfsr_and_sfar(void)
397	{	407	{
398	tlb_sfsr_reg_t sfsr;	408	tlb_sfsr_reg_t sfsr;
399	uintptr_t sfar;	409	uintptr_t sfar;
400		410
401	sfsr.value = dtlb_sfsr_read();	411	sfsr.value = dtlb_sfsr_read();
402	sfar = dtlb_sfar_read();	412	sfar = dtlb_sfar_read();
403		413
404	printf("DTLB SFSR: asi=%#x, ft=%#x, e=%d, ct=%d, pr=%d, w=%d, ow=%d, "	414	printf("DTLB SFSR: asi=%#x, ft=%#x, e=%d, ct=%d, pr=%d, w=%d, ow=%d, "
405	"fv=%d\n", sfsr.asi, sfsr.ft, sfsr.e, sfsr.ct, sfsr.pr, sfsr.w,	415	"fv=%d\n", sfsr.asi, sfsr.ft, sfsr.e, sfsr.ct, sfsr.pr, sfsr.w,
406	sfsr.ow, sfsr.fv);	416	sfsr.ow, sfsr.fv);
407	printf("DTLB SFAR: address=%p\n", sfar);	417	printf("DTLB SFAR: address=%p\n", sfar);
408		418
409	dtlb_sfsr_write(0);	419	dtlb_sfsr_write(0);
410	}	420	}
411		421
412	/** Invalidate all unlocked ITLB and DTLB entries. */	422	/** Invalidate all unlocked ITLB and DTLB entries. */
413	void tlb_invalidate_all(void)	423	void tlb_invalidate_all(void)
414	{	424	{
415	int i;	425	int i;
416	tlb_data_t d;	426	tlb_data_t d;
417	tlb_tag_read_reg_t t;	427	tlb_tag_read_reg_t t;
418		428
419	/*	429	/*
420	* Walk all ITLB and DTLB entries and remove all unlocked mappings.	430	* Walk all ITLB and DTLB entries and remove all unlocked mappings.
421	*	431	*
422	* The kernel doesn't use global mappings so any locked global mappings	432	* The kernel doesn't use global mappings so any locked global mappings
423	* found must have been created by someone else. Their only purpose now	433	* found must have been created by someone else. Their only purpose now
424	* is to collide with proper mappings. Invalidate immediately. It should	434	* is to collide with proper mappings. Invalidate immediately. It should
425	* be safe to invalidate them as late as now.	435	* be safe to invalidate them as late as now.
426	*/	436	*/
427		437
428	for (i = 0; i < ITLB_ENTRY_COUNT; i++) {	438	for (i = 0; i < ITLB_ENTRY_COUNT; i++) {
429	d.value = itlb_data_access_read(i);	439	d.value = itlb_data_access_read(i);
430	if (!d.l \|\| d.g) {	440	if (!d.l \|\| d.g) {
431	t.value = itlb_tag_read_read(i);	441	t.value = itlb_tag_read_read(i);
432	d.v = false;	442	d.v = false;
433	itlb_tag_access_write(t.value);	443	itlb_tag_access_write(t.value);
434	itlb_data_access_write(i, d.value);	444	itlb_data_access_write(i, d.value);
435	}	445	}
436	}	446	}
437		447
438	for (i = 0; i < DTLB_ENTRY_COUNT; i++) {	448	for (i = 0; i < DTLB_ENTRY_COUNT; i++) {
439	d.value = dtlb_data_access_read(i);	449	d.value = dtlb_data_access_read(i);
440	if (!d.l \|\| d.g) {	450	if (!d.l \|\| d.g) {
441	t.value = dtlb_tag_read_read(i);	451	t.value = dtlb_tag_read_read(i);
442	d.v = false;	452	d.v = false;
443	dtlb_tag_access_write(t.value);	453	dtlb_tag_access_write(t.value);
444	dtlb_data_access_write(i, d.value);	454	dtlb_data_access_write(i, d.value);
445	}	455	}
446	}	456	}
447		457
448	}	458	}
449		459
450	/** Invalidate all ITLB and DTLB entries that belong to specified ASID	460	/** Invalidate all ITLB and DTLB entries that belong to specified ASID
451	* (Context).	461	* (Context).
452	*	462	*
453	* @param asid Address Space ID.	463	* @param asid Address Space ID.
454	*/	464	*/
455	void tlb_invalidate_asid(asid_t asid)	465	void tlb_invalidate_asid(asid_t asid)
456	{	466	{
457	tlb_context_reg_t pc_save, ctx;	467	tlb_context_reg_t pc_save, ctx;
458		468
459	/* switch to nucleus because we are mapped by the primary context */	469	/* switch to nucleus because we are mapped by the primary context */
460	nucleus_enter();	470	nucleus_enter();
461		471
462	ctx.v = pc_save.v = mmu_primary_context_read();	472	ctx.v = pc_save.v = mmu_primary_context_read();
463	ctx.context = asid;	473	ctx.context = asid;
464	mmu_primary_context_write(ctx.v);	474	mmu_primary_context_write(ctx.v);
465		475
466	itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_PRIMARY, 0);	476	itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_PRIMARY, 0);
467	dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_PRIMARY, 0);	477	dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_PRIMARY, 0);
468		478
469	mmu_primary_context_write(pc_save.v);	479	mmu_primary_context_write(pc_save.v);
470		480
471	nucleus_leave();	481	nucleus_leave();
472	}	482	}
473		483
474	/** Invalidate all ITLB and DTLB entries for specified page range in specified	484	/** Invalidate all ITLB and DTLB entries for specified page range in specified
475	* address space.	485	* address space.
476	*	486	*
477	* @param asid Address Space ID.	487	* @param asid Address Space ID.
478	* @param page First page which to sweep out from ITLB and DTLB.	488	* @param page First page which to sweep out from ITLB and DTLB.
479	* @param cnt Number of ITLB and DTLB entries to invalidate.	489	* @param cnt Number of ITLB and DTLB entries to invalidate.
480	*/	490	*/
481	void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt)	491	void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt)
482	{	492	{
483	int i;	493	int i;
484	tlb_context_reg_t pc_save, ctx;	494	tlb_context_reg_t pc_save, ctx;
485		495

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(root)/branches/rcu/kernel/arch/sparc64/src/mm/tlb.c – Rev 2292 → 2307