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| 1 | /* |
1 | /* |
| 2 | * Copyright (c) 1987,1997, 2006, Vrije Universiteit, Amsterdam, The Netherlands All rights reserved. Redistribution and use of the MINIX 3 operating system in source and binary forms, with or without modification, are permitted provided that the following conditions are met: |
2 | * Copyright (c) 1987,1997, 2006, Vrije Universiteit, Amsterdam, The Netherlands All rights reserved. Redistribution and use of the MINIX 3 operating system in source and binary forms, with or without modification, are permitted provided that the following conditions are met: |
| 3 | * |
3 | * |
| 4 | * * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. |
4 | * * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. |
| 5 | * * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. |
5 | * * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. |
| 6 | * * Neither the name of the Vrije Universiteit nor the names of the software authors or contributors may be used to endorse or promote products derived from this software without specific prior written permission. |
6 | * * Neither the name of the Vrije Universiteit nor the names of the software authors or contributors may be used to endorse or promote products derived from this software without specific prior written permission. |
| 7 | * * Any deviations from these conditions require written permission from the copyright holder in advance |
7 | * * Any deviations from these conditions require written permission from the copyright holder in advance |
| 8 | * |
8 | * |
| 9 | * |
9 | * |
| 10 | * Disclaimer |
10 | * Disclaimer |
| 11 | * |
11 | * |
| 12 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS, AUTHORS, AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR |
12 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS, AUTHORS, AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR |
| 13 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
13 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| 14 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
14 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| 15 | * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR ANY AUTHORS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, |
15 | * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR ANY AUTHORS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, |
| 16 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
16 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| 17 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
17 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| 18 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
18 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| 19 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
19 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 20 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
20 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| 21 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
21 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 22 | * |
22 | * |
| 23 | * Changes: |
23 | * Changes: |
| 24 | * 2009 Lukas Mejdrech ported to HelenOS |
24 | * 2009 ported to HelenOS, Lukas Mejdrech |
| 25 | */ |
25 | */ |
| 26 | 26 | ||
| 27 | /** @addtogroup dp8390 |
27 | /** @addtogroup dp8390 |
| 28 | * @{ |
28 | * @{ |
| 29 | */ |
29 | */ |
| 30 | 30 | ||
| 31 | /** @file |
31 | /** @file |
| 32 | * \todo |
32 | * DP8390 network interface definitions. |
| 33 | */ |
33 | */ |
| 34 | 34 | ||
| 35 | #ifndef __NET_NETIF_DP8390_H__ |
35 | #ifndef __NET_NETIF_DP8390_H__ |
| 36 | #define __NET_NETIF_DP8390_H__ |
36 | #define __NET_NETIF_DP8390_H__ |
| 37 | 37 | ||
| 38 | #include "../../structures/packet/packet.h" |
38 | #include "../../structures/packet/packet.h" |
| 39 | 39 | ||
| 40 | #include "dp8390_port.h" |
40 | #include "dp8390_port.h" |
| 41 | #include "local.h" |
41 | #include "local.h" |
| 42 | 42 | ||
| - | 43 | /** Input/output size. |
|
| - | 44 | */ |
|
| 43 | #define DP8390_IO_SIZE 0x01f |
45 | #define DP8390_IO_SIZE 0x01f |
| 44 | 46 | ||
| 45 | /* |
47 | /* |
| 46 | dp8390.h |
48 | dp8390.h |
| 47 | 49 | ||
| 48 | Created: before Dec 28, 1992 by Philip Homburg |
50 | Created: before Dec 28, 1992 by Philip Homburg |
| 49 | */ |
51 | */ |
| 50 | 52 | ||
| 51 | /* National Semiconductor DP8390 Network Interface Controller. */ |
53 | /* National Semiconductor DP8390 Network Interface Controller. */ |
| 52 | 54 | ||
| 53 | /* Page 0, for reading ------------- */ |
55 | /* Page 0, for reading ------------- */ |
| 54 | #define DP_CR 0x0 /* Read side of Command Register */ |
56 | #define DP_CR 0x0 /* Read side of Command Register */ |
| 55 | #define DP_CLDA0 0x1 /* Current Local Dma Address 0 */ |
57 | #define DP_CLDA0 0x1 /* Current Local Dma Address 0 */ |
| 56 | #define DP_CLDA1 0x2 /* Current Local Dma Address 1 */ |
58 | #define DP_CLDA1 0x2 /* Current Local Dma Address 1 */ |
| 57 | #define DP_BNRY 0x3 /* Boundary Pointer */ |
59 | #define DP_BNRY 0x3 /* Boundary Pointer */ |
| 58 | #define DP_TSR 0x4 /* Transmit Status Register */ |
60 | #define DP_TSR 0x4 /* Transmit Status Register */ |
| 59 | #define DP_NCR 0x5 /* Number of Collisions Register */ |
61 | #define DP_NCR 0x5 /* Number of Collisions Register */ |
| 60 | #define DP_FIFO 0x6 /* Fifo ?? */ |
62 | #define DP_FIFO 0x6 /* Fifo ?? */ |
| 61 | #define DP_ISR 0x7 /* Interrupt Status Register */ |
63 | #define DP_ISR 0x7 /* Interrupt Status Register */ |
| 62 | #define DP_CRDA0 0x8 /* Current Remote Dma Address 0 */ |
64 | #define DP_CRDA0 0x8 /* Current Remote Dma Address 0 */ |
| 63 | #define DP_CRDA1 0x9 /* Current Remote Dma Address 1 */ |
65 | #define DP_CRDA1 0x9 /* Current Remote Dma Address 1 */ |
| 64 | #define DP_DUM1 0xA /* unused */ |
66 | #define DP_DUM1 0xA /* unused */ |
| 65 | #define DP_DUM2 0xB /* unused */ |
67 | #define DP_DUM2 0xB /* unused */ |
| 66 | #define DP_RSR 0xC /* Receive Status Register */ |
68 | #define DP_RSR 0xC /* Receive Status Register */ |
| 67 | #define DP_CNTR0 0xD /* Tally Counter 0 */ |
69 | #define DP_CNTR0 0xD /* Tally Counter 0 */ |
| 68 | #define DP_CNTR1 0xE /* Tally Counter 1 */ |
70 | #define DP_CNTR1 0xE /* Tally Counter 1 */ |
| 69 | #define DP_CNTR2 0xF /* Tally Counter 2 */ |
71 | #define DP_CNTR2 0xF /* Tally Counter 2 */ |
| 70 | 72 | ||
| 71 | /* Page 0, for writing ------------- */ |
73 | /* Page 0, for writing ------------- */ |
| 72 | #define DP_CR 0x0 /* Write side of Command Register */ |
74 | #define DP_CR 0x0 /* Write side of Command Register */ |
| 73 | #define DP_PSTART 0x1 /* Page Start Register */ |
75 | #define DP_PSTART 0x1 /* Page Start Register */ |
| 74 | #define DP_PSTOP 0x2 /* Page Stop Register */ |
76 | #define DP_PSTOP 0x2 /* Page Stop Register */ |
| 75 | #define DP_BNRY 0x3 /* Boundary Pointer */ |
77 | #define DP_BNRY 0x3 /* Boundary Pointer */ |
| 76 | #define DP_TPSR 0x4 /* Transmit Page Start Register */ |
78 | #define DP_TPSR 0x4 /* Transmit Page Start Register */ |
| 77 | #define DP_TBCR0 0x5 /* Transmit Byte Count Register 0 */ |
79 | #define DP_TBCR0 0x5 /* Transmit Byte Count Register 0 */ |
| 78 | #define DP_TBCR1 0x6 /* Transmit Byte Count Register 1 */ |
80 | #define DP_TBCR1 0x6 /* Transmit Byte Count Register 1 */ |
| 79 | #define DP_ISR 0x7 /* Interrupt Status Register */ |
81 | #define DP_ISR 0x7 /* Interrupt Status Register */ |
| 80 | #define DP_RSAR0 0x8 /* Remote Start Address Register 0 */ |
82 | #define DP_RSAR0 0x8 /* Remote Start Address Register 0 */ |
| 81 | #define DP_RSAR1 0x9 /* Remote Start Address Register 1 */ |
83 | #define DP_RSAR1 0x9 /* Remote Start Address Register 1 */ |
| 82 | #define DP_RBCR0 0xA /* Remote Byte Count Register 0 */ |
84 | #define DP_RBCR0 0xA /* Remote Byte Count Register 0 */ |
| 83 | #define DP_RBCR1 0xB /* Remote Byte Count Register 1 */ |
85 | #define DP_RBCR1 0xB /* Remote Byte Count Register 1 */ |
| 84 | #define DP_RCR 0xC /* Receive Configuration Register */ |
86 | #define DP_RCR 0xC /* Receive Configuration Register */ |
| 85 | #define DP_TCR 0xD /* Transmit Configuration Register */ |
87 | #define DP_TCR 0xD /* Transmit Configuration Register */ |
| 86 | #define DP_DCR 0xE /* Data Configuration Register */ |
88 | #define DP_DCR 0xE /* Data Configuration Register */ |
| 87 | #define DP_IMR 0xF /* Interrupt Mask Register */ |
89 | #define DP_IMR 0xF /* Interrupt Mask Register */ |
| 88 | 90 | ||
| 89 | /* Page 1, read/write -------------- */ |
91 | /* Page 1, read/write -------------- */ |
| 90 | #define DP_CR 0x0 /* Command Register */ |
92 | #define DP_CR 0x0 /* Command Register */ |
| 91 | #define DP_PAR0 0x1 /* Physical Address Register 0 */ |
93 | #define DP_PAR0 0x1 /* Physical Address Register 0 */ |
| 92 | #define DP_PAR1 0x2 /* Physical Address Register 1 */ |
94 | #define DP_PAR1 0x2 /* Physical Address Register 1 */ |
| 93 | #define DP_PAR2 0x3 /* Physical Address Register 2 */ |
95 | #define DP_PAR2 0x3 /* Physical Address Register 2 */ |
| 94 | #define DP_PAR3 0x4 /* Physical Address Register 3 */ |
96 | #define DP_PAR3 0x4 /* Physical Address Register 3 */ |
| 95 | #define DP_PAR4 0x5 /* Physical Address Register 4 */ |
97 | #define DP_PAR4 0x5 /* Physical Address Register 4 */ |
| 96 | #define DP_PAR5 0x6 /* Physical Address Register 5 */ |
98 | #define DP_PAR5 0x6 /* Physical Address Register 5 */ |
| 97 | #define DP_CURR 0x7 /* Current Page Register */ |
99 | #define DP_CURR 0x7 /* Current Page Register */ |
| 98 | #define DP_MAR0 0x8 /* Multicast Address Register 0 */ |
100 | #define DP_MAR0 0x8 /* Multicast Address Register 0 */ |
| 99 | #define DP_MAR1 0x9 /* Multicast Address Register 1 */ |
101 | #define DP_MAR1 0x9 /* Multicast Address Register 1 */ |
| 100 | #define DP_MAR2 0xA /* Multicast Address Register 2 */ |
102 | #define DP_MAR2 0xA /* Multicast Address Register 2 */ |
| 101 | #define DP_MAR3 0xB /* Multicast Address Register 3 */ |
103 | #define DP_MAR3 0xB /* Multicast Address Register 3 */ |
| 102 | #define DP_MAR4 0xC /* Multicast Address Register 4 */ |
104 | #define DP_MAR4 0xC /* Multicast Address Register 4 */ |
| 103 | #define DP_MAR5 0xD /* Multicast Address Register 5 */ |
105 | #define DP_MAR5 0xD /* Multicast Address Register 5 */ |
| 104 | #define DP_MAR6 0xE /* Multicast Address Register 6 */ |
106 | #define DP_MAR6 0xE /* Multicast Address Register 6 */ |
| 105 | #define DP_MAR7 0xF /* Multicast Address Register 7 */ |
107 | #define DP_MAR7 0xF /* Multicast Address Register 7 */ |
| 106 | 108 | ||
| 107 | /* Bits in dp_cr */ |
109 | /* Bits in dp_cr */ |
| 108 | #define CR_STP 0x01 /* Stop: software reset */ |
110 | #define CR_STP 0x01 /* Stop: software reset */ |
| 109 | #define CR_STA 0x02 /* Start: activate NIC */ |
111 | #define CR_STA 0x02 /* Start: activate NIC */ |
| 110 | #define CR_TXP 0x04 /* Transmit Packet */ |
112 | #define CR_TXP 0x04 /* Transmit Packet */ |
| 111 | #define CR_DMA 0x38 /* Mask for DMA control */ |
113 | #define CR_DMA 0x38 /* Mask for DMA control */ |
| 112 | #define CR_DM_NOP 0x00 /* DMA: No Operation */ |
114 | #define CR_DM_NOP 0x00 /* DMA: No Operation */ |
| 113 | #define CR_DM_RR 0x08 /* DMA: Remote Read */ |
115 | #define CR_DM_RR 0x08 /* DMA: Remote Read */ |
| 114 | #define CR_DM_RW 0x10 /* DMA: Remote Write */ |
116 | #define CR_DM_RW 0x10 /* DMA: Remote Write */ |
| 115 | #define CR_DM_SP 0x18 /* DMA: Send Packet */ |
117 | #define CR_DM_SP 0x18 /* DMA: Send Packet */ |
| 116 | #define CR_DM_ABORT 0x20 /* DMA: Abort Remote DMA Operation */ |
118 | #define CR_DM_ABORT 0x20 /* DMA: Abort Remote DMA Operation */ |
| 117 | #define CR_PS 0xC0 /* Mask for Page Select */ |
119 | #define CR_PS 0xC0 /* Mask for Page Select */ |
| 118 | #define CR_PS_P0 0x00 /* Register Page 0 */ |
120 | #define CR_PS_P0 0x00 /* Register Page 0 */ |
| 119 | #define CR_PS_P1 0x40 /* Register Page 1 */ |
121 | #define CR_PS_P1 0x40 /* Register Page 1 */ |
| 120 | #define CR_PS_P2 0x80 /* Register Page 2 */ |
122 | #define CR_PS_P2 0x80 /* Register Page 2 */ |
| 121 | #define CR_PS_T1 0xC0 /* Test Mode Register Map */ |
123 | #define CR_PS_T1 0xC0 /* Test Mode Register Map */ |
| 122 | 124 | ||
| 123 | /* Bits in dp_isr */ |
125 | /* Bits in dp_isr */ |
| 124 | #define ISR_PRX 0x01 /* Packet Received with no errors */ |
126 | #define ISR_PRX 0x01 /* Packet Received with no errors */ |
| 125 | #define ISR_PTX 0x02 /* Packet Transmitted with no errors */ |
127 | #define ISR_PTX 0x02 /* Packet Transmitted with no errors */ |
| 126 | #define ISR_RXE 0x04 /* Receive Error */ |
128 | #define ISR_RXE 0x04 /* Receive Error */ |
| 127 | #define ISR_TXE 0x08 /* Transmit Error */ |
129 | #define ISR_TXE 0x08 /* Transmit Error */ |
| 128 | #define ISR_OVW 0x10 /* Overwrite Warning */ |
130 | #define ISR_OVW 0x10 /* Overwrite Warning */ |
| 129 | #define ISR_CNT 0x20 /* Counter Overflow */ |
131 | #define ISR_CNT 0x20 /* Counter Overflow */ |
| 130 | #define ISR_RDC 0x40 /* Remote DMA Complete */ |
132 | #define ISR_RDC 0x40 /* Remote DMA Complete */ |
| 131 | #define ISR_RST 0x80 /* Reset Status */ |
133 | #define ISR_RST 0x80 /* Reset Status */ |
| 132 | 134 | ||
| 133 | /* Bits in dp_imr */ |
135 | /* Bits in dp_imr */ |
| 134 | #define IMR_PRXE 0x01 /* Packet Received iEnable */ |
136 | #define IMR_PRXE 0x01 /* Packet Received iEnable */ |
| 135 | #define IMR_PTXE 0x02 /* Packet Transmitted iEnable */ |
137 | #define IMR_PTXE 0x02 /* Packet Transmitted iEnable */ |
| 136 | #define IMR_RXEE 0x04 /* Receive Error iEnable */ |
138 | #define IMR_RXEE 0x04 /* Receive Error iEnable */ |
| 137 | #define IMR_TXEE 0x08 /* Transmit Error iEnable */ |
139 | #define IMR_TXEE 0x08 /* Transmit Error iEnable */ |
| 138 | #define IMR_OVWE 0x10 /* Overwrite Warning iEnable */ |
140 | #define IMR_OVWE 0x10 /* Overwrite Warning iEnable */ |
| 139 | #define IMR_CNTE 0x20 /* Counter Overflow iEnable */ |
141 | #define IMR_CNTE 0x20 /* Counter Overflow iEnable */ |
| 140 | #define IMR_RDCE 0x40 /* DMA Complete iEnable */ |
142 | #define IMR_RDCE 0x40 /* DMA Complete iEnable */ |
| 141 | 143 | ||
| 142 | /* Bits in dp_dcr */ |
144 | /* Bits in dp_dcr */ |
| 143 | #define DCR_WTS 0x01 /* Word Transfer Select */ |
145 | #define DCR_WTS 0x01 /* Word Transfer Select */ |
| 144 | #define DCR_BYTEWIDE 0x00 /* WTS: byte wide transfers */ |
146 | #define DCR_BYTEWIDE 0x00 /* WTS: byte wide transfers */ |
| 145 | #define DCR_WORDWIDE 0x01 /* WTS: word wide transfers */ |
147 | #define DCR_WORDWIDE 0x01 /* WTS: word wide transfers */ |
| 146 | #define DCR_BOS 0x02 /* Byte Order Select */ |
148 | #define DCR_BOS 0x02 /* Byte Order Select */ |
| 147 | #define DCR_LTLENDIAN 0x00 /* BOS: Little Endian */ |
149 | #define DCR_LTLENDIAN 0x00 /* BOS: Little Endian */ |
| 148 | #define DCR_BIGENDIAN 0x02 /* BOS: Big Endian */ |
150 | #define DCR_BIGENDIAN 0x02 /* BOS: Big Endian */ |
| 149 | #define DCR_LAS 0x04 /* Long Address Select */ |
151 | #define DCR_LAS 0x04 /* Long Address Select */ |
| 150 | #define DCR_BMS 0x08 /* Burst Mode Select |
152 | #define DCR_BMS 0x08 /* Burst Mode Select |
| 151 | * Called Loopback Select (LS) in |
153 | * Called Loopback Select (LS) in |
| 152 | * later manuals. Should be set. */ |
154 | * later manuals. Should be set. */ |
| 153 | #define DCR_AR 0x10 /* Autoinitialize Remote */ |
155 | #define DCR_AR 0x10 /* Autoinitialize Remote */ |
| 154 | #define DCR_FTS 0x60 /* Fifo Threshold Select */ |
156 | #define DCR_FTS 0x60 /* Fifo Threshold Select */ |
| 155 | #define DCR_2BYTES 0x00 /* 2 bytes */ |
157 | #define DCR_2BYTES 0x00 /* 2 bytes */ |
| 156 | #define DCR_4BYTES 0x40 /* 4 bytes */ |
158 | #define DCR_4BYTES 0x40 /* 4 bytes */ |
| 157 | #define DCR_8BYTES 0x20 /* 8 bytes */ |
159 | #define DCR_8BYTES 0x20 /* 8 bytes */ |
| 158 | #define DCR_12BYTES 0x60 /* 12 bytes */ |
160 | #define DCR_12BYTES 0x60 /* 12 bytes */ |
| 159 | 161 | ||
| 160 | /* Bits in dp_tcr */ |
162 | /* Bits in dp_tcr */ |
| 161 | #define TCR_CRC 0x01 /* Inhibit CRC */ |
163 | #define TCR_CRC 0x01 /* Inhibit CRC */ |
| 162 | #define TCR_ELC 0x06 /* Encoded Loopback Control */ |
164 | #define TCR_ELC 0x06 /* Encoded Loopback Control */ |
| 163 | #define TCR_NORMAL 0x00 /* ELC: Normal Operation */ |
165 | #define TCR_NORMAL 0x00 /* ELC: Normal Operation */ |
| 164 | #define TCR_INTERNAL 0x02 /* ELC: Internal Loopback */ |
166 | #define TCR_INTERNAL 0x02 /* ELC: Internal Loopback */ |
| 165 | #define TCR_0EXTERNAL 0x04 /* ELC: External Loopback LPBK=0 */ |
167 | #define TCR_0EXTERNAL 0x04 /* ELC: External Loopback LPBK=0 */ |
| 166 | #define TCR_1EXTERNAL 0x06 /* ELC: External Loopback LPBK=1 */ |
168 | #define TCR_1EXTERNAL 0x06 /* ELC: External Loopback LPBK=1 */ |
| 167 | #define TCR_ATD 0x08 /* Auto Transmit Disable */ |
169 | #define TCR_ATD 0x08 /* Auto Transmit Disable */ |
| 168 | #define TCR_OFST 0x10 /* Collision Offset Enable (be nice) */ |
170 | #define TCR_OFST 0x10 /* Collision Offset Enable (be nice) */ |
| 169 | 171 | ||
| 170 | /* Bits in dp_tsr */ |
172 | /* Bits in dp_tsr */ |
| 171 | #define TSR_PTX 0x01 /* Packet Transmitted (without error)*/ |
173 | #define TSR_PTX 0x01 /* Packet Transmitted (without error)*/ |
| 172 | #define TSR_DFR 0x02 /* Transmit Deferred, reserved in |
174 | #define TSR_DFR 0x02 /* Transmit Deferred, reserved in |
| 173 | * later manuals. */ |
175 | * later manuals. */ |
| 174 | #define TSR_COL 0x04 /* Transmit Collided */ |
176 | #define TSR_COL 0x04 /* Transmit Collided */ |
| 175 | #define TSR_ABT 0x08 /* Transmit Aborted */ |
177 | #define TSR_ABT 0x08 /* Transmit Aborted */ |
| 176 | #define TSR_CRS 0x10 /* Carrier Sense Lost */ |
178 | #define TSR_CRS 0x10 /* Carrier Sense Lost */ |
| 177 | #define TSR_FU 0x20 /* FIFO Underrun */ |
179 | #define TSR_FU 0x20 /* FIFO Underrun */ |
| 178 | #define TSR_CDH 0x40 /* CD Heartbeat */ |
180 | #define TSR_CDH 0x40 /* CD Heartbeat */ |
| 179 | #define TSR_OWC 0x80 /* Out of Window Collision */ |
181 | #define TSR_OWC 0x80 /* Out of Window Collision */ |
| 180 | 182 | ||
| 181 | /* Bits in tp_rcr */ |
183 | /* Bits in tp_rcr */ |
| 182 | #define RCR_SEP 0x01 /* Save Errored Packets */ |
184 | #define RCR_SEP 0x01 /* Save Errored Packets */ |
| 183 | #define RCR_AR 0x02 /* Accept Runt Packets */ |
185 | #define RCR_AR 0x02 /* Accept Runt Packets */ |
| 184 | #define RCR_AB 0x04 /* Accept Broadcast */ |
186 | #define RCR_AB 0x04 /* Accept Broadcast */ |
| 185 | #define RCR_AM 0x08 /* Accept Multicast */ |
187 | #define RCR_AM 0x08 /* Accept Multicast */ |
| 186 | #define RCR_PRO 0x10 /* Physical Promiscuous */ |
188 | #define RCR_PRO 0x10 /* Physical Promiscuous */ |
| 187 | #define RCR_MON 0x20 /* Monitor Mode */ |
189 | #define RCR_MON 0x20 /* Monitor Mode */ |
| 188 | 190 | ||
| 189 | /* Bits in dp_rsr */ |
191 | /* Bits in dp_rsr */ |
| 190 | #define RSR_PRX 0x01 /* Packet Received Intact */ |
192 | #define RSR_PRX 0x01 /* Packet Received Intact */ |
| 191 | #define RSR_CRC 0x02 /* CRC Error */ |
193 | #define RSR_CRC 0x02 /* CRC Error */ |
| 192 | #define RSR_FAE 0x04 /* Frame Alignment Error */ |
194 | #define RSR_FAE 0x04 /* Frame Alignment Error */ |
| 193 | #define RSR_FO 0x08 /* FIFO Overrun */ |
195 | #define RSR_FO 0x08 /* FIFO Overrun */ |
| 194 | #define RSR_MPA 0x10 /* Missed Packet */ |
196 | #define RSR_MPA 0x10 /* Missed Packet */ |
| 195 | #define RSR_PHY 0x20 /* Multicast Address Match */ |
197 | #define RSR_PHY 0x20 /* Multicast Address Match */ |
| 196 | #define RSR_DIS 0x40 /* Receiver Disabled */ |
198 | #define RSR_DIS 0x40 /* Receiver Disabled */ |
| 197 | #define RSR_DFR 0x80 /* In later manuals: Deferring */ |
199 | #define RSR_DFR 0x80 /* In later manuals: Deferring */ |
| 198 | 200 | ||
| - | 201 | /** Type definition of the receive header. |
|
| 199 | 202 | */ |
|
| 200 | typedef struct dp_rcvhdr |
203 | typedef struct dp_rcvhdr |
| 201 | { |
204 | { |
| - | 205 | /** Copy of rsr. |
|
| - | 206 | */ |
|
| 202 | u8_t dr_status; /* Copy of rsr */ |
207 | u8_t dr_status; |
| 203 | u8_t dr_next; /* Pointer to next packet */ |
208 | /** Pointer to next packet. |
| - | 209 | */ |
|
| - | 210 | u8_t dr_next; |
|
| 204 | u8_t dr_rbcl; /* Receive Byte Count Low */ |
211 | /** Receive Byte Count Low. |
| - | 212 | */ |
|
| - | 213 | u8_t dr_rbcl; |
|
| 205 | u8_t dr_rbch; /* Receive Byte Count High */ |
214 | /** Receive Byte Count High. |
| - | 215 | */ |
|
| - | 216 | u8_t dr_rbch; |
|
| 206 | } dp_rcvhdr_t; |
217 | } dp_rcvhdr_t; |
| 207 | 218 | ||
| - | 219 | /** Page size. |
|
| - | 220 | */ |
|
| 208 | #define DP_PAGESIZE 256 |
221 | #define DP_PAGESIZE 256 |
| 209 | 222 | ||
| 210 | /* Some macros to simplify accessing the dp8390 */ |
223 | /* Some macros to simplify accessing the dp8390 */ |
| - | 224 | /** Reads 1 byte from the zero page register. |
|
| - | 225 | * @param[in] dep The network interface structure. |
|
| - | 226 | * @param[in] reg The register offset. |
|
| - | 227 | * @returns The read value. |
|
| - | 228 | */ |
|
| 211 | #define inb_reg0(dep, reg) (inb(dep->de_dp8390_port+reg)) |
229 | #define inb_reg0(dep, reg) (inb(dep->de_dp8390_port+reg)) |
| - | 230 | ||
| - | 231 | /** Writes 1 byte zero page register. |
|
| - | 232 | * @param[in] dep The network interface structure. |
|
| - | 233 | * @param[in] reg The register offset. |
|
| - | 234 | * @param[in] data The value to be written. |
|
| - | 235 | */ |
|
| 212 | #define outb_reg0(dep, reg, data) (outb(dep->de_dp8390_port+reg, data)) |
236 | #define outb_reg0(dep, reg, data) (outb(dep->de_dp8390_port+reg, data)) |
| - | 237 | ||
| - | 238 | /** Reads 1 byte from the first page register. |
|
| - | 239 | * @param[in] dep The network interface structure. |
|
| - | 240 | * @param[in] reg The register offset. |
|
| - | 241 | * @returns The read value. |
|
| - | 242 | */ |
|
| 213 | #define inb_reg1(dep, reg) (inb(dep->de_dp8390_port+reg)) |
243 | #define inb_reg1(dep, reg) (inb(dep->de_dp8390_port+reg)) |
| - | 244 | ||
| - | 245 | /** Writes 1 byte first page register. |
|
| - | 246 | * @param[in] dep The network interface structure. |
|
| - | 247 | * @param[in] reg The register offset. |
|
| - | 248 | * @param[in] data The value to be written. |
|
| - | 249 | */ |
|
| 214 | #define outb_reg1(dep, reg, data) (outb(dep->de_dp8390_port+reg, data)) |
250 | #define outb_reg1(dep, reg, data) (outb(dep->de_dp8390_port+reg, data)) |
| 215 | 251 | ||
| 216 | /* Software interface to the dp8390 driver */ |
252 | /* Software interface to the dp8390 driver */ |
| 217 | 253 | ||
| 218 | struct dpeth; |
254 | struct dpeth; |
| 219 | struct iovec_dat; |
255 | struct iovec_dat; |
| 220 | //struct iovec_dat_s; |
256 | //struct iovec_dat_s; |
| 221 | _PROTOTYPE( typedef void (*dp_initf_t), (struct dpeth *dep) ); |
257 | _PROTOTYPE( typedef void (*dp_initf_t), (struct dpeth *dep) ); |
| 222 | _PROTOTYPE( typedef void (*dp_stopf_t), (struct dpeth *dep) ); |
258 | _PROTOTYPE( typedef void (*dp_stopf_t), (struct dpeth *dep) ); |
| 223 | _PROTOTYPE( typedef void (*dp_user2nicf_t), (struct dpeth *dep, |
259 | _PROTOTYPE( typedef void (*dp_user2nicf_t), (struct dpeth *dep, |
| 224 | struct iovec_dat *iovp, vir_bytes offset, |
260 | struct iovec_dat *iovp, vir_bytes offset, |
| 225 | int nic_addr, vir_bytes count) ); |
261 | int nic_addr, vir_bytes count) ); |
| 226 | //_PROTOTYPE( typedef void (*dp_user2nicf_s_t), (struct dpeth *dep, |
262 | //_PROTOTYPE( typedef void (*dp_user2nicf_s_t), (struct dpeth *dep, |
| 227 | // struct iovec_dat_s *iovp, vir_bytes offset, |
263 | // struct iovec_dat_s *iovp, vir_bytes offset, |
| 228 | // int nic_addr, vir_bytes count) ); |
264 | // int nic_addr, vir_bytes count) ); |
| 229 | _PROTOTYPE( typedef void (*dp_nic2userf_t), (struct dpeth *dep, |
265 | _PROTOTYPE( typedef void (*dp_nic2userf_t), (struct dpeth *dep, |
| 230 | int nic_addr, struct iovec_dat *iovp, |
266 | int nic_addr, struct iovec_dat *iovp, |
| 231 | vir_bytes offset, vir_bytes count) ); |
267 | vir_bytes offset, vir_bytes count) ); |
| 232 | //_PROTOTYPE( typedef void (*dp_nic2userf_s_t), (struct dpeth *dep, |
268 | //_PROTOTYPE( typedef void (*dp_nic2userf_s_t), (struct dpeth *dep, |
| 233 | // int nic_addr, struct iovec_dat_s *iovp, |
269 | // int nic_addr, struct iovec_dat_s *iovp, |
| 234 | // vir_bytes offset, vir_bytes count) ); |
270 | // vir_bytes offset, vir_bytes count) ); |
| 235 | //#if 0 |
271 | //#if 0 |
| 236 | //_PROTOTYPE( typedef void (*dp_getheaderf_t), (struct dpeth *dep, |
272 | //_PROTOTYPE( typedef void (*dp_getheaderf_t), (struct dpeth *dep, |
| 237 | // int page, struct dp_rcvhdr *h, u16_t *eth_type) ); |
273 | // int page, struct dp_rcvhdr *h, u16_t *eth_type) ); |
| 238 | //#endif |
274 | //#endif |
| 239 | _PROTOTYPE( typedef void (*dp_getblock_t), (struct dpeth *dep, |
275 | _PROTOTYPE( typedef void (*dp_getblock_t), (struct dpeth *dep, |
| 240 | int page, size_t offset, size_t size, void *dst) ); |
276 | int page, size_t offset, size_t size, void *dst) ); |
| 241 | 277 | ||
| 242 | /* iovectors are handled IOVEC_NR entries at a time. */ |
278 | /* iovectors are handled IOVEC_NR entries at a time. */ |
| 243 | //#define IOVEC_NR 16 |
279 | //#define IOVEC_NR 16 |
| 244 | // no vectors allowed |
280 | // no vectors allowed |
| 245 | #define IOVEC_NR 1 |
281 | #define IOVEC_NR 1 |
| 246 | 282 | ||
| 247 | /* |
283 | /* |
| 248 | typedef int irq_hook_t; |
284 | typedef int irq_hook_t; |
| 249 | */ |
285 | */ |
| 250 | typedef struct iovec_dat |
286 | typedef struct iovec_dat |
| 251 | { |
287 | { |
| 252 | iovec_t iod_iovec[IOVEC_NR]; |
288 | iovec_t iod_iovec[IOVEC_NR]; |
| 253 | int iod_iovec_s; |
289 | int iod_iovec_s; |
| 254 | // no direct process access |
290 | // no direct process access |
| 255 | int iod_proc_nr; |
291 | int iod_proc_nr; |
| 256 | vir_bytes iod_iovec_addr; |
292 | vir_bytes iod_iovec_addr; |
| 257 | } iovec_dat_t; |
293 | } iovec_dat_t; |
| 258 | /* |
294 | /* |
| 259 | typedef struct iovec_dat_s |
295 | typedef struct iovec_dat_s |
| 260 | { |
296 | { |
| 261 | iovec_s_t iod_iovec[IOVEC_NR]; |
297 | iovec_s_t iod_iovec[IOVEC_NR]; |
| 262 | int iod_iovec_s; |
298 | int iod_iovec_s; |
| 263 | int iod_proc_nr; |
299 | int iod_proc_nr; |
| 264 | cp_grant_id_t iod_grant; |
300 | cp_grant_id_t iod_grant; |
| 265 | vir_bytes iod_iovec_offset; |
301 | vir_bytes iod_iovec_offset; |
| 266 | } iovec_dat_s_t; |
302 | } iovec_dat_s_t; |
| 267 | */ |
303 | */ |
| 268 | #define SENDQ_NR 1 /* Maximum size of the send queue */ |
304 | #define SENDQ_NR 1 /* Maximum size of the send queue */ |
| 269 | #define SENDQ_PAGES 6 /* 6 * DP_PAGESIZE >= 1514 bytes */ |
305 | #define SENDQ_PAGES 6 /* 6 * DP_PAGESIZE >= 1514 bytes */ |
| 270 | 306 | ||
| 271 | /** Maximum number of waiting packets to be sent or received. |
307 | /** Maximum number of waiting packets to be sent or received. |
| 272 | */ |
308 | */ |
| 273 | #define MAX_PACKETS 4 |
309 | #define MAX_PACKETS 4 |
| 274 | 310 | ||
| 275 | typedef struct dpeth |
311 | typedef struct dpeth |
| 276 | { |
312 | { |
| 277 | /* Packet send queue. |
313 | /** Outgoing packets queue. |
| 278 | */ |
314 | */ |
| 279 | packet_t packet_queue; |
315 | packet_t packet_queue; |
| - | 316 | /** Outgoing packets count. |
|
| - | 317 | */ |
|
| 280 | int packet_count; |
318 | int packet_count; |
| 281 | 319 | ||
| 282 | /* Packet receive queue. |
320 | /** Received packets queue. |
| 283 | */ |
321 | */ |
| 284 | packet_t received_queue; |
322 | packet_t received_queue; |
| - | 323 | /** Received packets count. |
|
| - | 324 | */ |
|
| 285 | int received_count; |
325 | int received_count; |
| 286 | 326 | ||
| 287 | /* The de_base_port field is the starting point of the probe. |
327 | /* The de_base_port field is the starting point of the probe. |
| 288 | * The conf routine also fills de_linmem and de_irq. If the probe |
328 | * The conf routine also fills de_linmem and de_irq. If the probe |
| 289 | * routine knows the irq and/or memory address because they are |
329 | * routine knows the irq and/or memory address because they are |
| 290 | * hardwired in the board, the probe should modify these fields. |
330 | * hardwired in the board, the probe should modify these fields. |
| 291 | * Futhermore, the probe routine should also fill in de_initf and |
331 | * Futhermore, the probe routine should also fill in de_initf and |
| 292 | * de_stopf fields with the appropriate function pointers and set |
332 | * de_stopf fields with the appropriate function pointers and set |
| 293 | * de_prog_IO iff programmed I/O is to be used. |
333 | * de_prog_IO iff programmed I/O is to be used. |
| 294 | */ |
334 | */ |
| 295 | port_t de_base_port; |
335 | port_t de_base_port; |
| 296 | phys_bytes de_linmem; |
336 | phys_bytes de_linmem; |
| 297 | char *de_locmem; |
337 | char *de_locmem; |
| 298 | int de_irq; |
338 | int de_irq; |
| 299 | int de_int_pending; |
339 | int de_int_pending; |
| 300 | // irq_hook_t de_hook; |
340 | // irq_hook_t de_hook; |
| 301 | dp_initf_t de_initf; |
341 | dp_initf_t de_initf; |
| 302 | dp_stopf_t de_stopf; |
342 | dp_stopf_t de_stopf; |
| 303 | int de_prog_IO; |
343 | int de_prog_IO; |
| 304 | char de_name[sizeof("dp8390#n")]; |
344 | char de_name[sizeof("dp8390#n")]; |
| 305 | 345 | ||
| 306 | /* The initf function fills the following fields. Only cards that do |
346 | /* The initf function fills the following fields. Only cards that do |
| 307 | * programmed I/O fill in the de_pata_port field. |
347 | * programmed I/O fill in the de_pata_port field. |
| 308 | * In addition, the init routine has to fill in the sendq data |
348 | * In addition, the init routine has to fill in the sendq data |
| 309 | * structures. |
349 | * structures. |
| 310 | */ |
350 | */ |
| 311 | ether_addr_t de_address; |
351 | ether_addr_t de_address; |
| 312 | port_t de_dp8390_port; |
352 | port_t de_dp8390_port; |
| 313 | port_t de_data_port; |
353 | port_t de_data_port; |
| 314 | int de_16bit; |
354 | int de_16bit; |
| 315 | int de_ramsize; |
355 | int de_ramsize; |
| 316 | int de_offset_page; |
356 | int de_offset_page; |
| 317 | int de_startpage; |
357 | int de_startpage; |
| 318 | int de_stoppage; |
358 | int de_stoppage; |
| 319 | 359 | ||
| 320 | /* should be here - read even for ne2k isa init... */ |
360 | /* should be here - read even for ne2k isa init... */ |
| 321 | char de_pci; /* TRUE iff PCI device */ |
361 | char de_pci; /* TRUE iff PCI device */ |
| 322 | 362 | ||
| 323 | #if ENABLE_PCI |
363 | #if ENABLE_PCI |
| 324 | /* PCI config */ |
364 | /* PCI config */ |
| 325 | // char de_pci; /* TRUE iff PCI device */ |
365 | // char de_pci; /* TRUE iff PCI device */ |
| 326 | // u8_t de_pcibus; |
366 | // u8_t de_pcibus; |
| 327 | // u8_t de_pcidev; |
367 | // u8_t de_pcidev; |
| 328 | // u8_t de_pcifunc; |
368 | // u8_t de_pcifunc; |
| 329 | #endif |
369 | #endif |
| 330 | 370 | ||
| 331 | /* Do it yourself send queue */ |
371 | /* Do it yourself send queue */ |
| 332 | struct sendq |
372 | struct sendq |
| 333 | { |
373 | { |
| 334 | int sq_filled; /* this buffer contains a packet */ |
374 | int sq_filled; /* this buffer contains a packet */ |
| 335 | int sq_size; /* with this size */ |
375 | int sq_size; /* with this size */ |
| 336 | int sq_sendpage; /* starting page of the buffer */ |
376 | int sq_sendpage; /* starting page of the buffer */ |
| 337 | } de_sendq[SENDQ_NR]; |
377 | } de_sendq[SENDQ_NR]; |
| 338 | int de_sendq_nr; |
378 | int de_sendq_nr; |
| 339 | int de_sendq_head; /* Enqueue at the head */ |
379 | int de_sendq_head; /* Enqueue at the head */ |
| 340 | int de_sendq_tail; /* Dequeue at the tail */ |
380 | int de_sendq_tail; /* Dequeue at the tail */ |
| 341 | 381 | ||
| 342 | /* Fields for internal use by the dp8390 driver. */ |
382 | /* Fields for internal use by the dp8390 driver. */ |
| 343 | int de_flags; |
383 | int de_flags; |
| 344 | int de_mode; |
384 | int de_mode; |
| 345 | eth_stat_t de_stat; |
385 | eth_stat_t de_stat; |
| 346 | iovec_dat_t de_read_iovec; |
386 | iovec_dat_t de_read_iovec; |
| 347 | // iovec_dat_s_t de_read_iovec_s; |
387 | // iovec_dat_s_t de_read_iovec_s; |
| 348 | // int de_safecopy_read; |
388 | // int de_safecopy_read; |
| 349 | iovec_dat_t de_write_iovec; |
389 | iovec_dat_t de_write_iovec; |
| 350 | // iovec_dat_s_t de_write_iovec_s; |
390 | // iovec_dat_s_t de_write_iovec_s; |
| 351 | iovec_dat_t de_tmp_iovec; |
391 | iovec_dat_t de_tmp_iovec; |
| 352 | // iovec_dat_s_t de_tmp_iovec_s; |
392 | // iovec_dat_s_t de_tmp_iovec_s; |
| 353 | vir_bytes de_read_s; |
393 | vir_bytes de_read_s; |
| 354 | // int de_client; |
394 | // int de_client; |
| 355 | // message de_sendmsg; |
395 | // message de_sendmsg; |
| 356 | dp_user2nicf_t de_user2nicf; |
396 | dp_user2nicf_t de_user2nicf; |
| 357 | // dp_user2nicf_s_t de_user2nicf_s; |
397 | // dp_user2nicf_s_t de_user2nicf_s; |
| 358 | dp_nic2userf_t de_nic2userf; |
398 | dp_nic2userf_t de_nic2userf; |
| 359 | // dp_nic2userf_s_t de_nic2userf_s; |
399 | // dp_nic2userf_s_t de_nic2userf_s; |
| 360 | dp_getblock_t de_getblockf; |
400 | dp_getblock_t de_getblockf; |
| 361 | } dpeth_t; |
401 | } dpeth_t; |
| 362 | 402 | ||
| 363 | #define DEI_DEFAULT 0x8000 |
403 | #define DEI_DEFAULT 0x8000 |
| 364 | 404 | ||
| 365 | #define DEF_EMPTY 0x000 |
405 | #define DEF_EMPTY 0x000 |
| 366 | #define DEF_PACK_SEND 0x001 |
406 | #define DEF_PACK_SEND 0x001 |
| 367 | #define DEF_PACK_RECV 0x002 |
407 | #define DEF_PACK_RECV 0x002 |
| 368 | #define DEF_SEND_AVAIL 0x004 |
408 | #define DEF_SEND_AVAIL 0x004 |
| 369 | #define DEF_READING 0x010 |
409 | #define DEF_READING 0x010 |
| 370 | #define DEF_PROMISC 0x040 |
410 | #define DEF_PROMISC 0x040 |
| 371 | #define DEF_MULTI 0x080 |
411 | #define DEF_MULTI 0x080 |
| 372 | #define DEF_BROAD 0x100 |
412 | #define DEF_BROAD 0x100 |
| 373 | #define DEF_ENABLED 0x200 |
413 | #define DEF_ENABLED 0x200 |
| 374 | #define DEF_STOPPED 0x400 |
414 | #define DEF_STOPPED 0x400 |
| 375 | 415 | ||
| 376 | #define DEM_DISABLED 0x0 |
416 | #define DEM_DISABLED 0x0 |
| 377 | #define DEM_SINK 0x1 |
417 | #define DEM_SINK 0x1 |
| 378 | #define DEM_ENABLED 0x2 |
418 | #define DEM_ENABLED 0x2 |
| 379 | 419 | ||
| 380 | //#if !__minix_vmd |
420 | //#if !__minix_vmd |
| 381 | #define debug 1 /* Standard Minix lacks debug variable */ |
421 | #define debug 1 /* Standard Minix lacks debug variable */ |
| 382 | //#endif |
422 | //#endif |
| 383 | 423 | ||
| 384 | /* |
424 | /* |
| 385 | * $PchId: dp8390.h,v 1.10 2005/02/10 17:26:06 philip Exp $ |
425 | * $PchId: dp8390.h,v 1.10 2005/02/10 17:26:06 philip Exp $ |
| 386 | */ |
426 | */ |
| 387 | 427 | ||
| 388 | #endif |
428 | #endif |
| 389 | 429 | ||
| 390 | /** @} |
430 | /** @} |
| 391 | */ |
431 | */ |
| 392 | 432 | ||