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/*
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/*
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 * Copyright (c) 1987,1997, 2006, Vrije Universiteit, Amsterdam, The Netherlands All rights reserved. Redistribution and use of the MINIX 3 operating system in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
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 * Copyright (c) 1987,1997, 2006, Vrije Universiteit, Amsterdam, The Netherlands All rights reserved. Redistribution and use of the MINIX 3 operating system in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
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 *
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 *
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 * * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
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 * * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
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 * * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
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 * * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
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 * * Neither the name of the Vrije Universiteit nor the names of the software authors or contributors may be used to endorse or promote products derived from this software without specific prior written permission.
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 * * Neither the name of the Vrije Universiteit nor the names of the software authors or contributors may be used to endorse or promote products derived from this software without specific prior written permission.
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 * * Any deviations from these conditions require written permission from the copyright holder in advance
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 * * Any deviations from these conditions require written permission from the copyright holder in advance
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 *
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 *
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 *
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 *
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 * Disclaimer
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 * Disclaimer
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 *
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS, AUTHORS, AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR
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 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS, AUTHORS, AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR ANY AUTHORS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR ANY AUTHORS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 *
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 *
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 * Changes:
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 * Changes:
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 *  2009 Lukas Mejdrech ported to HelenOS
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 *  2009 Lukas Mejdrech ported to HelenOS
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 */
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 */
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/** @addtogroup dp8390
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/** @addtogroup dp8390
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 *  @{
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 *  @{
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 */
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 */
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30
 
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/** @file
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/** @file
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 *  \todo
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 *  \todo
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 */
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 */
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34
 
35
#ifndef __NET_NETIF_DP8390_H__
35
#ifndef __NET_NETIF_DP8390_H__
36
#define __NET_NETIF_DP8390_H__
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#define __NET_NETIF_DP8390_H__
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37
 
38
#include "../../structures/packet/packet.h"
38
#include "../../structures/packet/packet.h"
39
 
39
 
40
#include "dp8390_port.h"
40
#include "dp8390_port.h"
41
#include "local.h"
41
#include "local.h"
42
 
42
 
43
#define DP8390_IO_SIZE  0x01f
43
#define DP8390_IO_SIZE  0x01f
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44
 
45
/*
45
/*
46
dp8390.h
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dp8390.h
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47
 
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Created:    before Dec 28, 1992 by Philip Homburg
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Created:    before Dec 28, 1992 by Philip Homburg
49
*/
49
*/
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50
 
51
/* National Semiconductor DP8390 Network Interface Controller. */
51
/* National Semiconductor DP8390 Network Interface Controller. */
52
 
52
 
53
                /* Page 0, for reading ------------- */
53
                /* Page 0, for reading ------------- */
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#define DP_CR       0x0 /* Read side of Command Register     */
54
#define DP_CR       0x0 /* Read side of Command Register     */
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#define DP_CLDA0    0x1 /* Current Local Dma Address 0       */
55
#define DP_CLDA0    0x1 /* Current Local Dma Address 0       */
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#define DP_CLDA1    0x2 /* Current Local Dma Address 1       */
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#define DP_CLDA1    0x2 /* Current Local Dma Address 1       */
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#define DP_BNRY     0x3 /* Boundary Pointer                  */
57
#define DP_BNRY     0x3 /* Boundary Pointer                  */
58
#define DP_TSR      0x4 /* Transmit Status Register          */
58
#define DP_TSR      0x4 /* Transmit Status Register          */
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#define DP_NCR      0x5 /* Number of Collisions Register     */
59
#define DP_NCR      0x5 /* Number of Collisions Register     */
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#define DP_FIFO     0x6 /* Fifo ??                           */
60
#define DP_FIFO     0x6 /* Fifo ??                           */
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#define DP_ISR      0x7 /* Interrupt Status Register         */
61
#define DP_ISR      0x7 /* Interrupt Status Register         */
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#define DP_CRDA0    0x8 /* Current Remote Dma Address 0      */
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#define DP_CRDA0    0x8 /* Current Remote Dma Address 0      */
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#define DP_CRDA1    0x9 /* Current Remote Dma Address 1      */
63
#define DP_CRDA1    0x9 /* Current Remote Dma Address 1      */
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#define DP_DUM1     0xA /* unused                            */
64
#define DP_DUM1     0xA /* unused                            */
65
#define DP_DUM2     0xB /* unused                            */
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#define DP_DUM2     0xB /* unused                            */
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#define DP_RSR      0xC /* Receive Status Register           */
66
#define DP_RSR      0xC /* Receive Status Register           */
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#define DP_CNTR0    0xD /* Tally Counter 0                   */
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#define DP_CNTR0    0xD /* Tally Counter 0                   */
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#define DP_CNTR1    0xE /* Tally Counter 1                   */
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#define DP_CNTR1    0xE /* Tally Counter 1                   */
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#define DP_CNTR2    0xF /* Tally Counter 2                   */
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#define DP_CNTR2    0xF /* Tally Counter 2                   */
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70
 
71
                /* Page 0, for writing ------------- */
71
                /* Page 0, for writing ------------- */
72
#define DP_CR       0x0 /* Write side of Command Register    */
72
#define DP_CR       0x0 /* Write side of Command Register    */
73
#define DP_PSTART   0x1 /* Page Start Register               */
73
#define DP_PSTART   0x1 /* Page Start Register               */
74
#define DP_PSTOP    0x2 /* Page Stop Register                */
74
#define DP_PSTOP    0x2 /* Page Stop Register                */
75
#define DP_BNRY     0x3 /* Boundary Pointer                  */
75
#define DP_BNRY     0x3 /* Boundary Pointer                  */
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#define DP_TPSR     0x4 /* Transmit Page Start Register      */
76
#define DP_TPSR     0x4 /* Transmit Page Start Register      */
77
#define DP_TBCR0    0x5 /* Transmit Byte Count Register 0    */
77
#define DP_TBCR0    0x5 /* Transmit Byte Count Register 0    */
78
#define DP_TBCR1    0x6 /* Transmit Byte Count Register 1    */
78
#define DP_TBCR1    0x6 /* Transmit Byte Count Register 1    */
79
#define DP_ISR      0x7 /* Interrupt Status Register         */
79
#define DP_ISR      0x7 /* Interrupt Status Register         */
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#define DP_RSAR0    0x8 /* Remote Start Address Register 0   */
80
#define DP_RSAR0    0x8 /* Remote Start Address Register 0   */
81
#define DP_RSAR1    0x9 /* Remote Start Address Register 1   */
81
#define DP_RSAR1    0x9 /* Remote Start Address Register 1   */
82
#define DP_RBCR0    0xA /* Remote Byte Count Register 0      */
82
#define DP_RBCR0    0xA /* Remote Byte Count Register 0      */
83
#define DP_RBCR1    0xB /* Remote Byte Count Register 1      */
83
#define DP_RBCR1    0xB /* Remote Byte Count Register 1      */
84
#define DP_RCR      0xC /* Receive Configuration Register    */
84
#define DP_RCR      0xC /* Receive Configuration Register    */
85
#define DP_TCR      0xD /* Transmit Configuration Register   */
85
#define DP_TCR      0xD /* Transmit Configuration Register   */
86
#define DP_DCR      0xE /* Data Configuration Register       */
86
#define DP_DCR      0xE /* Data Configuration Register       */
87
#define DP_IMR      0xF /* Interrupt Mask Register           */
87
#define DP_IMR      0xF /* Interrupt Mask Register           */
88
 
88
 
89
                /* Page 1, read/write -------------- */
89
                /* Page 1, read/write -------------- */
90
#define DP_CR       0x0 /* Command Register                  */
90
#define DP_CR       0x0 /* Command Register                  */
91
#define DP_PAR0     0x1 /* Physical Address Register 0       */
91
#define DP_PAR0     0x1 /* Physical Address Register 0       */
92
#define DP_PAR1     0x2 /* Physical Address Register 1       */
92
#define DP_PAR1     0x2 /* Physical Address Register 1       */
93
#define DP_PAR2     0x3 /* Physical Address Register 2       */
93
#define DP_PAR2     0x3 /* Physical Address Register 2       */
94
#define DP_PAR3     0x4 /* Physical Address Register 3       */
94
#define DP_PAR3     0x4 /* Physical Address Register 3       */
95
#define DP_PAR4     0x5 /* Physical Address Register 4       */
95
#define DP_PAR4     0x5 /* Physical Address Register 4       */
96
#define DP_PAR5     0x6 /* Physical Address Register 5       */
96
#define DP_PAR5     0x6 /* Physical Address Register 5       */
97
#define DP_CURR     0x7 /* Current Page Register             */
97
#define DP_CURR     0x7 /* Current Page Register             */
98
#define DP_MAR0     0x8 /* Multicast Address Register 0      */
98
#define DP_MAR0     0x8 /* Multicast Address Register 0      */
99
#define DP_MAR1     0x9 /* Multicast Address Register 1      */
99
#define DP_MAR1     0x9 /* Multicast Address Register 1      */
100
#define DP_MAR2     0xA /* Multicast Address Register 2      */
100
#define DP_MAR2     0xA /* Multicast Address Register 2      */
101
#define DP_MAR3     0xB /* Multicast Address Register 3      */
101
#define DP_MAR3     0xB /* Multicast Address Register 3      */
102
#define DP_MAR4     0xC /* Multicast Address Register 4      */
102
#define DP_MAR4     0xC /* Multicast Address Register 4      */
103
#define DP_MAR5     0xD /* Multicast Address Register 5      */
103
#define DP_MAR5     0xD /* Multicast Address Register 5      */
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#define DP_MAR6     0xE /* Multicast Address Register 6      */
104
#define DP_MAR6     0xE /* Multicast Address Register 6      */
105
#define DP_MAR7     0xF /* Multicast Address Register 7      */
105
#define DP_MAR7     0xF /* Multicast Address Register 7      */
106
 
106
 
107
/* Bits in dp_cr */
107
/* Bits in dp_cr */
108
#define CR_STP      0x01    /* Stop: software reset              */
108
#define CR_STP      0x01    /* Stop: software reset              */
109
#define CR_STA      0x02    /* Start: activate NIC               */
109
#define CR_STA      0x02    /* Start: activate NIC               */
110
#define CR_TXP      0x04    /* Transmit Packet                   */
110
#define CR_TXP      0x04    /* Transmit Packet                   */
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#define CR_DMA      0x38    /* Mask for DMA control              */
111
#define CR_DMA      0x38    /* Mask for DMA control              */
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#define CR_DM_NOP   0x00    /* DMA: No Operation                 */
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#define CR_DM_NOP   0x00    /* DMA: No Operation                 */
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#define CR_DM_RR    0x08    /* DMA: Remote Read                  */
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#define CR_DM_RR    0x08    /* DMA: Remote Read                  */
114
#define CR_DM_RW    0x10    /* DMA: Remote Write                 */
114
#define CR_DM_RW    0x10    /* DMA: Remote Write                 */
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#define CR_DM_SP    0x18    /* DMA: Send Packet                  */
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#define CR_DM_SP    0x18    /* DMA: Send Packet                  */
116
#define CR_DM_ABORT 0x20    /* DMA: Abort Remote DMA Operation   */
116
#define CR_DM_ABORT 0x20    /* DMA: Abort Remote DMA Operation   */
117
#define CR_PS       0xC0    /* Mask for Page Select              */
117
#define CR_PS       0xC0    /* Mask for Page Select              */
118
#define CR_PS_P0    0x00    /* Register Page 0                   */
118
#define CR_PS_P0    0x00    /* Register Page 0                   */
119
#define CR_PS_P1    0x40    /* Register Page 1                   */
119
#define CR_PS_P1    0x40    /* Register Page 1                   */
120
#define CR_PS_P2    0x80    /* Register Page 2                   */
120
#define CR_PS_P2    0x80    /* Register Page 2                   */
121
#define CR_PS_T1    0xC0    /* Test Mode Register Map            */
121
#define CR_PS_T1    0xC0    /* Test Mode Register Map            */
122
 
122
 
123
/* Bits in dp_isr */
123
/* Bits in dp_isr */
124
#define ISR_PRX     0x01    /* Packet Received with no errors    */
124
#define ISR_PRX     0x01    /* Packet Received with no errors    */
125
#define ISR_PTX     0x02    /* Packet Transmitted with no errors */
125
#define ISR_PTX     0x02    /* Packet Transmitted with no errors */
126
#define ISR_RXE     0x04    /* Receive Error                     */
126
#define ISR_RXE     0x04    /* Receive Error                     */
127
#define ISR_TXE     0x08    /* Transmit Error                    */
127
#define ISR_TXE     0x08    /* Transmit Error                    */
128
#define ISR_OVW     0x10    /* Overwrite Warning                 */
128
#define ISR_OVW     0x10    /* Overwrite Warning                 */
129
#define ISR_CNT     0x20    /* Counter Overflow                  */
129
#define ISR_CNT     0x20    /* Counter Overflow                  */
130
#define ISR_RDC     0x40    /* Remote DMA Complete               */
130
#define ISR_RDC     0x40    /* Remote DMA Complete               */
131
#define ISR_RST     0x80    /* Reset Status                      */
131
#define ISR_RST     0x80    /* Reset Status                      */
132
 
132
 
133
/* Bits in dp_imr */
133
/* Bits in dp_imr */
134
#define IMR_PRXE    0x01    /* Packet Received iEnable           */
134
#define IMR_PRXE    0x01    /* Packet Received iEnable           */
135
#define IMR_PTXE    0x02    /* Packet Transmitted iEnable        */
135
#define IMR_PTXE    0x02    /* Packet Transmitted iEnable        */
136
#define IMR_RXEE    0x04    /* Receive Error iEnable             */
136
#define IMR_RXEE    0x04    /* Receive Error iEnable             */
137
#define IMR_TXEE    0x08    /* Transmit Error iEnable            */
137
#define IMR_TXEE    0x08    /* Transmit Error iEnable            */
138
#define IMR_OVWE    0x10    /* Overwrite Warning iEnable         */
138
#define IMR_OVWE    0x10    /* Overwrite Warning iEnable         */
139
#define IMR_CNTE    0x20    /* Counter Overflow iEnable          */
139
#define IMR_CNTE    0x20    /* Counter Overflow iEnable          */
140
#define IMR_RDCE    0x40    /* DMA Complete iEnable              */
140
#define IMR_RDCE    0x40    /* DMA Complete iEnable              */
141
 
141
 
142
/* Bits in dp_dcr */
142
/* Bits in dp_dcr */
143
#define DCR_WTS     0x01    /* Word Transfer Select              */
143
#define DCR_WTS     0x01    /* Word Transfer Select              */
144
#define DCR_BYTEWIDE    0x00    /* WTS: byte wide transfers          */
144
#define DCR_BYTEWIDE    0x00    /* WTS: byte wide transfers          */
145
#define DCR_WORDWIDE    0x01    /* WTS: word wide transfers          */
145
#define DCR_WORDWIDE    0x01    /* WTS: word wide transfers          */
146
#define DCR_BOS     0x02    /* Byte Order Select                 */
146
#define DCR_BOS     0x02    /* Byte Order Select                 */
147
#define DCR_LTLENDIAN   0x00    /* BOS: Little Endian                */
147
#define DCR_LTLENDIAN   0x00    /* BOS: Little Endian                */
148
#define DCR_BIGENDIAN   0x02    /* BOS: Big Endian                   */
148
#define DCR_BIGENDIAN   0x02    /* BOS: Big Endian                   */
149
#define DCR_LAS     0x04    /* Long Address Select               */
149
#define DCR_LAS     0x04    /* Long Address Select               */
150
#define DCR_BMS     0x08    /* Burst Mode Select
150
#define DCR_BMS     0x08    /* Burst Mode Select
151
                 * Called Loopback Select (LS) in
151
                 * Called Loopback Select (LS) in
152
                 * later manuals. Should be set.     */
152
                 * later manuals. Should be set.     */
153
#define DCR_AR      0x10    /* Autoinitialize Remote             */
153
#define DCR_AR      0x10    /* Autoinitialize Remote             */
154
#define DCR_FTS     0x60    /* Fifo Threshold Select             */
154
#define DCR_FTS     0x60    /* Fifo Threshold Select             */
155
#define DCR_2BYTES  0x00    /* 2 bytes                           */
155
#define DCR_2BYTES  0x00    /* 2 bytes                           */
156
#define DCR_4BYTES  0x40    /* 4 bytes                           */
156
#define DCR_4BYTES  0x40    /* 4 bytes                           */
157
#define DCR_8BYTES  0x20    /* 8 bytes                           */
157
#define DCR_8BYTES  0x20    /* 8 bytes                           */
158
#define DCR_12BYTES 0x60    /* 12 bytes                          */
158
#define DCR_12BYTES 0x60    /* 12 bytes                          */
159
 
159
 
160
/* Bits in dp_tcr */
160
/* Bits in dp_tcr */
161
#define TCR_CRC     0x01    /* Inhibit CRC                       */
161
#define TCR_CRC     0x01    /* Inhibit CRC                       */
162
#define TCR_ELC     0x06    /* Encoded Loopback Control          */
162
#define TCR_ELC     0x06    /* Encoded Loopback Control          */
163
#define TCR_NORMAL  0x00    /* ELC: Normal Operation             */
163
#define TCR_NORMAL  0x00    /* ELC: Normal Operation             */
164
#define TCR_INTERNAL    0x02    /* ELC: Internal Loopback            */
164
#define TCR_INTERNAL    0x02    /* ELC: Internal Loopback            */
165
#define TCR_0EXTERNAL   0x04    /* ELC: External Loopback LPBK=0     */
165
#define TCR_0EXTERNAL   0x04    /* ELC: External Loopback LPBK=0     */
166
#define TCR_1EXTERNAL   0x06    /* ELC: External Loopback LPBK=1     */
166
#define TCR_1EXTERNAL   0x06    /* ELC: External Loopback LPBK=1     */
167
#define TCR_ATD     0x08    /* Auto Transmit Disable             */
167
#define TCR_ATD     0x08    /* Auto Transmit Disable             */
168
#define TCR_OFST    0x10    /* Collision Offset Enable (be nice) */
168
#define TCR_OFST    0x10    /* Collision Offset Enable (be nice) */
169
 
169
 
170
/* Bits in dp_tsr */
170
/* Bits in dp_tsr */
171
#define TSR_PTX     0x01    /* Packet Transmitted (without error)*/
171
#define TSR_PTX     0x01    /* Packet Transmitted (without error)*/
172
#define TSR_DFR     0x02    /* Transmit Deferred, reserved in
172
#define TSR_DFR     0x02    /* Transmit Deferred, reserved in
173
                 * later manuals.            */
173
                 * later manuals.            */
174
#define TSR_COL     0x04    /* Transmit Collided                 */
174
#define TSR_COL     0x04    /* Transmit Collided                 */
175
#define TSR_ABT     0x08    /* Transmit Aborted                  */
175
#define TSR_ABT     0x08    /* Transmit Aborted                  */
176
#define TSR_CRS     0x10    /* Carrier Sense Lost                */
176
#define TSR_CRS     0x10    /* Carrier Sense Lost                */
177
#define TSR_FU      0x20    /* FIFO Underrun                     */
177
#define TSR_FU      0x20    /* FIFO Underrun                     */
178
#define TSR_CDH     0x40    /* CD Heartbeat                      */
178
#define TSR_CDH     0x40    /* CD Heartbeat                      */
179
#define TSR_OWC     0x80    /* Out of Window Collision           */
179
#define TSR_OWC     0x80    /* Out of Window Collision           */
180
 
180
 
181
/* Bits in tp_rcr */
181
/* Bits in tp_rcr */
182
#define RCR_SEP     0x01    /* Save Errored Packets              */
182
#define RCR_SEP     0x01    /* Save Errored Packets              */
183
#define RCR_AR      0x02    /* Accept Runt Packets               */
183
#define RCR_AR      0x02    /* Accept Runt Packets               */
184
#define RCR_AB      0x04    /* Accept Broadcast                  */
184
#define RCR_AB      0x04    /* Accept Broadcast                  */
185
#define RCR_AM      0x08    /* Accept Multicast                  */
185
#define RCR_AM      0x08    /* Accept Multicast                  */
186
#define RCR_PRO     0x10    /* Physical Promiscuous              */
186
#define RCR_PRO     0x10    /* Physical Promiscuous              */
187
#define RCR_MON     0x20    /* Monitor Mode                      */
187
#define RCR_MON     0x20    /* Monitor Mode                      */
188
 
188
 
189
/* Bits in dp_rsr */
189
/* Bits in dp_rsr */
190
#define RSR_PRX     0x01    /* Packet Received Intact            */
190
#define RSR_PRX     0x01    /* Packet Received Intact            */
191
#define RSR_CRC     0x02    /* CRC Error                         */
191
#define RSR_CRC     0x02    /* CRC Error                         */
192
#define RSR_FAE     0x04    /* Frame Alignment Error             */
192
#define RSR_FAE     0x04    /* Frame Alignment Error             */
193
#define RSR_FO      0x08    /* FIFO Overrun                      */
193
#define RSR_FO      0x08    /* FIFO Overrun                      */
194
#define RSR_MPA     0x10    /* Missed Packet                     */
194
#define RSR_MPA     0x10    /* Missed Packet                     */
195
#define RSR_PHY     0x20    /* Multicast Address Match           */
195
#define RSR_PHY     0x20    /* Multicast Address Match           */
196
#define RSR_DIS     0x40    /* Receiver Disabled                 */
196
#define RSR_DIS     0x40    /* Receiver Disabled                 */
197
#define RSR_DFR     0x80    /* In later manuals: Deferring       */
197
#define RSR_DFR     0x80    /* In later manuals: Deferring       */
198
 
198
 
199
 
199
 
200
typedef struct dp_rcvhdr
200
typedef struct dp_rcvhdr
201
{
201
{
202
    u8_t dr_status;         /* Copy of rsr                       */
202
    u8_t dr_status;         /* Copy of rsr                       */
203
    u8_t dr_next;           /* Pointer to next packet            */
203
    u8_t dr_next;           /* Pointer to next packet            */
204
    u8_t dr_rbcl;           /* Receive Byte Count Low            */
204
    u8_t dr_rbcl;           /* Receive Byte Count Low            */
205
    u8_t dr_rbch;           /* Receive Byte Count High           */
205
    u8_t dr_rbch;           /* Receive Byte Count High           */
206
} dp_rcvhdr_t;
206
} dp_rcvhdr_t;
207
 
207
 
208
#define DP_PAGESIZE 256
208
#define DP_PAGESIZE 256
209
 
209
 
210
/* Some macros to simplify accessing the dp8390 */
210
/* Some macros to simplify accessing the dp8390 */
211
#define inb_reg0(dep, reg)      (inb(dep->de_dp8390_port+reg))
211
#define inb_reg0(dep, reg)      (inb(dep->de_dp8390_port+reg))
212
#define outb_reg0(dep, reg, data)   (outb(dep->de_dp8390_port+reg, data))
212
#define outb_reg0(dep, reg, data)   (outb(dep->de_dp8390_port+reg, data))
213
#define inb_reg1(dep, reg)      (inb(dep->de_dp8390_port+reg))
213
#define inb_reg1(dep, reg)      (inb(dep->de_dp8390_port+reg))
214
#define outb_reg1(dep, reg, data)   (outb(dep->de_dp8390_port+reg, data))
214
#define outb_reg1(dep, reg, data)   (outb(dep->de_dp8390_port+reg, data))
215
 
215
 
216
/* Software interface to the dp8390 driver */
216
/* Software interface to the dp8390 driver */
217
 
217
 
218
struct dpeth;
218
struct dpeth;
219
struct iovec_dat;
219
struct iovec_dat;
220
//struct iovec_dat_s;
220
//struct iovec_dat_s;
221
_PROTOTYPE( typedef void (*dp_initf_t), (struct dpeth *dep)     );
221
_PROTOTYPE( typedef void (*dp_initf_t), (struct dpeth *dep)     );
222
_PROTOTYPE( typedef void (*dp_stopf_t), (struct dpeth *dep)     );
222
_PROTOTYPE( typedef void (*dp_stopf_t), (struct dpeth *dep)     );
223
_PROTOTYPE( typedef void (*dp_user2nicf_t), (struct dpeth *dep,
223
_PROTOTYPE( typedef void (*dp_user2nicf_t), (struct dpeth *dep,
224
            struct iovec_dat *iovp, vir_bytes offset,
224
            struct iovec_dat *iovp, vir_bytes offset,
225
            int nic_addr, vir_bytes count)          );
225
            int nic_addr, vir_bytes count)          );
226
//_PROTOTYPE( typedef void (*dp_user2nicf_s_t), (struct dpeth *dep,
226
//_PROTOTYPE( typedef void (*dp_user2nicf_s_t), (struct dpeth *dep,
227
//          struct iovec_dat_s *iovp, vir_bytes offset,
227
//          struct iovec_dat_s *iovp, vir_bytes offset,
228
//          int nic_addr, vir_bytes count)          );
228
//          int nic_addr, vir_bytes count)          );
229
_PROTOTYPE( typedef void (*dp_nic2userf_t), (struct dpeth *dep,
229
_PROTOTYPE( typedef void (*dp_nic2userf_t), (struct dpeth *dep,
230
            int nic_addr, struct iovec_dat *iovp,
230
            int nic_addr, struct iovec_dat *iovp,
231
            vir_bytes offset, vir_bytes count)      );
231
            vir_bytes offset, vir_bytes count)      );
232
//_PROTOTYPE( typedef void (*dp_nic2userf_s_t), (struct dpeth *dep,
232
//_PROTOTYPE( typedef void (*dp_nic2userf_s_t), (struct dpeth *dep,
233
//          int nic_addr, struct iovec_dat_s *iovp,
233
//          int nic_addr, struct iovec_dat_s *iovp,
234
//          vir_bytes offset, vir_bytes count)      );
234
//          vir_bytes offset, vir_bytes count)      );
235
//#if 0
235
//#if 0
236
//_PROTOTYPE( typedef void (*dp_getheaderf_t), (struct dpeth *dep,
236
//_PROTOTYPE( typedef void (*dp_getheaderf_t), (struct dpeth *dep,
237
//          int page, struct dp_rcvhdr *h, u16_t *eth_type) );
237
//          int page, struct dp_rcvhdr *h, u16_t *eth_type) );
238
//#endif
238
//#endif
239
_PROTOTYPE( typedef void (*dp_getblock_t), (struct dpeth *dep,
239
_PROTOTYPE( typedef void (*dp_getblock_t), (struct dpeth *dep,
240
        int page, size_t offset, size_t size, void *dst)    );
240
        int page, size_t offset, size_t size, void *dst)    );
241
 
241
 
242
/* iovectors are handled IOVEC_NR entries at a time. */
242
/* iovectors are handled IOVEC_NR entries at a time. */
243
//#define IOVEC_NR  16
243
//#define IOVEC_NR  16
244
// no vectors allowed
244
// no vectors allowed
245
#define IOVEC_NR    1
245
#define IOVEC_NR    1
246
 
246
 
247
/*
247
/*
248
typedef int irq_hook_t;
248
typedef int irq_hook_t;
249
*/
249
*/
250
typedef struct iovec_dat
250
typedef struct iovec_dat
251
{
251
{
252
  iovec_t iod_iovec[IOVEC_NR];
252
  iovec_t iod_iovec[IOVEC_NR];
253
  int iod_iovec_s;
253
  int iod_iovec_s;
254
  // no direct process access
254
  // no direct process access
255
  int iod_proc_nr;
255
  int iod_proc_nr;
256
  vir_bytes iod_iovec_addr;
256
  vir_bytes iod_iovec_addr;
257
} iovec_dat_t;
257
} iovec_dat_t;
258
/*
258
/*
259
typedef struct iovec_dat_s
259
typedef struct iovec_dat_s
260
{
260
{
261
  iovec_s_t iod_iovec[IOVEC_NR];
261
  iovec_s_t iod_iovec[IOVEC_NR];
262
  int iod_iovec_s;
262
  int iod_iovec_s;
263
  int iod_proc_nr;
263
  int iod_proc_nr;
264
  cp_grant_id_t iod_grant;
264
  cp_grant_id_t iod_grant;
265
  vir_bytes iod_iovec_offset;
265
  vir_bytes iod_iovec_offset;
266
} iovec_dat_s_t;
266
} iovec_dat_s_t;
267
*/
267
*/
268
#define SENDQ_NR    1   /* Maximum size of the send queue */
268
#define SENDQ_NR    1   /* Maximum size of the send queue */
269
#define SENDQ_PAGES 6   /* 6 * DP_PAGESIZE >= 1514 bytes */
269
#define SENDQ_PAGES 6   /* 6 * DP_PAGESIZE >= 1514 bytes */
270
 
270
 
-
 
271
/** Maximum number of waiting packets to be sent or received.
-
 
272
 */
-
 
273
#define MAX_PACKETS 4
-
 
274
 
271
typedef struct dpeth
275
typedef struct dpeth
272
{
276
{
273
    /* Packet send queue.
277
    /* Packet send queue.
274
    */
278
    */
275
    packet_t    packet_queue;
279
    packet_t    packet_queue;
276
    int         packet_count;
280
    int         packet_count;
277
 
281
 
278
    /* Packet receive queue.
282
    /* Packet receive queue.
279
    */
283
    */
280
    packet_t    received_queue;
284
    packet_t    received_queue;
-
 
285
    int         received_count;
281
 
286
 
282
    /* The de_base_port field is the starting point of the probe.
287
    /* The de_base_port field is the starting point of the probe.
283
     * The conf routine also fills de_linmem and de_irq. If the probe
288
     * The conf routine also fills de_linmem and de_irq. If the probe
284
     * routine knows the irq and/or memory address because they are
289
     * routine knows the irq and/or memory address because they are
285
     * hardwired in the board, the probe should modify these fields.
290
     * hardwired in the board, the probe should modify these fields.
286
     * Futhermore, the probe routine should also fill in de_initf and
291
     * Futhermore, the probe routine should also fill in de_initf and
287
     * de_stopf fields with the appropriate function pointers and set
292
     * de_stopf fields with the appropriate function pointers and set
288
     * de_prog_IO iff programmed I/O is to be used.
293
     * de_prog_IO iff programmed I/O is to be used.
289
     */
294
     */
290
    port_t de_base_port;
295
    port_t de_base_port;
291
    phys_bytes de_linmem;
296
    phys_bytes de_linmem;
292
    char *de_locmem;
297
    char *de_locmem;
293
    int de_irq;
298
    int de_irq;
294
    int de_int_pending;
299
    int de_int_pending;
295
//  irq_hook_t de_hook;
300
//  irq_hook_t de_hook;
296
    dp_initf_t de_initf;
301
    dp_initf_t de_initf;
297
    dp_stopf_t de_stopf;
302
    dp_stopf_t de_stopf;
298
    int de_prog_IO;
303
    int de_prog_IO;
299
    char de_name[sizeof("dp8390#n")];
304
    char de_name[sizeof("dp8390#n")];
300
 
305
 
301
    /* The initf function fills the following fields. Only cards that do
306
    /* The initf function fills the following fields. Only cards that do
302
     * programmed I/O fill in the de_pata_port field.
307
     * programmed I/O fill in the de_pata_port field.
303
     * In addition, the init routine has to fill in the sendq data
308
     * In addition, the init routine has to fill in the sendq data
304
     * structures.
309
     * structures.
305
     */
310
     */
306
    ether_addr_t de_address;
311
    ether_addr_t de_address;
307
    port_t de_dp8390_port;
312
    port_t de_dp8390_port;
308
    port_t de_data_port;
313
    port_t de_data_port;
309
    int de_16bit;
314
    int de_16bit;
310
    int de_ramsize;
315
    int de_ramsize;
311
    int de_offset_page;
316
    int de_offset_page;
312
    int de_startpage;
317
    int de_startpage;
313
    int de_stoppage;
318
    int de_stoppage;
314
 
319
 
315
    /* should be here - read even for ne2k isa init... */
320
    /* should be here - read even for ne2k isa init... */
316
    char de_pci;            /* TRUE iff PCI device */
321
    char de_pci;            /* TRUE iff PCI device */
317
 
322
 
318
#if ENABLE_PCI
323
#if ENABLE_PCI
319
    /* PCI config */
324
    /* PCI config */
320
//  char de_pci;            /* TRUE iff PCI device */
325
//  char de_pci;            /* TRUE iff PCI device */
321
//  u8_t de_pcibus; 
326
//  u8_t de_pcibus; 
322
//  u8_t de_pcidev; 
327
//  u8_t de_pcidev; 
323
//  u8_t de_pcifunc;    
328
//  u8_t de_pcifunc;    
324
#endif
329
#endif
325
 
330
 
326
    /* Do it yourself send queue */
331
    /* Do it yourself send queue */
327
    struct sendq
332
    struct sendq
328
    {
333
    {
329
        int sq_filled;      /* this buffer contains a packet */
334
        int sq_filled;      /* this buffer contains a packet */
330
        int sq_size;        /* with this size */
335
        int sq_size;        /* with this size */
331
        int sq_sendpage;    /* starting page of the buffer */
336
        int sq_sendpage;    /* starting page of the buffer */
332
    } de_sendq[SENDQ_NR];
337
    } de_sendq[SENDQ_NR];
333
    int de_sendq_nr;
338
    int de_sendq_nr;
334
    int de_sendq_head;      /* Enqueue at the head */
339
    int de_sendq_head;      /* Enqueue at the head */
335
    int de_sendq_tail;      /* Dequeue at the tail */
340
    int de_sendq_tail;      /* Dequeue at the tail */
336
 
341
 
337
    /* Fields for internal use by the dp8390 driver. */
342
    /* Fields for internal use by the dp8390 driver. */
338
    int de_flags;
343
    int de_flags;
339
    int de_mode;
344
    int de_mode;
340
    eth_stat_t de_stat;
345
    eth_stat_t de_stat;
341
    iovec_dat_t de_read_iovec;
346
    iovec_dat_t de_read_iovec;
342
//  iovec_dat_s_t de_read_iovec_s;
347
//  iovec_dat_s_t de_read_iovec_s;
343
//  int de_safecopy_read;
348
//  int de_safecopy_read;
344
    iovec_dat_t de_write_iovec;
349
    iovec_dat_t de_write_iovec;
345
//  iovec_dat_s_t de_write_iovec_s;
350
//  iovec_dat_s_t de_write_iovec_s;
346
    iovec_dat_t de_tmp_iovec;
351
    iovec_dat_t de_tmp_iovec;
347
//  iovec_dat_s_t de_tmp_iovec_s;
352
//  iovec_dat_s_t de_tmp_iovec_s;
348
    vir_bytes de_read_s;
353
    vir_bytes de_read_s;
349
//  int de_client;
354
//  int de_client;
350
//  message de_sendmsg;
355
//  message de_sendmsg;
351
    dp_user2nicf_t de_user2nicf;
356
    dp_user2nicf_t de_user2nicf;
352
//  dp_user2nicf_s_t de_user2nicf_s; 
357
//  dp_user2nicf_s_t de_user2nicf_s; 
353
    dp_nic2userf_t de_nic2userf;
358
    dp_nic2userf_t de_nic2userf;
354
//  dp_nic2userf_s_t de_nic2userf_s; 
359
//  dp_nic2userf_s_t de_nic2userf_s; 
355
    dp_getblock_t de_getblockf;
360
    dp_getblock_t de_getblockf;
356
} dpeth_t;
361
} dpeth_t;
357
 
362
 
358
#define DEI_DEFAULT 0x8000
363
#define DEI_DEFAULT 0x8000
359
 
364
 
360
#define DEF_EMPTY   0x000
365
#define DEF_EMPTY   0x000
361
#define DEF_PACK_SEND   0x001
366
#define DEF_PACK_SEND   0x001
362
#define DEF_PACK_RECV   0x002
367
#define DEF_PACK_RECV   0x002
363
#define DEF_SEND_AVAIL  0x004
368
#define DEF_SEND_AVAIL  0x004
364
#define DEF_READING 0x010
369
#define DEF_READING 0x010
365
#define DEF_PROMISC 0x040
370
#define DEF_PROMISC 0x040
366
#define DEF_MULTI   0x080
371
#define DEF_MULTI   0x080
367
#define DEF_BROAD   0x100
372
#define DEF_BROAD   0x100
368
#define DEF_ENABLED 0x200
373
#define DEF_ENABLED 0x200
369
#define DEF_STOPPED 0x400
374
#define DEF_STOPPED 0x400
370
 
375
 
371
#define DEM_DISABLED    0x0
376
#define DEM_DISABLED    0x0
372
#define DEM_SINK    0x1
377
#define DEM_SINK    0x1
373
#define DEM_ENABLED 0x2
378
#define DEM_ENABLED 0x2
374
 
379
 
375
//#if !__minix_vmd
380
//#if !__minix_vmd
376
#define debug       1   /* Standard Minix lacks debug variable */
381
#define debug       1   /* Standard Minix lacks debug variable */
377
//#endif
382
//#endif
378
 
383
 
379
/*
384
/*
380
 * $PchId: dp8390.h,v 1.10 2005/02/10 17:26:06 philip Exp $
385
 * $PchId: dp8390.h,v 1.10 2005/02/10 17:26:06 philip Exp $
381
 */
386
 */
382
 
387
 
383
#endif
388
#endif
384
 
389
 
385
/** @}
390
/** @}
386
 */
391
 */
387
 
392