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Line 33... Line 33...
33
 */
33
 */
34
 
34
 
35
#ifndef KERN_sparc64_TLB_H_
35
#ifndef KERN_sparc64_TLB_H_
36
#define KERN_sparc64_TLB_H_
36
#define KERN_sparc64_TLB_H_
37
 
37
 
-
 
38
#if defined (US)
38
#define ITLB_ENTRY_COUNT        64
39
#define ITLB_ENTRY_COUNT        64
39
#define DTLB_ENTRY_COUNT        64
40
#define DTLB_ENTRY_COUNT        64
-
 
41
#define DTLB_MAX_LOCKED_ENTRIES     DTLB_ENTRY_COUNT
-
 
42
#endif
-
 
43
 
-
 
44
/** TLB_DSMALL is the only of the three DMMUs that can hold locked entries. */
-
 
45
#if defined (US3)
-
 
46
#define DTLB_MAX_LOCKED_ENTRIES     16
-
 
47
#endif
40
 
48
 
41
#define MEM_CONTEXT_KERNEL      0
49
#define MEM_CONTEXT_KERNEL      0
42
#define MEM_CONTEXT_TEMP        1
50
#define MEM_CONTEXT_TEMP        1
43
 
51
 
44
/** Page sizes. */
52
/** Page sizes. */
Line 51... Line 59...
51
#define KERNEL_PAGE_WIDTH       22  /* 4M */
59
#define KERNEL_PAGE_WIDTH       22  /* 4M */
52
 
60
 
53
/* TLB Demap Operation types. */
61
/* TLB Demap Operation types. */
54
#define TLB_DEMAP_PAGE      0
62
#define TLB_DEMAP_PAGE      0
55
#define TLB_DEMAP_CONTEXT   1
63
#define TLB_DEMAP_CONTEXT   1
-
 
64
#if defined (US3)
-
 
65
#define TLB_DEMAP_ALL       2
-
 
66
#endif
56
 
67
 
57
#define TLB_DEMAP_TYPE_SHIFT    6
68
#define TLB_DEMAP_TYPE_SHIFT    6
58
 
69
 
59
/* TLB Demap Operation Context register encodings. */
70
/* TLB Demap Operation Context register encodings. */
60
#define TLB_DEMAP_PRIMARY   0
71
#define TLB_DEMAP_PRIMARY   0
61
#define TLB_DEMAP_SECONDARY 1
72
#define TLB_DEMAP_SECONDARY 1
62
#define TLB_DEMAP_NUCLEUS   2
73
#define TLB_DEMAP_NUCLEUS   2
63
 
74
 
-
 
75
/* There are more TLBs in one MMU in US3, their codes are defined here. */
-
 
76
#if defined (US3)
-
 
77
/* D-MMU: one small (16-entry) TLB and two big (512-entry) TLBs */
-
 
78
#define TLB_DSMALL  0
-
 
79
#define TLB_DBIG_0  2
-
 
80
#define TLB_DBIG_1  3
-
 
81
   
-
 
82
/* I-MMU: one small (16-entry) TLB and one big TLB */
-
 
83
#define TLB_ISMALL  0
-
 
84
#define TLB_IBIG    2
-
 
85
#endif
-
 
86
 
64
#define TLB_DEMAP_CONTEXT_SHIFT 4
87
#define TLB_DEMAP_CONTEXT_SHIFT 4
65
 
88
 
66
/* TLB Tag Access shifts */
89
/* TLB Tag Access shifts */
67
#define TLB_TAG_ACCESS_CONTEXT_SHIFT    0
90
#define TLB_TAG_ACCESS_CONTEXT_SHIFT    0
68
#define TLB_TAG_ACCESS_CONTEXT_MASK ((1 << 13) - 1)
91
#define TLB_TAG_ACCESS_CONTEXT_MASK ((1 << 13) - 1)
Line 74... Line 97...
74
#include <arch/mm/mmu.h>
97
#include <arch/mm/mmu.h>
75
#include <arch/mm/page.h>
98
#include <arch/mm/page.h>
76
#include <arch/asm.h>
99
#include <arch/asm.h>
77
#include <arch/barrier.h>
100
#include <arch/barrier.h>
78
#include <arch/types.h>
101
#include <arch/types.h>
-
 
102
#include <arch/register.h>
-
 
103
#include <arch/cpu.h>
79
 
104
 
80
union tlb_context_reg {
105
union tlb_context_reg {
81
    uint64_t v;
106
    uint64_t v;
82
    struct {
107
    struct {
83
        unsigned long : 51;
108
        unsigned long : 51;
Line 88... Line 113...
88
 
113
 
89
/** I-/D-TLB Data In/Access Register type. */
114
/** I-/D-TLB Data In/Access Register type. */
90
typedef tte_data_t tlb_data_t;
115
typedef tte_data_t tlb_data_t;
91
 
116
 
92
/** I-/D-TLB Data Access Address in Alternate Space. */
117
/** I-/D-TLB Data Access Address in Alternate Space. */
-
 
118
 
-
 
119
#if defined (US)
-
 
120
 
93
union tlb_data_access_addr {
121
union tlb_data_access_addr {
94
    uint64_t value;
122
    uint64_t value;
95
    struct {
123
    struct {
96
        uint64_t : 55;
124
        uint64_t : 55;
97
        unsigned tlb_entry : 6;
125
        unsigned tlb_entry : 6;
98
        unsigned : 3;
126
        unsigned : 3;
99
    } __attribute__ ((packed));
127
    } __attribute__ ((packed));
100
};
128
};
101
typedef union tlb_data_access_addr tlb_data_access_addr_t;
129
typedef union tlb_data_access_addr dtlb_data_access_addr_t;
-
 
130
typedef union tlb_data_access_addr dtlb_tag_read_addr_t;
-
 
131
typedef union tlb_data_access_addr itlb_data_access_addr_t;
102
typedef union tlb_data_access_addr tlb_tag_read_addr_t;
132
typedef union tlb_data_access_addr itlb_tag_read_addr_t;
-
 
133
 
-
 
134
#elif defined (US3)
-
 
135
 
-
 
136
/*
-
 
137
 * In US3, I-MMU and D-MMU have different formats of the data
-
 
138
 * access register virtual address. In the corresponding
-
 
139
 * structures the member variable for the entry number is
-
 
140
 * called "local_tlb_entry" - it contrasts with the "tlb_entry"
-
 
141
 * for the US data access register VA structure. The rationale
-
 
142
 * behind this is to prevent careless mistakes in the code
-
 
143
 * caused by setting only the entry number and not the TLB
-
 
144
 * number in the US3 code (when taking the code from US).
-
 
145
 */
-
 
146
 
-
 
147
union dtlb_data_access_addr {
-
 
148
    uint64_t value;
-
 
149
    struct {
-
 
150
        uint64_t : 45;
-
 
151
        unsigned : 1;
-
 
152
        unsigned tlb_number : 2;
-
 
153
        unsigned : 4;
-
 
154
        unsigned local_tlb_entry : 9;
-
 
155
        unsigned : 3;
-
 
156
    } __attribute__ ((packed));
-
 
157
};
-
 
158
typedef union dtlb_data_access_addr dtlb_data_access_addr_t;
-
 
159
typedef union dtlb_data_access_addr dtlb_tag_read_addr_t;
-
 
160
 
-
 
161
union itlb_data_access_addr {
-
 
162
    uint64_t value;
-
 
163
    struct {
-
 
164
        uint64_t : 45;
-
 
165
        unsigned : 1;
-
 
166
        unsigned tlb_number : 2;
-
 
167
        unsigned : 6;
-
 
168
        unsigned local_tlb_entry : 7;
-
 
169
        unsigned : 3;
-
 
170
    } __attribute__ ((packed));
-
 
171
};
-
 
172
typedef union itlb_data_access_addr itlb_data_access_addr_t;
-
 
173
typedef union itlb_data_access_addr itlb_tag_read_addr_t;
-
 
174
 
-
 
175
#endif
103
 
176
 
104
/** I-/D-TLB Tag Read Register. */
177
/** I-/D-TLB Tag Read Register. */
105
union tlb_tag_read_reg {
178
union tlb_tag_read_reg {
106
    uint64_t value;
179
    uint64_t value;
107
    struct {
180
    struct {
Line 116... Line 189...
116
/** TLB Demap Operation Address. */
189
/** TLB Demap Operation Address. */
117
union tlb_demap_addr {
190
union tlb_demap_addr {
118
    uint64_t value;
191
    uint64_t value;
119
    struct {
192
    struct {
120
        uint64_t vpn: 51;   /**< Virtual Address bits 63:13. */
193
        uint64_t vpn: 51;   /**< Virtual Address bits 63:13. */
-
 
194
#if defined (US)
121
        unsigned : 6;       /**< Ignored. */
195
        unsigned : 6;       /**< Ignored. */
122
        unsigned type : 1;  /**< The type of demap operation. */
196
        unsigned type : 1;  /**< The type of demap operation. */
-
 
197
#elif defined (US3)
-
 
198
        unsigned : 5;       /**< Ignored. */
-
 
199
        unsigned type: 2;   /**< The type of demap operation. */
-
 
200
#endif
123
        unsigned context : 2;   /**< Context register selection. */
201
        unsigned context : 2;   /**< Context register selection. */
124
        unsigned : 4;       /**< Zero. */
202
        unsigned : 4;       /**< Zero. */
125
    } __attribute__ ((packed));
203
    } __attribute__ ((packed));
126
};
204
};
127
typedef union tlb_demap_addr tlb_demap_addr_t;
205
typedef union tlb_demap_addr tlb_demap_addr_t;
128
 
206
 
129
/** TLB Synchronous Fault Status Register. */
207
/** TLB Synchronous Fault Status Register. */
130
union tlb_sfsr_reg {
208
union tlb_sfsr_reg {
131
    uint64_t value;
209
    uint64_t value;
132
    struct {
210
    struct {
-
 
211
#if defined (US)
133
        unsigned long : 40; /**< Implementation dependent. */
212
        unsigned long : 40; /**< Implementation dependent. */
134
        unsigned asi : 8;   /**< ASI. */
213
        unsigned asi : 8;   /**< ASI. */
135
        unsigned : 2;
214
        unsigned : 2;
136
        unsigned ft : 7;    /**< Fault type. */
215
        unsigned ft : 7;    /**< Fault type. */
-
 
216
#elif defined (US3)
-
 
217
        unsigned long : 39; /**< Implementation dependent. */
-
 
218
        unsigned nf : 1;    /**< Non-faulting load. */
-
 
219
        unsigned asi : 8;   /**< ASI. */
-
 
220
        unsigned tm : 1;    /**< I-TLB miss. */
-
 
221
        unsigned : 3;       /**< Reserved. */
-
 
222
        unsigned ft : 5;    /**< Fault type. */
-
 
223
#endif
137
        unsigned e : 1;     /**< Side-effect bit. */
224
        unsigned e : 1;     /**< Side-effect bit. */
138
        unsigned ct : 2;    /**< Context Register selection. */
225
        unsigned ct : 2;    /**< Context Register selection. */
139
        unsigned pr : 1;    /**< Privilege bit. */
226
        unsigned pr : 1;    /**< Privilege bit. */
140
        unsigned w : 1;     /**< Write bit. */
227
        unsigned w : 1;     /**< Write bit. */
141
        unsigned ow : 1;    /**< Overwrite bit. */
228
        unsigned ow : 1;    /**< Overwrite bit. */
142
        unsigned fv : 1;    /**< Fault Valid bit. */
229
        unsigned fv : 1;    /**< Fault Valid bit. */
143
    } __attribute__ ((packed));
230
    } __attribute__ ((packed));
144
};
231
};
145
typedef union tlb_sfsr_reg tlb_sfsr_reg_t;
232
typedef union tlb_sfsr_reg tlb_sfsr_reg_t;
146
 
233
 
-
 
234
#if defined (US3)
-
 
235
 
-
 
236
/*
-
 
237
 * Functions for determining the number of entries in TLBs. They either return
-
 
238
 * a constant value or a value based on the CPU autodetection.
-
 
239
 */
-
 
240
 
-
 
241
/**
-
 
242
 * Determine the number of entries in the DMMU's small TLB.
-
 
243
 */
-
 
244
static inline uint16_t tlb_dsmall_size(void)
-
 
245
{
-
 
246
    return 16;
-
 
247
}
-
 
248
 
-
 
249
/**
-
 
250
 * Determine the number of entries in each DMMU's big TLB.
-
 
251
 */
-
 
252
static inline uint16_t tlb_dbig_size(void)
-
 
253
{
-
 
254
    return 512;
-
 
255
}
-
 
256
 
-
 
257
/**
-
 
258
 * Determine the number of entries in the IMMU's small TLB.
-
 
259
 */
-
 
260
static inline uint16_t tlb_ismall_size(void)
-
 
261
{
-
 
262
    return 16;
-
 
263
}
-
 
264
 
-
 
265
/**
-
 
266
 * Determine the number of entries in the IMMU's big TLB.
-
 
267
 */
-
 
268
static inline uint16_t tlb_ibig_size(void)
-
 
269
{
-
 
270
    if (((ver_reg_t) ver_read()).impl == IMPL_ULTRASPARCIV_PLUS)
-
 
271
        return 512;
-
 
272
    else
-
 
273
        return 128;
-
 
274
}
-
 
275
 
-
 
276
#endif
-
 
277
 
147
/** Read MMU Primary Context Register.
278
/** Read MMU Primary Context Register.
148
 *
279
 *
149
 * @return Current value of Primary Context Register.
280
 * @return      Current value of Primary Context Register.
150
 */
281
 */
151
static inline uint64_t mmu_primary_context_read(void)
282
static inline uint64_t mmu_primary_context_read(void)
152
{
283
{
153
    return asi_u64_read(ASI_DMMU, VA_PRIMARY_CONTEXT_REG);
284
    return asi_u64_read(ASI_DMMU, VA_PRIMARY_CONTEXT_REG);
154
}
285
}
155
 
286
 
156
/** Write MMU Primary Context Register.
287
/** Write MMU Primary Context Register.
157
 *
288
 *
158
 * @param v New value of Primary Context Register.
289
 * @param v     New value of Primary Context Register.
159
 */
290
 */
160
static inline void mmu_primary_context_write(uint64_t v)
291
static inline void mmu_primary_context_write(uint64_t v)
161
{
292
{
162
    asi_u64_write(ASI_DMMU, VA_PRIMARY_CONTEXT_REG, v);
293
    asi_u64_write(ASI_DMMU, VA_PRIMARY_CONTEXT_REG, v);
163
    flush_pipeline();
294
    flush_pipeline();
164
}
295
}
165
 
296
 
166
/** Read MMU Secondary Context Register.
297
/** Read MMU Secondary Context Register.
167
 *
298
 *
168
 * @return Current value of Secondary Context Register.
299
 * @return      Current value of Secondary Context Register.
169
 */
300
 */
170
static inline uint64_t mmu_secondary_context_read(void)
301
static inline uint64_t mmu_secondary_context_read(void)
171
{
302
{
172
    return asi_u64_read(ASI_DMMU, VA_SECONDARY_CONTEXT_REG);
303
    return asi_u64_read(ASI_DMMU, VA_SECONDARY_CONTEXT_REG);
173
}
304
}
174
 
305
 
175
/** Write MMU Primary Context Register.
306
/** Write MMU Primary Context Register.
176
 *
307
 *
177
 * @param v New value of Primary Context Register.
308
 * @param v     New value of Primary Context Register.
178
 */
309
 */
179
static inline void mmu_secondary_context_write(uint64_t v)
310
static inline void mmu_secondary_context_write(uint64_t v)
180
{
311
{
181
    asi_u64_write(ASI_DMMU, VA_SECONDARY_CONTEXT_REG, v);
312
    asi_u64_write(ASI_DMMU, VA_SECONDARY_CONTEXT_REG, v);
182
    flush_pipeline();
313
    flush_pipeline();
183
}
314
}
184
 
315
 
-
 
316
#if defined (US)
-
 
317
 
185
/** Read IMMU TLB Data Access Register.
318
/** Read IMMU TLB Data Access Register.
186
 *
319
 *
187
 * @param entry TLB Entry index.
320
 * @param entry     TLB Entry index.
188
 *
321
 *
189
 * @return Current value of specified IMMU TLB Data Access Register.
322
 * @return      Current value of specified IMMU TLB Data Access
-
 
323
 *          Register.
190
 */
324
 */
191
static inline uint64_t itlb_data_access_read(index_t entry)
325
static inline uint64_t itlb_data_access_read(index_t entry)
192
{
326
{
193
    tlb_data_access_addr_t reg;
327
    itlb_data_access_addr_t reg;
194
   
328
   
195
    reg.value = 0;
329
    reg.value = 0;
196
    reg.tlb_entry = entry;
330
    reg.tlb_entry = entry;
197
    return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value);
331
    return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value);
198
}
332
}
199
 
333
 
200
/** Write IMMU TLB Data Access Register.
334
/** Write IMMU TLB Data Access Register.
201
 *
335
 *
202
 * @param entry TLB Entry index.
336
 * @param entry     TLB Entry index.
203
 * @param value Value to be written.
337
 * @param value     Value to be written.
204
 */
338
 */
205
static inline void itlb_data_access_write(index_t entry, uint64_t value)
339
static inline void itlb_data_access_write(index_t entry, uint64_t value)
206
{
340
{
207
    tlb_data_access_addr_t reg;
341
    itlb_data_access_addr_t reg;
208
   
342
   
209
    reg.value = 0;
343
    reg.value = 0;
210
    reg.tlb_entry = entry;
344
    reg.tlb_entry = entry;
211
    asi_u64_write(ASI_ITLB_DATA_ACCESS_REG, reg.value, value);
345
    asi_u64_write(ASI_ITLB_DATA_ACCESS_REG, reg.value, value);
212
    flush_pipeline();
346
    flush_pipeline();
213
}
347
}
214
 
348
 
215
/** Read DMMU TLB Data Access Register.
349
/** Read DMMU TLB Data Access Register.
216
 *
350
 *
217
 * @param entry TLB Entry index.
351
 * @param entry     TLB Entry index.
218
 *
352
 *
219
 * @return Current value of specified DMMU TLB Data Access Register.
353
 * @return      Current value of specified DMMU TLB Data Access
-
 
354
 *          Register.
220
 */
355
 */
221
static inline uint64_t dtlb_data_access_read(index_t entry)
356
static inline uint64_t dtlb_data_access_read(index_t entry)
222
{
357
{
223
    tlb_data_access_addr_t reg;
358
    dtlb_data_access_addr_t reg;
224
   
359
   
225
    reg.value = 0;
360
    reg.value = 0;
226
    reg.tlb_entry = entry;
361
    reg.tlb_entry = entry;
227
    return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value);
362
    return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value);
228
}
363
}
229
 
364
 
230
/** Write DMMU TLB Data Access Register.
365
/** Write DMMU TLB Data Access Register.
231
 *
366
 *
232
 * @param entry TLB Entry index.
367
 * @param entry     TLB Entry index.
233
 * @param value Value to be written.
368
 * @param value     Value to be written.
234
 */
369
 */
235
static inline void dtlb_data_access_write(index_t entry, uint64_t value)
370
static inline void dtlb_data_access_write(index_t entry, uint64_t value)
236
{
371
{
237
    tlb_data_access_addr_t reg;
372
    dtlb_data_access_addr_t reg;
238
   
373
   
239
    reg.value = 0;
374
    reg.value = 0;
240
    reg.tlb_entry = entry;
375
    reg.tlb_entry = entry;
241
    asi_u64_write(ASI_DTLB_DATA_ACCESS_REG, reg.value, value);
376
    asi_u64_write(ASI_DTLB_DATA_ACCESS_REG, reg.value, value);
242
    membar();
377
    membar();
243
}
378
}
244
 
379
 
245
/** Read IMMU TLB Tag Read Register.
380
/** Read IMMU TLB Tag Read Register.
246
 *
381
 *
247
 * @param entry TLB Entry index.
382
 * @param entry     TLB Entry index.
248
 *
383
 *
249
 * @return Current value of specified IMMU TLB Tag Read Register.
384
 * @return      Current value of specified IMMU TLB Tag Read Register.
250
 */
385
 */
251
static inline uint64_t itlb_tag_read_read(index_t entry)
386
static inline uint64_t itlb_tag_read_read(index_t entry)
252
{
387
{
253
    tlb_tag_read_addr_t tag;
388
    itlb_tag_read_addr_t tag;
254
 
389
 
255
    tag.value = 0;
390
    tag.value = 0;
256
    tag.tlb_entry = entry;
391
    tag.tlb_entry = entry;
257
    return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value);
392
    return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value);
258
}
393
}
259
 
394
 
260
/** Read DMMU TLB Tag Read Register.
395
/** Read DMMU TLB Tag Read Register.
261
 *
396
 *
262
 * @param entry TLB Entry index.
397
 * @param entry     TLB Entry index.
263
 *
398
 *
264
 * @return Current value of specified DMMU TLB Tag Read Register.
399
 * @return      Current value of specified DMMU TLB Tag Read Register.
265
 */
400
 */
266
static inline uint64_t dtlb_tag_read_read(index_t entry)
401
static inline uint64_t dtlb_tag_read_read(index_t entry)
267
{
402
{
268
    tlb_tag_read_addr_t tag;
403
    dtlb_tag_read_addr_t tag;
269
 
404
 
270
    tag.value = 0;
405
    tag.value = 0;
271
    tag.tlb_entry = entry;
406
    tag.tlb_entry = entry;
272
    return asi_u64_read(ASI_DTLB_TAG_READ_REG, tag.value);
407
    return asi_u64_read(ASI_DTLB_TAG_READ_REG, tag.value);
273
}
408
}
274
 
409
 
-
 
410
#elif defined (US3)
-
 
411
 
-
 
412
 
-
 
413
/** Read IMMU TLB Data Access Register.
-
 
414
 *
-
 
415
 * @param tlb       TLB number (one of TLB_ISMALL or TLB_IBIG)
-
 
416
 * @param entry     TLB Entry index.
-
 
417
 *
-
 
418
 * @return      Current value of specified IMMU TLB Data Access
-
 
419
 *          Register.
-
 
420
 */
-
 
421
static inline uint64_t itlb_data_access_read(int tlb, index_t entry)
-
 
422
{
-
 
423
    itlb_data_access_addr_t reg;
-
 
424
   
-
 
425
    reg.value = 0;
-
 
426
    reg.tlb_number = tlb;
-
 
427
    reg.local_tlb_entry = entry;
-
 
428
    return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value);
-
 
429
}
-
 
430
 
-
 
431
/** Write IMMU TLB Data Access Register.
-
 
432
 * @param tlb       TLB number (one of TLB_ISMALL or TLB_IBIG)
-
 
433
 * @param entry     TLB Entry index.
-
 
434
 * @param value     Value to be written.
-
 
435
 */
-
 
436
static inline void itlb_data_access_write(int tlb, index_t entry,
-
 
437
    uint64_t value)
-
 
438
{
-
 
439
    itlb_data_access_addr_t reg;
-
 
440
   
-
 
441
    reg.value = 0;
-
 
442
    reg.tlb_number = tlb;
-
 
443
    reg.local_tlb_entry = entry;
-
 
444
    asi_u64_write(ASI_ITLB_DATA_ACCESS_REG, reg.value, value);
-
 
445
    flush_pipeline();
-
 
446
}
-
 
447
 
-
 
448
/** Read DMMU TLB Data Access Register.
-
 
449
 *
-
 
450
 * @param tlb       TLB number (one of TLB_DSMALL, TLB_DBIG, TLB_DBIG)
-
 
451
 * @param entry     TLB Entry index.
-
 
452
 *
-
 
453
 * @return      Current value of specified DMMU TLB Data Access
-
 
454
 *          Register.
-
 
455
 */
-
 
456
static inline uint64_t dtlb_data_access_read(int tlb, index_t entry)
-
 
457
{
-
 
458
    dtlb_data_access_addr_t reg;
-
 
459
   
-
 
460
    reg.value = 0;
-
 
461
    reg.tlb_number = tlb;
-
 
462
    reg.local_tlb_entry = entry;
-
 
463
    return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value);
-
 
464
}
-
 
465
 
-
 
466
/** Write DMMU TLB Data Access Register.
-
 
467
 *
-
 
468
 * @param tlb       TLB number (one of TLB_DSMALL, TLB_DBIG_0, TLB_DBIG_1)  
-
 
469
 * @param entry     TLB Entry index.
-
 
470
 * @param value     Value to be written.
-
 
471
 */
-
 
472
static inline void dtlb_data_access_write(int tlb, index_t entry,
-
 
473
    uint64_t value)
-
 
474
{
-
 
475
    dtlb_data_access_addr_t reg;
-
 
476
   
-
 
477
    reg.value = 0;
-
 
478
    reg.tlb_number = tlb;
-
 
479
    reg.local_tlb_entry = entry;
-
 
480
    asi_u64_write(ASI_DTLB_DATA_ACCESS_REG, reg.value, value);
-
 
481
    membar();
-
 
482
}
-
 
483
 
-
 
484
/** Read IMMU TLB Tag Read Register.
-
 
485
 *
-
 
486
 * @param tlb       TLB number (one of TLB_ISMALL or TLB_IBIG)
-
 
487
 * @param entry     TLB Entry index.
-
 
488
 *
-
 
489
 * @return      Current value of specified IMMU TLB Tag Read Register.
-
 
490
 */
-
 
491
static inline uint64_t itlb_tag_read_read(int tlb, index_t entry)
-
 
492
{
-
 
493
    itlb_tag_read_addr_t tag;
-
 
494
 
-
 
495
    tag.value = 0;
-
 
496
    tag.tlb_number = tlb;
-
 
497
    tag.local_tlb_entry = entry;
-
 
498
    return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value);
-
 
499
}
-
 
500
 
-
 
501
/** Read DMMU TLB Tag Read Register.
-
 
502
 *
-
 
503
 * @param tlb       TLB number (one of TLB_DSMALL, TLB_DBIG_0, TLB_DBIG_1)
-
 
504
 * @param entry     TLB Entry index.
-
 
505
 *
-
 
506
 * @return      Current value of specified DMMU TLB Tag Read Register.
-
 
507
 */
-
 
508
static inline uint64_t dtlb_tag_read_read(int tlb, index_t entry)
-
 
509
{
-
 
510
    dtlb_tag_read_addr_t tag;
-
 
511
 
-
 
512
    tag.value = 0;
-
 
513
    tag.tlb_number = tlb;
-
 
514
    tag.local_tlb_entry = entry;
-
 
515
    return asi_u64_read(ASI_DTLB_TAG_READ_REG, tag.value);
-
 
516
}
-
 
517
 
-
 
518
#endif
-
 
519
 
-
 
520
 
275
/** Write IMMU TLB Tag Access Register.
521
/** Write IMMU TLB Tag Access Register.
276
 *
522
 *
277
 * @param v Value to be written.
523
 * @param v     Value to be written.
278
 */
524
 */
279
static inline void itlb_tag_access_write(uint64_t v)
525
static inline void itlb_tag_access_write(uint64_t v)
280
{
526
{
281
    asi_u64_write(ASI_IMMU, VA_IMMU_TAG_ACCESS, v);
527
    asi_u64_write(ASI_IMMU, VA_IMMU_TAG_ACCESS, v);
282
    flush_pipeline();
528
    flush_pipeline();
283
}
529
}
284
 
530
 
285
/** Read IMMU TLB Tag Access Register.
531
/** Read IMMU TLB Tag Access Register.
286
 *
532
 *
287
 * @return Current value of IMMU TLB Tag Access Register.
533
 * @return      Current value of IMMU TLB Tag Access Register.
288
 */
534
 */
289
static inline uint64_t itlb_tag_access_read(void)
535
static inline uint64_t itlb_tag_access_read(void)
290
{
536
{
291
    return asi_u64_read(ASI_IMMU, VA_IMMU_TAG_ACCESS);
537
    return asi_u64_read(ASI_IMMU, VA_IMMU_TAG_ACCESS);
292
}
538
}
293
 
539
 
294
/** Write DMMU TLB Tag Access Register.
540
/** Write DMMU TLB Tag Access Register.
295
 *
541
 *
296
 * @param v Value to be written.
542
 * @param v     Value to be written.
297
 */
543
 */
298
static inline void dtlb_tag_access_write(uint64_t v)
544
static inline void dtlb_tag_access_write(uint64_t v)
299
{
545
{
300
    asi_u64_write(ASI_DMMU, VA_DMMU_TAG_ACCESS, v);
546
    asi_u64_write(ASI_DMMU, VA_DMMU_TAG_ACCESS, v);
301
    membar();
547
    membar();
302
}
548
}
303
 
549
 
304
/** Read DMMU TLB Tag Access Register.
550
/** Read DMMU TLB Tag Access Register.
305
 *
551
 *
306
 * @return Current value of DMMU TLB Tag Access Register.
552
 * @return      Current value of DMMU TLB Tag Access Register.
307
 */
553
 */
308
static inline uint64_t dtlb_tag_access_read(void)
554
static inline uint64_t dtlb_tag_access_read(void)
309
{
555
{
310
    return asi_u64_read(ASI_DMMU, VA_DMMU_TAG_ACCESS);
556
    return asi_u64_read(ASI_DMMU, VA_DMMU_TAG_ACCESS);
311
}
557
}
312
 
558
 
313
 
559
 
314
/** Write IMMU TLB Data in Register.
560
/** Write IMMU TLB Data in Register.
315
 *
561
 *
316
 * @param v Value to be written.
562
 * @param v     Value to be written.
317
 */
563
 */
318
static inline void itlb_data_in_write(uint64_t v)
564
static inline void itlb_data_in_write(uint64_t v)
319
{
565
{
320
    asi_u64_write(ASI_ITLB_DATA_IN_REG, 0, v);
566
    asi_u64_write(ASI_ITLB_DATA_IN_REG, 0, v);
321
    flush_pipeline();
567
    flush_pipeline();
322
}
568
}
323
 
569
 
324
/** Write DMMU TLB Data in Register.
570
/** Write DMMU TLB Data in Register.
325
 *
571
 *
326
 * @param v Value to be written.
572
 * @param v     Value to be written.
327
 */
573
 */
328
static inline void dtlb_data_in_write(uint64_t v)
574
static inline void dtlb_data_in_write(uint64_t v)
329
{
575
{
330
    asi_u64_write(ASI_DTLB_DATA_IN_REG, 0, v);
576
    asi_u64_write(ASI_DTLB_DATA_IN_REG, 0, v);
331
    membar();
577
    membar();
332
}
578
}
333
 
579
 
334
/** Read ITLB Synchronous Fault Status Register.
580
/** Read ITLB Synchronous Fault Status Register.
335
 *
581
 *
336
 * @return Current content of I-SFSR register.
582
 * @return      Current content of I-SFSR register.
337
 */
583
 */
338
static inline uint64_t itlb_sfsr_read(void)
584
static inline uint64_t itlb_sfsr_read(void)
339
{
585
{
340
    return asi_u64_read(ASI_IMMU, VA_IMMU_SFSR);
586
    return asi_u64_read(ASI_IMMU, VA_IMMU_SFSR);
341
}
587
}
342
 
588
 
343
/** Write ITLB Synchronous Fault Status Register.
589
/** Write ITLB Synchronous Fault Status Register.
344
 *
590
 *
345
 * @param v New value of I-SFSR register.
591
 * @param v     New value of I-SFSR register.
346
 */
592
 */
347
static inline void itlb_sfsr_write(uint64_t v)
593
static inline void itlb_sfsr_write(uint64_t v)
348
{
594
{
349
    asi_u64_write(ASI_IMMU, VA_IMMU_SFSR, v);
595
    asi_u64_write(ASI_IMMU, VA_IMMU_SFSR, v);
350
    flush_pipeline();
596
    flush_pipeline();
351
}
597
}
352
 
598
 
353
/** Read DTLB Synchronous Fault Status Register.
599
/** Read DTLB Synchronous Fault Status Register.
354
 *
600
 *
355
 * @return Current content of D-SFSR register.
601
 * @return      Current content of D-SFSR register.
356
 */
602
 */
357
static inline uint64_t dtlb_sfsr_read(void)
603
static inline uint64_t dtlb_sfsr_read(void)
358
{
604
{
359
    return asi_u64_read(ASI_DMMU, VA_DMMU_SFSR);
605
    return asi_u64_read(ASI_DMMU, VA_DMMU_SFSR);
360
}
606
}
361
 
607
 
362
/** Write DTLB Synchronous Fault Status Register.
608
/** Write DTLB Synchronous Fault Status Register.
363
 *
609
 *
364
 * @param v New value of D-SFSR register.
610
 * @param v     New value of D-SFSR register.
365
 */
611
 */
366
static inline void dtlb_sfsr_write(uint64_t v)
612
static inline void dtlb_sfsr_write(uint64_t v)
367
{
613
{
368
    asi_u64_write(ASI_DMMU, VA_DMMU_SFSR, v);
614
    asi_u64_write(ASI_DMMU, VA_DMMU_SFSR, v);
369
    membar();
615
    membar();
370
}
616
}
371
 
617
 
372
/** Read DTLB Synchronous Fault Address Register.
618
/** Read DTLB Synchronous Fault Address Register.
373
 *
619
 *
374
 * @return Current content of D-SFAR register.
620
 * @return      Current content of D-SFAR register.
375
 */
621
 */
376
static inline uint64_t dtlb_sfar_read(void)
622
static inline uint64_t dtlb_sfar_read(void)
377
{
623
{
378
    return asi_u64_read(ASI_DMMU, VA_DMMU_SFAR);
624
    return asi_u64_read(ASI_DMMU, VA_DMMU_SFAR);
379
}
625
}
380
 
626
 
381
/** Perform IMMU TLB Demap Operation.
627
/** Perform IMMU TLB Demap Operation.
382
 *
628
 *
383
 * @param type Selects between context and page demap.
629
 * @param type      Selects between context and page demap (and entire MMU
-
 
630
 *          demap on US3).
384
 * @param context_encoding Specifies which Context register has Context ID for
631
 * @param context_encoding Specifies which Context register has Context ID for
385
 *  demap.
632
 *          demap.
386
 * @param page Address which is on the page to be demapped.
633
 * @param page      Address which is on the page to be demapped.
387
 */
634
 */
388
static inline void itlb_demap(int type, int context_encoding, uintptr_t page)
635
static inline void itlb_demap(int type, int context_encoding, uintptr_t page)
389
{
636
{
390
    tlb_demap_addr_t da;
637
    tlb_demap_addr_t da;
391
    page_address_t pg;
638
    page_address_t pg;
Line 395... Line 642...
395
   
642
   
396
    da.type = type;
643
    da.type = type;
397
    da.context = context_encoding;
644
    da.context = context_encoding;
398
    da.vpn = pg.vpn;
645
    da.vpn = pg.vpn;
399
   
646
   
400
    asi_u64_write(ASI_IMMU_DEMAP, da.value, 0); /* da.value is the
-
 
401
                             * address within the
647
    /* da.value is the address within the ASI */
402
                             * ASI */
648
    asi_u64_write(ASI_IMMU_DEMAP, da.value, 0);
-
 
649
 
403
    flush_pipeline();
650
    flush_pipeline();
404
}
651
}
405
 
652
 
406
/** Perform DMMU TLB Demap Operation.
653
/** Perform DMMU TLB Demap Operation.
407
 *
654
 *
408
 * @param type Selects between context and page demap.
655
 * @param type      Selects between context and page demap (and entire MMU
-
 
656
 *          demap on US3).
409
 * @param context_encoding Specifies which Context register has Context ID for
657
 * @param context_encoding Specifies which Context register has Context ID for
410
 *   demap.
658
 *          demap.
411
 * @param page Address which is on the page to be demapped.
659
 * @param page      Address which is on the page to be demapped.
412
 */
660
 */
413
static inline void dtlb_demap(int type, int context_encoding, uintptr_t page)
661
static inline void dtlb_demap(int type, int context_encoding, uintptr_t page)
414
{
662
{
415
    tlb_demap_addr_t da;
663
    tlb_demap_addr_t da;
416
    page_address_t pg;
664
    page_address_t pg;
Line 420... Line 668...
420
   
668
   
421
    da.type = type;
669
    da.type = type;
422
    da.context = context_encoding;
670
    da.context = context_encoding;
423
    da.vpn = pg.vpn;
671
    da.vpn = pg.vpn;
424
   
672
   
425
    asi_u64_write(ASI_DMMU_DEMAP, da.value, 0); /* da.value is the
-
 
426
                             * address within the
673
    /* da.value is the address within the ASI */
427
                             * ASI */
674
    asi_u64_write(ASI_DMMU_DEMAP, da.value, 0);
-
 
675
 
428
    membar();
676
    membar();
429
}
677
}
430
 
678
 
431
extern void fast_instruction_access_mmu_miss(unative_t unused, istate_t *istate);
679
extern void fast_instruction_access_mmu_miss(unative_t, istate_t *);
432
extern void fast_data_access_mmu_miss(tlb_tag_access_reg_t tag, istate_t *istate);
680
extern void fast_data_access_mmu_miss(tlb_tag_access_reg_t, istate_t *);
433
extern void fast_data_access_protection(tlb_tag_access_reg_t tag , istate_t *istate);
681
extern void fast_data_access_protection(tlb_tag_access_reg_t , istate_t *);
434
 
682
 
435
extern void dtlb_insert_mapping(uintptr_t page, uintptr_t frame, int pagesize, bool locked, bool cacheable);
683
extern void dtlb_insert_mapping(uintptr_t, uintptr_t, int, bool, bool);
436
 
684
 
437
extern void dump_sfsr_and_sfar(void);
685
extern void dump_sfsr_and_sfar(void);
438
 
686
 
439
#endif /* !def __ASM__ */
687
#endif /* !def __ASM__ */
440
 
688